CN110677021B - Output drive circuit of anti ground bounce noise - Google Patents
Output drive circuit of anti ground bounce noise Download PDFInfo
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- CN110677021B CN110677021B CN201910896616.4A CN201910896616A CN110677021B CN 110677021 B CN110677021 B CN 110677021B CN 201910896616 A CN201910896616 A CN 201910896616A CN 110677021 B CN110677021 B CN 110677021B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
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Abstract
The invention relates to an output driving circuit for resisting ground bounce noise, and belongs to the field of semiconductor integrated circuits. The output driving circuit introduces a certain time delay in the switching process of the output driving PMOS tube and the NMOS tube by adding a logic circuit to avoid simultaneous conduction, and the circuits have different driving capacities in the static state and the switching process by controlling the driving tubes with different width-length ratios to be sequentially started. The output driving circuit can effectively reduce the ground bounce noise and has higher driving capability.
Description
Technical Field
The invention relates to an output driving circuit for resisting ground bounce noise, and belongs to the field of semiconductor integrated circuits.
Background
With the integration of the CMOS integrated circuit becoming higher and higher, the operating frequency becomes faster and faster, the number of input/output pins also becomes higher and the noise of the synchronous switch also becomes larger. The synchronous switching noise not only causes the jitter of the power supply and the ground plane of the chip, but also affects the delay and distortion of other output signals, and even worse, the circuit cannot work normally if the maximum amplitude of the synchronous switching noise exceeds the threshold voltage of a transistor. The output unit is a main noise source of synchronous switching noise, and the generated noise is large because the switching current flowing through the ground pin of the chip changes very rapidly and the package parasitic inductance is also large.
Ground bounce refers to voltage oscillation generated between a reference ground plane of a chip and a ground pin of a shell, and is caused by current spikes flowing through parasitic inductance of the shell. The principle of the ground bounce effect is shown in FIG. 1, wherein LVDD、LGND、L1、L2The parasitic inductor introduced for chip packaging is composed of a shell pin, a bonding wire and a chip PAD inductor. RON1And RON2The on-resistance of NMOS tubes of the data bus port and other control signal ports respectively, C1、C2Respectively its load capacitance.
When the data bus DBx (x is 0,1, …, n) pin output changes from "1" to "0", the charge on the bus capacitor is drained through DBx pull-down NMOS, the current magnitude is I CdV/dt, and the change in current in turn causes a voltage drop V across the lead inductanceGBLdI/dt, resulting in disturbances at the chip ground plane. When the control signal CB outputs a low level, a low on-resistance (R) is passed between the CB and the chip groundON2) The ground noise of the chip directly causes disturbance on the CB pin, and seriously influences the work of a rear-stage circuit. The effect of a data bus pinout change from "0" to "1" on the chip supply voltage is similar. When a plurality of output ends are synchronously turned, the ground bounce effect is obvious.
As shown in fig. 2, in the conventional tri-state output driving circuit, when the output level is switched, the PMOS output transistor PM and the NMOS output transistor NM are turned on at the same time within a certain time, which not only causes a large current change rate, resulting in a large ground bounce noise, but also generates a large power consumption.
Disclosure of Invention
The technical problem solved by the invention is as follows: the defects in the prior art are overcome, the ground bounce noise resisting output driving circuit with high driving capacity is provided, and the ground bounce noise resisting capacity of the output driving unit is improved.
The technical scheme of the invention is as follows: an anti-ground bounce noise output driving circuit comprises a first inverter INV1, a first NAND gate NAND1, a first delay line DLY1, a first NOR gate NOR1, a second inverter INV2, a third NOR gate NOR3, a third delay line DLY3, a second NAND gate 2, a fourth inverter INV4, a first PMOS tube P1 and a first NMOS tube N1;
the input data terminal D is simultaneously connected with one input terminal of the first NAND gate NAND1 and one input terminal of the third NOR gate NOR 3; the output enable control terminal OEN connects an input terminal of the first inverter INV1 and another input terminal of the third NOR gate NOR 3; the output end of the first inverter INV1 is connected to the other input end of the first NAND gate NAND 1; the output end of the first NAND gate NAND1 is connected with the input end of a first delay line DLY1 and one input end of a first NOR gate NOR1, the output end of the first delay line DLY1 is connected with the other input end of the first NOR gate NOR1, the output end of the first NOR gate NOR1 is connected with the input end of a second inverter INV2, and the output end of the second inverter INV2 is connected with the gate end of a first PMOS transistor P1;
the output terminal of the third NOR gate NOR3 is connected to both the input terminal of the third delay line DLY3 and one input terminal of the second NAND gate NAND 2; the output end of the third delay line DLY3 is connected with the other input end of the second NAND gate NAND 2; the output end of the second NAND gate NAND2 is connected with the input end of the fourth inverter INV 4; the output end of the fourth inverter INV4 is connected to the gate end of the first NMOS transistor N1; the source end of the first PMOS pipe P1 is connected with a power supply; the source end of the first NMOS transistor N1 is grounded; the drain terminal of the first PMOS transistor P1 and the drain terminal of the first NMOS transistor N1 are connected together as the output terminal Q of the output driving circuit.
The delay times of the first delay line DLY1 and the third delay line DLY3 are the same.
The delay time of the first delay line DLY1 and the third delay line DLY3 does not exceed 1/10 of the duty cycle of the output driver circuit.
The output driving circuit further comprises a second delay line DLY2, a second NOR gate NOR2, a third inverter INV3, a fourth delay line DLY4, a third NAND gate NAND3, a fifth inverter INV5, a second PMOS tube P2 and a second NMOS tube N2;
the input end of the second delay line DLY2 is connected with the gate end of the first PMOS tube P1; the output end of the second delay line DLY2 and the output end of the first NAND gate NAND1 are respectively connected with the input end of a second NOR gate NOR2, the output end of the second NOR gate NOR2 is connected with the input end of a third inverter INV3, and the output end of the third inverter INV3 is connected with the gate end of a second PMOS transistor P2;
the input end of the fourth delay line DLY4 is connected with the gate end of the first NMOS transistor N1; the output end of the fourth delay line DLY4 and the output end of the third NOR gate NOR3 are respectively connected with the input end of a third NAND gate NAND3, the output end of the third NAND gate NAND3 is connected with the input end of a fifth inverter INV5, and the output end of the fifth inverter INV5 is connected with the gate end of a second NMOS transistor N2;
the source end of the second PMOS pipe P2 is connected with a power supply; the source end of the second NMOS transistor N2 is grounded; the drain terminal of the second PMOS transistor P2 and the drain terminal of the second NMOS transistor N2 are connected to the output terminal Q of the output driving circuit.
The delay times of the second delay line DLY2 and the fourth delay line DLY4 are the same.
The width-to-length ratio of the second PMOS pipe P2 is larger than that of the first PMOS pipe P1.
The width-to-length ratio of the second NMOS transistor N2 is greater than that of the first NMOS transistor N1.
The width-to-length ratios of the first PMOS tube P1, the first NMOS tube N1, the second PMOS tube P2 and the second NMOS tube N2 meet the following conditions:
the second inverter INV2 has the same structure as the third inverter INV3, and comprises a third PMOS transistor P3, a third NMOS transistor N3 and a fourth NMOS transistor N4;
the source end of the third PMOS pipe P3 is connected with a power supply; the drain terminal of the third PMOS transistor P3 is connected to the drain terminal of the third NMOS transistor N3, the source terminal of the third NMOS transistor N3 is connected to the drain terminal of the fourth NMOS transistor N4, and the source terminal of the fourth NMOS transistor N4 is grounded.
The fourth inverter INV4 has the same structure as the fifth inverter INV5, and comprises a fourth PMOS transistor P4, a fifth PMOS transistor P5 and a fifth NMOS transistor N5;
the source end of the fourth PMOS pipe P4 is connected with a power supply; the drain terminal of the fourth PMOS transistor P4 is connected to the source terminal of the fifth PMOS transistor P5, the drain terminal of the fifth PMOS transistor P5 is connected to the drain terminal of the fifth NMOS transistor N5, and the source terminal of the fifth NMOS transistor N5 is grounded.
Compared with the prior art, the invention has the beneficial effects that:
(1) according to the invention, through adding the logic circuit, a certain time delay is introduced in the switching process of the output drive PMOS tube and the NMOS tube, so that the output drive PMOS tube and the NMOS tube are ensured to be opened at the same time, the dynamic current is reduced, and the ground bounce noise resistance of the output drive unit is improved.
(2) The invention adds the primary output drive PMOS tube and the NMOS tube on the basis of the primary output drive PMOS tube and the NMOS tube, thereby improving the drive capability of the output drive circuit;
(3) the PMOS tube and the NMOS tube are driven by two stages of outputs with different width-length ratios, so that the driving capacities of output ports in static states and switching processes are different, and the synchronous switching noise is reduced by reducing the current change rate.
(4) According to the invention, a weak pull-down structure of connecting 2 NMOS tubes in series is adopted in the phase inverter of the front stage of the grid end of the output drive PMOS tube, and a weak pull-up structure of connecting 2 PMOS tubes in series is adopted in the phase inverter of the front stage of the grid end of the output drive NMOS tube, so that the current change rate is further reduced.
Drawings
FIG. 1 is a schematic diagram of the ground bounce effect;
FIG. 2 is a block diagram of a conventional tri-state output driver circuit;
FIG. 3 is a structural diagram of an output driving circuit with high driving capability to resist ground bounce noise according to an embodiment of the present invention;
FIG. 4 is a circuit configuration diagram of inverters INV2 and INV3 according to an embodiment of the present invention;
fig. 5 is a circuit configuration diagram of inverters INV4 and INV5 according to an embodiment of the present invention;
FIG. 6 shows the input waveforms at the gate terminals of the output driving PMOS transistor and the NMOS transistor according to the embodiment of the present invention.
Detailed Description
The invention is further illustrated by the following examples.
In order to meet the requirement of high output driving capability, a PMOS (P-channel metal oxide semiconductor) tube and an NMOS (N-channel metal oxide semiconductor) tube in an output unit usually adopt devices with large width-length ratio, and during output level conversion, the PMOS tube and the NMOS tube have short simultaneous conduction phenomenon, so that the generated dynamic current is very large.
In order to avoid the above situation, the present invention provides an output driving circuit resistant to ground bounce noise. As shown in fig. 3, the driving circuit is composed of a first inverter INV1, a first NAND gate NAND1, a first delay line DLY1, a first NOR gate NOR1, a second inverter INV2, a third NOR gate NOR3, a third delay line DLY3, a second NAND gate NAND2, a fourth inverter INV4, a first PMOS transistor P1, a first NMOS transistor N1, a second delay line DLY2, a second NOR gate NOR2, a third inverter INV3, a fourth delay line DLY4, a third NAND gate 3, a fifth inverter INV5, a second PMOS transistor P2, and a second NMOS transistor N2.
The input data terminal D is simultaneously connected with one input terminal of the first NAND gate NAND1 and one input terminal of the third NOR gate NOR 3; the output enable control terminal OEN connects an input terminal of the first inverter INV1 and another input terminal of the third NOR gate NOR 3; the output end of the first inverter INV1 is connected to the other input end of the first NAND gate NAND 1; the output end of the first NAND gate NAND1 is connected with the input end of a first delay line DLY1 and one input end of a first NOR gate NOR1, the output end of the first delay line DLY1 is connected with the other input end of the first NOR gate NOR1, the output end of the first NOR gate NOR1 is connected with the input end of a second inverter INV2, and the output end of the second inverter INV2 is connected with the gate end of a first PMOS transistor P1;
the output terminal of the third NOR gate NOR3 is connected to both the input terminal of the third delay line DLY3 and one input terminal of the second NAND gate NAND 2; the output end of the third delay line DLY3 is connected with the other input end of the second NAND gate NAND 2; the output end of the second NAND gate NAND2 is connected with the input end of the fourth inverter INV 4; the output end of the fourth inverter INV4 is connected to the gate end of the first NMOS transistor N1;
the input end of the second delay line DLY2 is connected with the gate end of the first PMOS tube P1; the output end of the second delay line DLY2 and the output end of the first NAND gate NAND1 are respectively connected with the input end of a second NOR gate NOR2, the output end of the second NOR gate NOR2 is connected with the input end of a third inverter INV3, and the output end of the third inverter INV3 is connected with the gate end of a second PMOS transistor P2;
the input end of the fourth delay line DLY4 is connected with the gate end of the first NMOS transistor N1; the output end of the fourth delay line DLY4 and the output end of the third NOR gate NOR3 are respectively connected with the input end of a third NAND gate NAND3, the output end of the third NAND gate NAND3 is connected with the input end of a fifth inverter INV5, and the output end of the fifth inverter INV5 is connected with the gate end of a second NMOS transistor N2;
the source end of the first PMOS pipe P1 is connected with a power supply; the source end of the first NMOS transistor N1 is grounded; the source end of the second PMOS pipe P2 is connected with a power supply; the source end of the second NMOS transistor N2 is grounded; the drain terminal of the first PMOS transistor P1, the drain terminal of the first NMOS transistor N1, the drain terminal of the second PMOS transistor P2 and the drain terminal of the second NMOS transistor N2 are connected together as the output terminal Q of the output driving circuit.
In order to ensure the symmetry of the rising time and the falling time of the output data terminal Q, the delay times of the first delay line DLY1 and the third delay line DLY3 are preferably the same.
In order to meet the requirement of the circuit operating frequency, the delay time of the first delay line DLY1 and the third delay line DLY3 does not exceed 1/10 of the operating period of the output driving circuit as a preferable scheme.
In order to ensure the symmetry of the rising time and the falling time of the output data terminal Q, the delay time of the second delay line DLY2 and the delay time of the fourth delay line DLY4 are preferably the same.
In order to ensure sufficient driving capability in the case of static output "1", the width-to-length ratio of the second PMOS transistor P2 is preferably greater than the width-to-length ratio of the first PMOS transistor P1.
In order to ensure sufficient driving capability for the static output "0", preferably, the width-to-length ratio of the second NMOS transistor N2 is greater than the width-to-length ratio of the first NMOS transistor N1.
In order to ensure that the output driving circuit has a stable flip threshold, preferably, the width-to-length ratios of the first PMOS transistor P1, the first NMOS transistor N1, the second PMOS transistor P2, and the second NMOS transistor N2 satisfy the following conditions:
in order to reduce the rate of change of current when the output is inverted from "0" to "1", preferably, the second inverter INV2 has the same structure as the third inverter INV3, and includes a third PMOS transistor P3, a third NMOS transistor N3 and a fourth NMOS transistor N4; the source end of the third PMOS pipe P3 is connected with a power supply; the drain terminal of the third PMOS transistor P3 is connected to the drain terminal of the third NMOS transistor N3, the source terminal of the third NMOS transistor N3 is connected to the drain terminal of the fourth NMOS transistor N4, and the source terminal of the fourth NMOS transistor N4 is grounded, as shown in fig. 4.
Also, in order to reduce the rate of change of the current when the output is inverted from "1" to "0", preferably, the fourth inverter INV4 has the same structure as the fifth inverter INV5, and includes a fourth PMOS transistor P4, a fifth PMOS transistor P5, and a fifth NMOS transistor N5; the source end of the fourth PMOS pipe P4 is connected with a power supply; the drain terminal of the fourth PMOS transistor P4 is connected to the source terminal of the fifth PMOS transistor P5, the drain terminal of the fifth PMOS transistor P5 is connected to the drain terminal of the fifth NMOS transistor N5, and the source terminal of the fifth NMOS transistor N5 is grounded, as shown in fig. 5. .
Example (b):
the operation principle will be described below with reference to the gate-side input waveforms of the output driving PMOS transistor and the NMOS transistor in an embodiment of the present invention.
The circuit structure in fig. 3 is adopted to generate the gate end driving signals PG1 and NG1 shown in fig. 6, so that the PMOS transistor and the NMOS transistor are not turned on at the same time.
In order to reduce the ground bounce noise, the output driving PMOS tube is divided into a first PMOS tube P1 and a second PMOS tube P2, and the output driving NMOS tube is divided into a first NMOS tube N1 and a second NMOS tube N2, wherein the width-to-length ratio of the first PMOS tube P1 is smaller than that of the second PMOS tube P2, and the width-to-length ratio of the first NMOS tube N1 is smaller than that of the second NMOS tube N2. When the output end Q is turned over from '1' to '0', the first PMOS tube P1 and the second PMOS tube P2 are turned off at the moment t1, the first NMOS tube N1 is turned on at the moment t2, the pull-down capacity is weak, the current change rate is small, and then the second NMOS tube N2 is turned on at the moment t3, so that the driving capacity is enough when the static output is '0'. When the output end Q is turned over from '0' to '1', the first NMOS tube N1 and the second NMOS tube N2 are turned off at the moment t5, the first PMOS tube P1 is turned on at the moment t6, the pull-up capacity is weak, the current change rate is small, and then the second PMOS tube P2 is turned on at the moment t7, so that sufficient driving capacity is guaranteed when the static output is '1'.
In addition, in the design of the inverters INV2 and INV3, the width-to-length ratio of the NMOS transistors is reduced by serially connecting 2 NMOS transistors, so that the pull-down capability of the inverters is weakened, the opening speeds of the first PMOS transistor P1 and the second PMOS transistor P2 are reduced, and the purpose of reducing the current change rate is achieved. In the design of the inverters INV4 and INV5, the width-to-length ratio of the PMOS tubes is reduced by serially connecting 2 PMOS tubes, so that the pull-up capability of the inverters is weakened, the opening speeds of the first NMOS tube N1 and the second NMOS tube N2 are reduced, and the purpose of reducing the current change rate is achieved.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications of the present invention without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above.
Claims (9)
1. An anti-ground bounce noise output driving circuit is characterized by comprising a first inverter INV1, a first NAND gate NAND1, a first delay line DLY1, a first NOR gate NOR1, a second inverter INV2, a third NOR gate NOR3, a third delay line DLY3, a second NAND gate 2, a fourth inverter INV4, a first PMOS tube P1, a first NMOS tube N1, a second delay line DLY2, a second NOR gate NOR2, a third inverter INV3, a fourth delay line DLY4, a third NAND gate 3, a fifth inverter INV5, a second NMOS tube P2 and a second NMOS tube N2;
the input data terminal D is simultaneously connected with one input terminal of the first NAND gate NAND1 and one input terminal of the third NOR gate NOR 3; the output enable control terminal OEN connects an input terminal of the first inverter INV1 and another input terminal of the third NOR gate NOR 3; the output end of the first inverter INV1 is connected to the other input end of the first NAND gate NAND 1; the output end of the first NAND gate NAND1 is connected with the input end of a first delay line DLY1 and one input end of a first NOR gate NOR1, the output end of the first delay line DLY1 is connected with the other input end of the first NOR gate NOR1, the output end of the first NOR gate NOR1 is connected with the input end of a second inverter INV2, and the output end of the second inverter INV2 is connected with the gate end of a first PMOS transistor P1;
the output terminal of the third NOR gate NOR3 is connected to both the input terminal of the third delay line DLY3 and one input terminal of the second NAND gate NAND 2; the output end of the third delay line DLY3 is connected with the other input end of the second NAND gate NAND 2; the output end of the second NAND gate NAND2 is connected with the input end of the fourth inverter INV 4; the output end of the fourth inverter INV4 is connected to the gate end of the first NMOS transistor N1; the source end of the first PMOS pipe P1 is connected with a power supply; the source end of the first NMOS transistor N1 is grounded; the drain terminal of the first PMOS tube P1 and the drain terminal of the first NMOS tube N1 are connected together and used as the output end Q of the output drive circuit;
the input end of the second delay line DLY2 is connected with the gate end of the first PMOS tube P1; the output end of the second delay line DLY2 and the output end of the first NAND gate NAND1 are respectively connected with the input end of a second NOR gate NOR2, the output end of the second NOR gate NOR2 is connected with the input end of a third inverter INV3, and the output end of the third inverter INV3 is connected with the gate end of a second PMOS transistor P2;
the input end of the fourth delay line DLY4 is connected with the gate end of the first NMOS transistor N1; the output end of the fourth delay line DLY4 and the output end of the third NOR gate NOR3 are respectively connected with the input end of a third NAND gate NAND3, the output end of the third NAND gate NAND3 is connected with the input end of a fifth inverter INV5, and the output end of the fifth inverter INV5 is connected with the gate end of a second NMOS transistor N2;
the source end of the second PMOS pipe P2 is connected with a power supply; the source end of the second NMOS transistor N2 is grounded; the drain terminal of the second PMOS transistor P2 and the drain terminal of the second NMOS transistor N2 are connected to the output terminal Q of the output driving circuit.
2. The ground bounce noise resistant output driver circuit of claim 1, wherein the delay times of the first delay line DLY1 and the third delay line DLY3 are the same.
3. The ground bounce noise resistant output driver circuit of claim 2, wherein the delay time of the first delay line DLY1 and the third delay line DLY3 does not exceed 1/10 of the duty cycle of the output driver circuit.
4. The ground bounce noise resistant output driver circuit of claim 1, wherein the delay times of the second delay line DLY2 and the fourth delay line DLY4 are the same.
5. The ground bounce noise resistant output driver circuit as claimed in claim 1, wherein the width-to-length ratio of the second PMOS transistor P2 is greater than the width-to-length ratio of the first PMOS transistor P1.
6. The ground bounce noise resistant output driver circuit as claimed in claim 1, wherein the width-to-length ratio of the second NMOS transistor N2 is greater than the width-to-length ratio of the first NMOS transistor N1.
7. The output driving circuit of claim 1, wherein the width-to-length ratios of the first PMOS transistor P1, the first NMOS transistor N1, the second PMOS transistor P2, and the second NMOS transistor N2 satisfy the following condition:
8. the ground bounce noise resistant output driving circuit as claimed in claim 1, wherein the second inverter INV2 has the same structure as the third inverter INV3, and comprises a third PMOS transistor P3, a third NMOS transistor N3 and a fourth NMOS transistor N4;
the source end of the third PMOS pipe P3 is connected with a power supply; the drain terminal of the third PMOS transistor P3 is connected to the drain terminal of the third NMOS transistor N3, the source terminal of the third NMOS transistor N3 is connected to the drain terminal of the fourth NMOS transistor N4, and the source terminal of the fourth NMOS transistor N4 is grounded.
9. The ground bounce noise resistant output driving circuit as claimed in claim 1, wherein the fourth inverter INV4 is the same as the fifth inverter INV5, and comprises a fourth PMOS transistor P4, a fifth PMOS transistor P5 and a fifth NMOS transistor N5;
the source end of the fourth PMOS pipe P4 is connected with a power supply; the drain terminal of the fourth PMOS transistor P4 is connected to the source terminal of the fifth PMOS transistor P5, the drain terminal of the fifth PMOS transistor P5 is connected to the drain terminal of the fifth NMOS transistor N5, and the source terminal of the fifth NMOS transistor N5 is grounded.
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