CN108494394A - The output driving circuit and method of a kind of low noise and anti-high ground bounce noise - Google Patents
The output driving circuit and method of a kind of low noise and anti-high ground bounce noise Download PDFInfo
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- CN108494394A CN108494394A CN201810660099.6A CN201810660099A CN108494394A CN 108494394 A CN108494394 A CN 108494394A CN 201810660099 A CN201810660099 A CN 201810660099A CN 108494394 A CN108494394 A CN 108494394A
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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- H—ELECTRICITY
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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Abstract
The present invention discloses the output driving circuit and method of a kind of low noise and anti-high ground bounce noise, which is divided into predrive module, PMOS drive modules and NMOS drive modules.The PMOS drive modules are connected to the PMOS input nodes with the predrive module, the NMOS drive modules are connected to the NMOS input nodes with the predrive module so that reduce ground bounce noise by the output driving resistance of output driving circuit described in dynamic regulation when the PMOS input nodes or the NMOS input nodes input Dynamic Signal；Enhance anti-highland bullet noise effect by improving output driving resistance when the PMOS input nodes or the NMOS input nodes input stationary singnal.Compared with the existing technology, the present invention reduces ground bounce noise, while by improving output resistance when static drive, improving anti-highland bullet noise effect by dynamically adjusting the output driving resistance of the output driving circuit.
Description
Technical field
The present invention relates to a kind of output driving of semiconductor integrated circuit more particularly to low noise and anti-high ground bounce noise electricity
Road and based on the output driving circuit reduction ground bounce noise method.
Background technology
There are package inductance between power supply on circuit board and encapsulating package power supply, encapsulating package power supply and semiconductor are integrated
There are On chip parasitic inductance between circuit internal electric source, there is encapsulation electricity between the ground wire and encapsulating package ground wire on circuit board
Sense, encapsulating package line there are On chip parasitic inductances between semiconductor integrated circuit internal ground wire.In general package inductance
Much larger than On chip parasitic inductance, there are larger transient current variation, this transient current in the power cord and ground wire of integrated circuit
Larger AC voltage difference fluctuation is generated by package inductance, will cause semiconductor integrated circuit internal electric source, internal ground wire electricity
Pressure is different from power supply, the ground wire voltage on circuit board.This phenomenon is called ground bounce effect, this effect is introduced in power supply with ground wire
Ground bounce noise.
IO driving circuits are widely used as a kind of universal circuit in IC, with the increase of IC functions now, companion
With and what is come is that I/O pin number increases, the number of IO driving circuits also increases as naturally, but due to the pin of entire IC
Limited, corresponding power pins number often can not proportional increase.Due to common multiple IO driving circuits while work
As when will produce apparent ground bounce noise, when this ground bounce noise reach certain numerical value may result in receiving terminal circuit receive
To the signal level of mistake.Wherein ground bounce noise formula is, whereinIt is single IO driving circuits
Caused, L is the parasitic inductance numerical value of IC power pins or ground pin, and N is the number that IO driving circuits work at the same time, in order to
Ensure that IC has multiple functions, the number that IO driving circuits work at the same time also to be difficult to reduce.
Current most of designing techniques are merely focusing on the ground bounce noise for how reducing and being generated when IO drive circuit works, pass
System single IO driving circuits as shown in Figure 1, enabled output end OE for high level in the case of, when the letter of data output end DO
When number being converted to low level for high level, NMOS tube NMO1, NMOS tube NMO2 and NMOS tube NMO3 shutdown, PMOS tube PMO1 is at first
Conducting, after buffer delay, PMOS tube PMO2 and PMOS tube PMO3 are then turned on, due to ground bounce noise and curent change
Rate is directly proportional, and PMOS tube PMO2 and PMOS tube PMO3 successively have electric current to pull up output node VOUT after being then turned on, although electric
Road delay has certain loss, but reduces the change rate of pull-up current；When the signal of data output end DO is electric from low to high
When flat turn is changed, PMOS tube PMO1, PMOS tube PMO2 and PMOS tube PMO3 shutdowns, NMOS tube NMO1 is connected at first, by buffer
After delay, NMOS tube NMO2 and NMOS tube NMO3 are then turned on, also due to ground bounce noise team is directly proportional to current changing rate,
NMOS tube NMO2 first has a low current to pull down output node VOUT after opening, NMOS tube NMO2 unlatchings later have a high current again
Output node VOUT is pulled down, the change rate of pull-down current is greatly reduced.But this circuit still has the shortcomings that bigger:First
It is the IO driving circuits there is PMOS tube PMO1, PMOS tube PMO2 and PMOS tube PMO3 is almost simultaneously turned on or NMOS tube
NMO1, NMOS tube NMO2 and NMOS tube NMO3, which are almost simultaneously turned on, causes larger current in the short time electric to load by PMOS tube
Capacity charge discharges to load capacitance by NMOS tube, so as to cause larger ground bounce noise is generated；Secondly in circuit static
Under working condition, PMOS tube or NMOS tube remain conducting, this will introduce ground bounce noise, will also generate larger static work(
Consumption.
In addition, some occurred in the prior art reduce the IO driving circuit designing techniques of ground bounce noise, such as U.S. intentionally
Patent US4880997 makes afterbody that PMOS tube and NMOS tube be driven slowly to lead by controlling pre-driver driving capabilities
It is logical, it still cannot effectively eliminate since multiple IO driving circuits work at the same time output signal electricity caused by the ground bullet signal of generation
Equal wrong phenomenon.
Invention content
In order to improve the anti-ground bounce noise interference performance of IO output driving circuits itself as far as possible, the present invention proposes a kind of low
Output noise and the IO output driving circuits with highly resistance power ground resilience energy power, its technical solution is as follows：
A kind of output driving circuit of low noise and anti-high ground bounce noise, including with data output end and enabled output end be input
Predrive module, PMOS input nodes, the PMOS common nodes being connected with PMOS input nodes, NMOS input nodes, with
NMOS input nodes connected NMOS common nodes, output node, ground terminal and supply voltage end；The output driving circuit is also
Including PMOS drive modules and NMOS drive modules；
The PMOS drive modules are connected to the PMOS input nodes with the predrive module so that the PMOS inputs section
Ground bounce noise, the PMOS are reduced by the output driving resistance of dynamic regulation PMOS drive modules when point input Dynamic Signal
Enhance anti-highland bullet noise effect by improving output driving resistance when input node inputs stationary singnal；
The NMOS drive modules are connected to the NMOS input nodes with the predrive module so that the NMOS inputs section
Ground bounce noise, the NMOS are reduced by the output driving resistance of dynamic regulation NMOS drive modules when point input Dynamic Signal
Enhance anti-highland bullet noise effect by improving output driving resistance when input node inputs stationary singnal；
Wherein, the PMOS drive modules and the NMOS drive modules are connected to the output node；The Dynamic Signal is
There are the signal of level overturning, the stationary singnal is the signal for not occurring level overturning.
Further, the PMOS drive modules include the failing edge delays time to control submodule of preset quantity and are divided into pre-
If organizing the PMOS tube of number；The grid of first group of PMOS tube is all connected to the PMOS inputs with the output end of first phase inverter
Node, and remaining each group PMOS tube is all correspondingly connected with the output end of a failing edge delays time to control submodule by its grid, in advance
If the input terminal of the failing edge delays time to control submodule of quantity is all connected to the PMOS common nodes so that in PMOS public affairs
When conode inputs Dynamic Signal, the failing edge delays time to control submodule is adjusted by controlling the turn-on time of each group PMOS tube
The output driving resistance of PMOS drive modules is saved to reduce the change rate of electric current, to reduce ground bounce noise；In PMOS public affairs
When conode inputs stationary singnal, the failing edge delays time to control submodule is driven by turning off each group PMOS tube to increase PMOS
The output driving resistance of module is to enhance the effect of anti-high ground bounce noise；
The NMOS drive modules include the rising edge delays time to control submodule of preset quantity and the NMOS for being divided into preset group number
Pipe；The grid of first group of NMOS tube is all connected to the NMOS input nodes with the output end of second phase inverter, and remaining
Each group NMOS tube is all correspondingly connected with the output end of a rising edge delays time to control submodule, the rising of preset quantity by its grid
It is all connected to the NMOS common nodes along the input terminal of delays time to control submodule so that dynamic in NMOS common nodes input
When state signal, the failing edge delays time to control submodule drives mould by controlling the turn-on time of each group NMOS tube to adjust NMOS
The output driving resistance of block reduces the change rate of electric current, to reduce ground bounce noise；It is inputted in the NMOS common nodes
When stationary singnal, the failing edge delays time to control submodule increases the output of NMOS drive modules by turning off each group NMOS tube
Drive resistance to enhance the effect of anti-high ground bounce noise；
Wherein, the preset quantity subtracts one equal to the preset group number；Each group of PMOS tube in remaining described each group PMOS tube
A corresponding failing edge delays time to control submodule；Each group of NMOS tube corresponds to described in one in remaining described each group NMOS tube
Rising edge delays time to control submodule.
Further, the PMOS drive modules include being divided into the PMOS tube of preset group number, the number of first group of PMOS tube
Mesh is smaller than the number of remaining group PMOS tube so that the data output end, which is the ground bounce noise in high level stage, to be reduced；
The number of first group of NMOS tube is smaller than the number of remaining group NMOS tube so that the data output end is low level rank
The ground bounce noise of section reduces.
Further, the source electrode for the PMOS tube for being divided into preset group number described in the PMOS drive modules is all connected to described
Supply voltage end, drain electrode are all connected to the output node；
The drain electrode for the NMOS tube for being divided into preset group number described in the NMOS drive modules is all connected to the output node, source
Pole is all connected to the ground terminal.
Further, the numerical value of the preset group number is set as 3 or more than 3.
Further, the failing edge delays time to control submodule include the first input logic unit, low level time delay elements,
4th phase inverter and second or door, wherein the input terminal of the first input logic unit connects the PMOS input nodes, and first is defeated
Enter the input terminal of the output end connection low level time delay elements of logic unit, the output end connection the 4th of low level time delay elements is anti-
The input terminal of phase device, the common node that the output end of the first input logic unit is connected with the input terminal of low level time delay elements
Be connected to two input terminals of second or door with the output end of the 4th phase inverter, second or the output end connection of door described remaining is each
The grid of corresponding one group of PMOS tube in group PMOS tube；
Wherein, the first input logic unit is buffer or time delay elements, and the low level time delay elements determine the low electricity of output
Pulse-width.
Further, the rising edge delays time to control submodule include the second input logic unit, high level time delay elements,
5th phase inverter and second and door, wherein the input terminal of the second input logic unit connects the NMOS input nodes, and second is defeated
Enter the input terminal of the output end connection high level time delay elements of logic unit, the output end connection the 5th of high level time delay elements is anti-
The input terminal of phase device, the common node that the output end of the second input logic unit is connected with the input terminal of high level time delay elements
It is connected to two input terminals of second and door with the output end of the 5th phase inverter, second connect that described remaining is each with the output end of door
The grid of corresponding one group of NMOS tube in group NMOS tube；
Wherein, the second input logic unit is buffer or time delay elements, and the high level time delay elements determine the height electricity of output
Pulse-width.
Further, the turn-on time length of failing edge delays time to control submodule control remaining each group PMOS tube
With the initial time of conducting；The turn-on time length of rising edge delays time to control submodule control remaining each group NMOS tube
With the initial time of conducting.
A method of the reduction ground bounce noise based on the output driving circuit, this method include：
When rising edge signal is inputted the predrive module by the data output end DO, the PMOS input nodes receive
Failing edge signal is connected first group of PMOS tube in the PMOS drive modules, and triggers the failing edge delays time to control submodule
Low level pulse signal is exported, remaining is connected and organizes corresponding PMOS tube, to which the turn-on time for controlling remaining each group PMOS tube is long
The initial time of degree and conducting, ground bounce noise is reduced by the output driving resistance of dynamic regulation PMOS drive modules；
When the data output end DO keeps high level state, the PMOS input nodes keep low level signal, described
First group of PMOS tube continues to be connected in PMOS drive modules, and the failing edge delays time to control submodule exports high level, shutdown
Remaining group PMOS tube so that the output driving resistance of the output driving circuit increases, to enhance anti-highland bullet noise effect；
When failing edge signal is inputted the predrive module by the data output end DO, the NMOS input nodes receive
Rising edge signal is connected first group of NMOS tube in the NMOS drive modules, and triggers the rising edge delays time to control submodule
High level pulse signal is exported, remaining is connected and organizes corresponding NMOS tube, to which the turn-on time for controlling remaining each group NMOS tube is long
The initial time of degree and conducting, ground bounce noise is reduced by the output driving resistance of dynamic regulation NMOS drive modules；
When the data output end DO keeps low level state, the PMOS input nodes keep high level signal, described
First group of NMOS tube continues to be connected in NMOS drive modules, and the rising edge delays time to control submodule exports low level, shutdown
Remaining group NMOS tube so that the output driving resistance of the output driving circuit increases, to enhance anti-highland bullet noise effect.
Compared with the existing technology, the present invention implements, in order to reduce the ground bounce noise of generation as far as possible, to drive by dynamic adjustment
Dynamic PMOS tube changes output driving ability with the turn-on time of NMOS tube is driven, and reduces current changing rate, defeated to reduce IO
Go out ground bounce noise caused by driving circuit, while increasing output driving resistance when inputting stationary singnal, improves the output
The ability for driving the anti-high ground bounce noise of resistance, to ensure output driving circuit output signal under various application conditions
Accuracy rate.
Description of the drawings
Fig. 1 is traditional single IO drive circuit schematic diagrams；
Fig. 2 is the output driving circuit schematic diagram of a kind of low noise and anti-high ground bounce noise that present invention implementation provides；
Fig. 3 is the circuit diagram for the failing edge delays time to control submodule that present invention implementation provides；
Fig. 4 is the circuit diagram for the rising edge delays time to control submodule that present invention implementation provides；
Fig. 5 is the signal timing diagram for the output driving circuit node that present invention implementation provides；
Fig. 6 is the schematic diagram that output driving circuit in the prior art generates ground bounce noise；
Fig. 7 is the schematic diagram for the anti-ground bounce noise of output driving circuit that present invention implementation provides.
Specific implementation mode
The specific implementation mode of the present invention is described further below in conjunction with the accompanying drawings：
In order to reduce the ground bounce noise of IO output driving circuits generation as far as possible, most viable mode is exactly to reduce as far as possible individually
Current changing rate caused by the work of IO output driving circuits, and reduce the number of power pins or the parasitic inductance of ground pin
Mesh, but power pins or ground pin are often limited by product packing forms and can not reduce, while in order to ensure that IC has multiple work(
Can, IO output driving circuit concurrent working numbers are also difficult to reduce.In view of the above-mentioned problems, set forth herein a kind of novel low noises
And the output driving circuit of ground bounce effect resisting, present inventive concept are mainly that dynamic adjustment drives PMOS tube and drives leading for NMOS tube
Logical resistance mode reduces ground bounce noise caused by output driving circuit to realize, and realizes anti-high ground bounce noise under stationary singnal
Effect.
Fig. 1 is the output driving circuit of a kind of low noise and anti-high ground bounce noise that present invention implementation provides, the output
Driving circuit further includes PMOS drive modules and NMOS drive modules；PMOS drive modules are connected to institute with the predrive module
State PMOS input nodes A so that pass through dynamic regulation PMOS drive modules when the PMOS input nodes A inputs Dynamic Signal
Output driving resistance reduces ground bounce noise, and when PMOS input nodes A inputs stationary singnal, which passes through, improves output driving electricity
Resistance enhances anti-highland bullet noise effect；
NMOS drive modules are connected to the NMOS input nodes B with the predrive module so that the NMOS input nodes B
Ground bounce noise is reduced by the output driving resistance of dynamic regulation NMOS drive modules when inputting Dynamic Signal, the NMOS is defeated
Enhance anti-highland bullet noise effect by improving output driving resistance when ingress B input stationary singnals.
Specifically, the PMOS drive modules and the NMOS drive modules are connected to the output node OUT.It is described dynamic
State signal is that there are the signals that low and high level is overturn, including rising edge signal and failing edge signal；The stationary singnal can not be
The signal of existing level overturning, including high level signal and low level signal.
As one embodiment of the present invention, as shown in Figure 1, the output driving circuit includes with data output end DO
With the predrive module that enabled output end OE is input, PMOS input nodes A, the PMOS being connected with PMOS input nodes A are public
Node A1, NMOS input node B, NMOS common nodes B1, output node VOUT, the ground terminal being connected with NMOS input nodes B
VSS and supply voltage end VCC；The predrive module includes the first phase inverter that output end is connected with PMOS input nodes A
The second phase inverter INV2 that INV1 and output end are connected with NMOS input nodes B.As shown in Figure 1, making to predrive module
Further instruction, data output end DO and enabled output end OE are connected to first and door AND1, and first with door AND1's
Output end connects the input terminal of the first phase inverter INV1, and the output end of the first phase inverter INV1 is connected to PMOS input nodes A；Make
Energy output end OE is connected to the input terminal of first or door OR1 by third phase inverter INV3, and data output end DO is connected to first
Or another input terminal of door OR1, the output end of first or door OR1 are connected to the input terminal of the second phase inverter INV2, second is anti-
The output end of phase device INV2 is connected to NMOS input nodes B.Under the premise of enabled output end OE sets height, as shown in figure 4, when number
When exporting rising edge signal according to output end DO, the signal PU1 at PMOS input nodes A is failing edge signal, NMOS input nodes B
The signal PD1 at place is also failing edge signal, but signal PD1 is postponed relative to signal PU1.As shown in Fig. 2, the output is driven
Dynamic circuit further includes the PMOS drive modules being connect with the predrive module by the PMOS input nodes A, and passes through institute
State the NMOS drive modules that NMOS input nodes B is connect with the predrive module.
As one embodiment of the present invention, the PMOS drive modules include the failing edge delays time to control of preset quantity
Submodule and the PMOS tube for being divided into preset group number, the setting of the PMOS tube number in the setting and each group of the preset group number is all
Meet the practical driving capability of chip I/O, wherein the preset quantity subtracts one equal to the preset group number；In addition to first group
Each group of PMOS tube corresponds to a failing edge delays time to control submodule in remaining each group PMOS tube outside PMOS tube；Of the invention real
It applies in example, to simplify the explanation, preset group number is set as 3, and preset quantity is set as 2, and all PMOS tube in each group are all simultaneously
Connection connection, can be reduced to an equivalent PMOS tube, as shown in Fig. 2, first group of PMOS tube is reduced to the first PMOS tube PM1, the
Two groups of PMOS tube are reduced to the second PMOS tube PM2, and third group PMOS tube is reduced to third PMOS tube PM3.First PMOS tube PM1's
The output end of grid and the first phase inverter INV1 is connected to the PMOS input nodes A.And it is every in remaining group PMOS tube
One PMOS tube all connects the output end of a failing edge delays time to control submodule by its grid, i.e. the second PMOS tube PM2's
The grid that grid connects the first failing edge delays time to control submodule OSL1, third PMOS tube PM3 connects the delay control of the second failing edge
The input of system module OSL2, the first failing edge delays time to control submodule OSL1 and the second failing edge delays time to control submodule OSL2
End is all connected to the PMOS common nodes A1.After the first PMOS tube PM1 is connected in the signal PU1 of the PMOS input nodes A, letter
Number PU1 drives the second PMOS tube PM2, signal PU1 to decline by second after the first failing edge delays time to control submodule OSL1
Third PMOS tube PM3 is driven after delays time to control submodule OSL2, after the PMOS input nodes A inputs failing edge signal,
The controlled system conducting of each group PMOS tube, wherein the turn-on time width of the second PMOS tube PM2 is by the first failing edge delays time to control submodule
Block OSL1 is limited, and the turn-on time width of third PMOS tube PM3 is limited by the second failing edge delays time to control submodule OSL2.
Specifically, the number of the driving PMOS tube in first group of PMOS tube is set as minimum, because this group of PMOS tube is in number
According between output end DO output high periods, i.e., the described PMOS input nodes A is always conducting between low period, and described
PMOS input nodes A is connected at first when being failing edge signal, base area bullet expressions of noise, due toNumerical value maximum value is directly proportional to the PMOS tube number be connected at first, so the number by reducing by first group of PMOS tube
The current changing rate during level conversion at the PMOS input nodes A can be reduced, and then reduce the output driving electricity
Road exports the ground bounce noise in high level stage in data output end DO.When the PMOS common nodes A1 inputs Dynamic Signal,
The first failing edge delays time to control submodule OSL1 controls the turn-on time width of the second PMOS tube PM2, and described second declines
Along the turn-on time width of delays time to control submodule OSL2 control third PMOS tube PM3, and then control the defeated of PMOS drive modules
Go out to drive resistance to reduce the change rate of electric current, to reduce ground bounce noise；When the PMOS common nodes A1 inputs static letter
Number when, the first failing edge delays time to control submodule OSL1 turns off the second PMOS tube PM2, the second failing edge delays time to control
Submodule OSL2 turns off third PMOS tube PM3, to increase the output driving resistance of PMOS drive modules to enhance anti-highland bullet
The effect of noise so that under the conditions of quiescent operation the equivalent output driving resistance of PMOS drive modules compared with the prior art in it is defeated
The resistance value gone out when driving circuit each group PMOS tube simultaneously turns on is big, weakens ground bounce noise and believes the output of the output driving circuit
Number influence, enhance the ground bounce effect resisting of the output driving circuit.
As one embodiment of the present invention, the NMOS drive modules include the rising edge delays time to control of preset quantity
Submodule and the NMOS tube for being divided into preset group number, the setting of the NMOS tube number in the setting and each group of the preset group number is all
Meet the practical driving capability of chip I/O, wherein the preset quantity subtracts one equal to the preset group number；In addition to first group
Each group of NMOS tube corresponds to a rising edge delays time to control submodule in remaining each group NMOS tube outside NMOS tube；Of the invention real
It applies in example, to simplify the explanation, preset group number is set as 3, and preset quantity is set as 2, and all NMOS tubes in each group are all simultaneously
Connection connection, can be reduced to an equivalent NMOS tube, as shown in Fig. 2, first group of NMOS tube is reduced to the first NMOS tube NM1, the
Two groups of NMOS tubes are reduced to the second NMOS tube NM2, and third group NMOS tube is reduced to third NMOS tube NM3.First NMOS tube NM1's
The output end of grid and the second phase inverter INV2 is connected to the NMOS input nodes B.And it is every in remaining group NMOS tube
One NMOS tube all connects the output end of a rising edge delays time to control submodule by its grid, i.e. the second NMOS tube NM2's
The grid that grid connects the first rising edge delays time to control submodule OSH1, third NMOS tube NM3 connects the delay control of the second rising edge
The input of system module OSH2, the first rising edge delays time to control submodule OSH1 and the second rising edge delays time to control submodule OSH2
End is all connected to the NMOS common nodes B1.After the first NMOS tube NM1 is connected in the signal PD1 of the NMOS input nodes B, letter
Number PD1 drives the second NMOS tube NM2, signal PD1 to rise by second after the first rising edge delays time to control submodule OSH1
Third NMOS tube NM3 is driven after delays time to control submodule OSH2, after the NMOS input nodes B inputs rising edge signal,
The controlled system conducting of each group NMOS tube, wherein the turn-on time width of the second NMOS tube NM2 is by the first rising edge delays time to control submodule
Block OSH1 is limited, and the turn-on time width of third PMOS tube PM3 is limited by the second rising edge delays time to control submodule OSH2.
Specifically, the number of the driving NMOS tube in first group of NMOS tube is set as minimum, because this group of NMOS tube is in number
According between output end DO output high periods, i.e., the described NMOS input nodes B is always conducting between high period, and described
NMOS input nodes B is connected at first when being rising edge signal, base area bullet expressions of noise, due toNumerical value maximum value is directly proportional to the NMOS tube number be connected at first, so the number by reducing by first group of NMOS tube
The current changing rate during level conversion at the NMOS input nodes B can be reduced, and then reduce the output driving electricity
Road exports the ground bounce noise in low level stage in data output end DO.When the NMOS common nodes B1 inputs Dynamic Signal,
The first rising edge delays time to control submodule OSH1 controls the turn-on time width of the second NMOS tube NM2, and described second rises
Along the turn-on time width of delays time to control submodule OSH2 control third NMOS tubes NM3, and then control the defeated of NMOS drive modules
Go out to drive resistance to reduce the change rate of electric current, to reduce ground bounce noise；When the NMOS common nodes B1 inputs static letter
Number when, the first rising edge delays time to control submodule OSH1 turns off the second NMOS tube NM2, the second rising edge delays time to control
Submodule OSH2 turns off third NMOS tube NM3, to increase the output driving resistance of NMOS drive modules to enhance anti-highland bullet
The effect of noise so that under the conditions of quiescent operation the equivalent output driving resistance of NMOS drive modules compared with the prior art in it is defeated
The resistance value gone out when driving circuit each group NMOS tube simultaneously turns on is big, weakens ground bounce noise and believes the output of the output driving circuit
Number influence, enhance the anti-highland bullet noise effect of the output driving circuit.
The source electrode for the PMOS tube for being divided into preset group number described in the PMOS drive modules is all connected to supply voltage end
VCC, drain electrode are all connected to output node OUT；It is divided into the leakage of the NMOS tube of preset group number described in the NMOS drive modules
Pole is all connected to output node OUT, and source electrode is all connected to ground terminal VSS；Every group of PMOS tube connects with corresponding one group of NMOS tube
It connects to form recommending output mode structure to enhance IO output driving abilities, and the numerical value of the preset group number is set as 3 or more than 3.
As shown in figure 3, the failing edge delays time to control submodule includes the first input logic unit s1, low level time delay list
First d1, the 4th phase inverter INV4 and second or door OR2, the submodule are by the failing edge signal of the PMOS input nodes A
Trigger work.The logical construction of the failing edge delays time to control submodule includes：The input terminal of first input logic unit s1
Connect the PMOS input nodes A1, the input of the output end connection low level time delay elements d1 of the first input logic unit s1
End, the output end of low level time delay elements d1 connect the input terminal of the 4th phase inverter INV4, and the first input logic unit s1's is defeated
The output end of common node and the 4th phase inverter INV4 that outlet is connected with the input terminal of low level time delay elements d1 is connected to
Two input terminals of second or door OR2.Specifically, as shown in Fig. 2, under the failing edge delays time to control submodule is used as first
When drop is along delays time to control submodule OSL1, the output end of second or door OR2 connects the grid of the second PMOS tube PM2；Work as institute
When stating failing edge delays time to control submodule as the second failing edge delays time to control submodule OSL2, the output end of second or door OR2
Connect the grid of the third PMOS tube PM3.Wherein, the first input logic unit s1 is buffer or time delay elements；Low level
Time delay elements d1 directly determines low level pulse width caused by the failing edge delays time to control submodule, to described
The turn-on time of second PMOS tube PM2 and the third PMOS tube PM3 have an impact, and turn-on time length can be arranged identical
It can also be different, this is determined jointly by the load capacitance and circuit work frequency of the output driving circuit.
As shown in figure 4, the rising edge delays time to control submodule includes the second input logic unit s2, high level time delay list
First d2, the 5th phase inverter INV5 and second and door AND2, which touched by the rising edge signal of the NMOS input nodes B
Send out work.The logical construction of the rising edge delays time to control submodule includes：The output end of second input logic unit s2 connects
The input terminal of high level time delay elements d2 is connect, the output end of high level time delay elements d2 connects the input of the 5th phase inverter INV5
End, the common node and the 5th that the output end of the second input logic unit s2 is connected with the input terminal of high level time delay elements d2
The output end of phase inverter INV5 is connected to two input terminals of second and door AND2；Specifically, as shown in Fig. 2, working as the rising
When being used as the first rising edge delays time to control submodule OSH1 along delays time to control submodule, second connect institute with the output end of door AND2
State the grid of the second NMOS tube NM2；When the rising edge delays time to control submodule is used as the second rising edge delays time to control submodule
When OSH2, second connect the grid of the third NMOS tube NM3 with the output end of door AND2；Wherein, the second input logic unit
S2 is buffer or time delay elements；High level time delay elements d2 is directly determined produced by the rising edge delays time to control submodule
High-level pulse width, to generate shadow to the turn-on time of the second NMOS tube NM2 and the third NMOS tube NM3
Ring, turn-on time length can be arranged it is identical can also be different, this be according to the load capacitance of the output driving circuit and
Circuit work frequency is determined jointly.
Occur in Fig. 6 single IO driving circuits traditional in the prior art output node OUT and receiving terminal recevie it
Between contain the output circuit schematic diagram of package inductance, for traditional single IO driving circuits, the R_mos in Fig. 6 is output
Equivalent output driving resistance under node OUT outputs static low level or high level state, L_ground drive for the IO
Package inductance on the ground wire of circuit, L_pkg are the package inductance on the power cord of the IO driving circuits, and C_load drives for the IO
The load capacitance of dynamic circuit, p_out is load output signal.The IO driving circuits generate ground bounce noise be
When IO driving circuit number Ns increase, i.e., the semiconductor circuit where IO driving circuits has N number of output while height occurs
Level is overturn, and the electric current of the package inductance L_ground on the ground wire of the IO driving circuits will become N times at this time, will production on ground wire
Larger voltage fluctuation is given birth to, similarly the package inductance L_pkg on the power cord of the IO driving circuits also generates larger voltage wave
It is dynamic.From the point of view of Fig. 6, if being static low level on output node OUT, then load output signal p_out should be low level, but
Be due to the ground wire of this IO driving circuit be largely generated with other overturning waveform IO driving circuits be connected so that
The ground nodes VSS of this IO driving circuit just will appear ground bounce noise signal, this ground bounce noise signal passes through under NMOS tube
Draw conducting that can transfer out, amplitude is suitable with ground bounce noise signal original on ground nodes VSS, believes when the load exports
When number p_out is sent to receiving terminal recevie, receiving terminal recevie is allowed to receive a high level pulse signal v_err, to
It causes to receive mistake, causes the erroneous judgement of other devices, generate logic error.
As one embodiment of the present invention, occur in Fig. 7 the output node OUT of the output driving circuit with it is described
The output circuit signal of package inductance is contained between the receiving terminal recevie of integrated circuit external where output driving circuit
Figure, difference lies in the equivalent output driving resistance under quiescent operation state in Fig. 7 with the single IO driving circuits united in Fig. 6 for this
Resistance value increasing considerably relative to Fig. 6.R_big in Fig. 7 is that the output driving circuit is quiet in output node OUT outputs
Equivalent output driving resistance under state signal condition, L_ground are the package inductance on the ground wire of the output driving circuit,
L_pkg is the package inductance on the power cord of the output driving circuit, and C_load is the load capacitance of the IO driving circuits, p_
Out is load output signal.
When being static low level signal on the output node OUT of the output driving circuit, the output driving circuit
Ground wire be largely to generate ground wires of IO output driving circuits of overturning waveform with other in same chip to be connected so that
There is ground bounce noise signal in the ground nodes VSS of the output driving circuit, this ground bounce noise signal drives by the NMOS
Dynamic model block transfers out.Due to the corresponding voltage peak Vp of load output signal p_out and the equivalent driving output resistance R_
The relationship of big is as follows：
,
So when the resistance value of the equivalent output driving resistance R_big of the output driving circuit is more than substantially that common IO drives
The equivalent output driving resistance of circuit, also above the equivalent output driving of most of driving circuit using Low-noise Design Technology
When resistance, the corresponding voltage fluctuation amplitudes of load output signal p_out are weakened, and ensure receiving terminal recevie in output node
Reception signal when OUT is static low level signal is low level signal v_no_err, avoids generating logic error.The output
Driving circuit changes the output driving resistance by the turn-on time that dynamic adjusts driving PMOS tube and drives NMOS tube, especially
It only has first group of PMOS tube or first group of NMOS tube conducting under quiescent operation status condition, and remaining organizes MOS
Pipe is turned off because of the control of the rising edge delays time to control submodule or the failing edge delays time to control submodule so that described
Equivalent output driving resistance increases, and to reduce the crest voltage fluctuation amplitude on load output signal p_out, realizes anti-highland
Play the effect of noise.
The embodiment of the present invention provides above-mentioned output driving circuit working signal sequence diagram, as shown in figure 5, t0 moment, institute
It states data output end DO and rising edge signal is sent into the predrive module, the signal PU1 at the PMOS input nodes A is
Failing edge signal, the first PMOS tube PM1 conductings, the signal PD1 at the NMOS input nodes B are also that failing edge is believed
Number, the first NMOS tube NM1 shutdowns.
As shown in figure 5, the t1 moment, the data output end DO keeps high level state, the grid of the second PMOS tube PM2
Signal PU2 at pole is one that signal PU1 is obtained by the logical action of the first failing edge delays time to control submodule OSL1
A failing edge signal, the second PMOS tube PM2 are pulled up conducting, and the signal PD2 at the grid of the second NMOS tube NM2
It is described for the low level signal that signal PD1 is obtained by the logical action of the first rising edge delays time to control submodule OSH1
Second NMOS tube NM2 shutdowns；The signal PU1 at t1 moment keeps low level so that the first PMOS tube PM1 is held on；t1
The signal PD1 at moment keeps low level so that the first NMOS tube NM1 is held off.
As shown in figure 5, the t2 moment, the data output end DO keeps high level state, the grid of the third PMOS tube PM3
Signal PU3 at pole is one that signal PU1 is obtained by the logical action of the second failing edge delays time to control submodule OSL2
A failing edge signal, the third PMOS tube PM3 are pulled up conducting, and the signal PD3 at the grid of the third NMOS tube NM3
It is described for the low level signal that signal PD1 is obtained by the logical action of the second rising edge delays time to control submodule OSH2
The NM3 shutdowns of third NMOS tube；The third PMOS tube PM3 pulling drive output node OUT are gradually become by low level signal at this time
Turn to high level signal.The signal PU1 at t2 moment keeps low level so that the first PMOS tube PM1 is held on；The t2 moment
Signal PU2 saltus steps later are high level so that the second PMOS tube PM2 shutdowns；The signal PD1 at t2 moment keeps low electricity
It is flat so that the first NMOS tube NM1 is held off；The signal PD2 at t2 moment keeps low level so that second NMOS tube
NM2 is held off.
Above-mentioned t0 is to t2 time sections, according to the variation of the data output end DO output signals, the PMOS drivings
The output driving resistance of module changes with the turn-on and turn-off of each group PMOS tube, wherein first group of PMOS tube is led always
Logical but this group of PMOS tube number is minimum, and for PMOS drive modules described in auxiliary adjustment whether the conducting of remaining group PMOS tube
Output driving resistance reduces the change rate of electric current, to realize reduction ground bounce noise.
As shown in figure 5, the t3 moment, failing edge signal is sent into the predrive module by the data output end DO, in institute
It is rising edge signal to state the signal PU1 at PMOS input nodes A, and the first PMOS tube PM1 shutdowns are inputted in the NMOS and saved
Signal PD1 at point B is also rising edge signal, the first NMOS tube NM1 conductings.
As shown in figure 5, the t4 moment, the data output end DO keeps low level state, the grid of the second PMOS tube PM2
Signal PU2 at pole is the height that signal PU1 is obtained by the logical action of the first failing edge delays time to control submodule OSL1
Level signal, the second PMOS tube PM2 shutdowns, and the signal PD2 at the grid of the second NMOS tube NM2 is signal PD1
By the rising edge signal that the logical action of the first rising edge delays time to control submodule OSH1 obtains, second NMOS tube
NM2 is pulled down conducting；The signal PU1 at t4 moment keeps high level so that the first PMOS tube PM1 is held off；The t4 moment
Signal PD1 keep high level so that the first NMOS tube NM1 is held on.
As shown in figure 5, the t5 moment, the data output end DO keeps low level state, the grid of the third PMOS tube PM3
Signal PU3 at pole is the height that signal PU1 is obtained by the logical action of the second failing edge delays time to control submodule OSL2
Level signal, the third PMOS tube PM3 shutdowns, and the signal PD3 at the grid of the third NMOS tube NM3 is signal PD1
By the rising edge signal that the logical action of the second rising edge delays time to control submodule OSH2 obtains, the third NMOS tube
NM3 is pulled down conducting；The third PMOS tube PM3 pulling drive output nodes OUT is gradually varied to by high level signal at this time
Low level signal.The signal PU1 at T5 moment keeps high level so that the first PMOS tube PM1 is held off；The letter at t5 moment
Number PU2 is high level signal so that the second PMOS tube PM2 shutdowns；The signal PD1 at t5 moment keeps high level so that institute
The first NMOS tube NM1 is stated to be held on；Signal PD2 saltus steps after the t5 moment are low level so that the second NMOS tube NM2
Shutdown.
Above-mentioned t3 is to t5 time sections, according to the signal intensity that the data output end DO is exported, the NMOS drivings
The output driving resistance of module changes with the turn-on and turn-off of each group NMOS tube, wherein first group of NMOS tube is led always
Logical but this group of NMOS tube number is minimum, and for NMOS drive modules described in auxiliary adjustment whether the conducting of remaining group NMOS tube
Output driving resistance reduces current changing rate, to realize reduction ground bounce noise.
Specifically, only when the PMOS common nodes A1 input signals are a failing edge signals, under described first
Drop all generates an effective low electricity along delays time to control submodule OSL1 and the second failing edge delays time to control submodule OSL2
Flat pulse, when inputting other signals at the PMOS common nodes A1, the first failing edge delays time to control submodule OSL1
All it is to maintain high level output with the second failing edge delays time to control submodule OSL2, therefore meaning that driving the third
The turn-on time of PMOS tube PM3 and the second PMOS tube PM2 are limited, and the third PMOS tube PM3 and described
The conducting start time of two PMOS tube PM2 will be later than the first PMOS tube PM1.The wherein described third PMOS tube PM3 and institute
Stating the second PMOS tube PM2 can simultaneously turn on, it is possibility to have the turn-on time of a fixed response time and the second PMOS tube PM2 are long
Degree is controlled by the first failing edge delays time to control submodule OSL1, the turn-on time length of the third PMOS tube PM3 by
What the second failing edge delays time to control submodule OSL2 was controlled；Their turn-on time length can be identical, can not also
Together, this is codetermined in the condition of actually driving output by the load capacitance and working frequency of the output driving circuit.
In order to reduce ground bounce noise, the first failing edge delays time to control submodule OSL1 and described second can be passed through
The OSL2 controls of failing edge delays time to control submodule reduce leading jointly for the second PMOS tube PM2 and third PMOS tube PM3
The logical time, or pass through the first rising edge delays time to control submodule OSH1 and the second rising edge delays time to control submodule
OSH2 controls reduce the common turn-on time of the second NMOS tube NM2 and the third NMOS tube NM3, especially quiet in input
The second PMOS tube PM2, the third PMOS tube PM3, the second NMOS tube NM2 and the 3rd NMOS in the case of state signal
Pipe NM3 is not turned on substantially, to increase the equivalent driving output resistance of the output driving circuit, avoids the output driving electricity
The preset group number PMOS tube or NMOS tube almost simultaneously turn on and larger current are allowed to pass through PMOS tube when the afterbody driving on road
It charges to load capacitance or is discharged load capacitance by NMOS tube and increase ground bounce noise.
Device embodiments described above are only schematical, and those of ordinary skill in the art are not paying creation
Property labour in the case of, you can to understand and implement.
Claims (9)
1. the output driving circuit of a kind of low noise and anti-high ground bounce noise, including with data output end and enabled output end it is defeated
The predrive module that enters, PMOS input nodes, the PMOS common nodes being connected with PMOS input nodes, NMOS input nodes, with
NMOS input nodes connected NMOS common nodes, output node, ground terminal and supply voltage end；It is characterized in that, described defeated
It further includes PMOS drive modules and NMOS drive modules to go out driving circuit；
The PMOS drive modules are connected to the PMOS input nodes with the predrive module so that the PMOS inputs section
Ground bounce noise, the PMOS are reduced by the output driving resistance of dynamic regulation PMOS drive modules when point input Dynamic Signal
Enhance anti-highland bullet noise effect by improving output driving resistance when input node inputs stationary singnal；
The NMOS drive modules are connected to the NMOS input nodes with the predrive module so that the NMOS inputs section
Ground bounce noise, the NMOS are reduced by the output driving resistance of dynamic regulation NMOS drive modules when point input Dynamic Signal
Enhance anti-highland bullet noise effect by improving output driving resistance when input node inputs stationary singnal；
Wherein, the PMOS drive modules and the NMOS drive modules are connected to the output node；The Dynamic Signal is
There are the signal of level overturning, the stationary singnal is the signal for not occurring level overturning.
2. output driving circuit according to claim 1, which is characterized in that the PMOS drive modules include preset quantity
Failing edge delays time to control submodule and be divided into the PMOS tube of preset group number；The grid of first group of PMOS tube is all anti-with described first
The output end of phase device is connected to the PMOS input nodes, and remaining each group PMOS tube is all correspondingly connected with by its grid under one
Output end along delays time to control submodule drops, and the input terminal of the failing edge delays time to control submodule of preset quantity is all connected to described
PMOS common nodes so that when the PMOS common nodes input Dynamic Signal, the failing edge delays time to control submodule is logical
The turn-on time for crossing control each group PMOS tube reduces the change rate of electric current to adjust the output driving resistance of PMOS drive modules,
To reduce ground bounce noise；When the PMOS common nodes input stationary singnal, the failing edge delays time to control submodule is logical
Shutdown each group PMOS tube is crossed to increase the output driving resistance of PMOS drive modules to enhance the effect of anti-high ground bounce noise；
The NMOS drive modules include the rising edge delays time to control submodule of preset quantity and the NMOS for being divided into preset group number
Pipe；The grid of first group of NMOS tube is all connected to the NMOS input nodes with the output end of second phase inverter, and remaining
Each group NMOS tube is all correspondingly connected with the output end of a rising edge delays time to control submodule, the rising of preset quantity by its grid
It is all connected to the NMOS common nodes along the input terminal of delays time to control submodule so that dynamic in NMOS common nodes input
When state signal, the failing edge delays time to control submodule drives mould by controlling the turn-on time of each group NMOS tube to adjust NMOS
The output driving resistance of block reduces the change rate of electric current, to reduce ground bounce noise；It is inputted in the NMOS common nodes
When stationary singnal, the failing edge delays time to control submodule increases the output of NMOS drive modules by turning off each group NMOS tube
Drive resistance to enhance the effect of anti-high ground bounce noise；
Wherein, the preset quantity subtracts one equal to the preset group number；Each group of PMOS tube in remaining described each group PMOS tube
A corresponding failing edge delays time to control submodule；Each group of NMOS tube corresponds to described in one in remaining described each group NMOS tube
Rising edge delays time to control submodule.
3. output driving circuit according to claim 2, which is characterized in that the PMOS drive modules include be divided into it is default
The number of the PMOS tube of group number, first group of PMOS tube is smaller than the number of remaining group PMOS tube so that the data output end is height
The ground bounce noise in level stage reduces；
The number of first group of NMOS tube is smaller than the number of remaining group NMOS tube so that the data output end is low level rank
The ground bounce noise of section reduces.
4. output driving circuit according to claim 3, which is characterized in that be divided into described in the PMOS drive modules default
The source electrode of the PMOS tube of group number is all connected to the supply voltage end, and drain electrode is all connected to the output node；
The drain electrode for the NMOS tube for being divided into preset group number described in the NMOS drive modules is all connected to the output node, source
Pole is all connected to the ground terminal.
5. according to any one of claim 2 to claim 4 output driving circuit, which is characterized in that the preset group number
Numerical value be set as 3 or be more than 3.
6. output driving circuit according to claim 1, which is characterized in that the failing edge delays time to control submodule includes the
One input logic unit, low level time delay elements, the 4th phase inverter and second or door, wherein the first input logic unit it is defeated
Entering end and connects the PMOS input nodes, the output end of the first input logic unit connects the input terminal of low level time delay elements,
The output end of low level time delay elements connects the input terminal of the 4th phase inverter, the output end and low level of the first input logic unit
The output end of common node and the 4th phase inverter that the input terminal of time delay elements is connected is connected to two inputs of second or door
End, second or door remaining described each group PMOS tube of output end connection in corresponding one group of PMOS tube grid；
Wherein, the first input logic unit is buffer or time delay elements, and the low level time delay elements determine the low electricity of output
Pulse-width.
7. output driving circuit according to claim 1, which is characterized in that the rising edge delays time to control submodule includes the
Two input logic units, high level time delay elements, the 5th phase inverter and second and door, wherein the second input logic unit it is defeated
Entering end and connects the NMOS input nodes, the output end of the second input logic unit connects the input terminal of high level time delay elements,
The output end of high level time delay elements connects the input terminal of the 5th phase inverter, the output end and high level of the second input logic unit
The output end of common node and the 5th phase inverter that the input terminal of time delay elements is connected is connected to second two inputs with door
End, second connects the grid of corresponding one group of NMOS tube in remaining described each group NMOS tube with the output end of door；
Wherein, the second input logic unit is buffer or time delay elements, and the high level time delay elements determine the height electricity of output
Pulse-width.
8. according to claim 6 or claim 7 the method, which is characterized in that the failing edge delays time to control submodule control
The system turn-on time length of remaining each group PMOS tube and the initial time of conducting；The rising edge delays time to control submodule control
The system turn-on time length of remaining each group NMOS tube and the initial time of conducting.
9. a kind of method of the reduction ground bounce noise based on any one of claim 1 to claim 8 output driving circuit,
It is characterized in that, this method includes：
When rising edge signal is inputted the predrive module by the data output end DO, the PMOS input nodes receive
Failing edge signal is connected first group of PMOS tube in the PMOS drive modules, and triggers the failing edge delays time to control submodule
Low level pulse signal is exported, remaining is connected and organizes corresponding PMOS tube, to which the turn-on time for controlling remaining each group PMOS tube is long
The initial time of degree and conducting, ground bounce noise is reduced by the output driving resistance of dynamic regulation PMOS drive modules；
When the data output end DO keeps high level state, the PMOS input nodes keep low level signal, described
First group of PMOS tube continues to be connected in PMOS drive modules, and the failing edge delays time to control submodule exports high level, shutdown
Remaining group PMOS tube so that the output driving resistance of the output driving circuit increases, to enhance anti-highland bullet noise effect；
When failing edge signal is inputted the predrive module by the data output end DO, the NMOS input nodes receive
Rising edge signal is connected first group of NMOS tube in the NMOS drive modules, and triggers the rising edge delays time to control submodule
High level pulse signal is exported, remaining is connected and organizes corresponding NMOS tube, to which the turn-on time for controlling remaining each group NMOS tube is long
The initial time of degree and conducting, ground bounce noise is reduced by the output driving resistance of dynamic regulation NMOS drive modules；
When the data output end DO keeps low level state, the PMOS input nodes keep high level signal, described
First group of NMOS tube continues to be connected in NMOS drive modules, and the rising edge delays time to control submodule exports low level, shutdown
Remaining group NMOS tube so that the output driving resistance of the output driving circuit increases, to enhance anti-highland bullet noise effect.
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| CN201810660099.6A CN108494394B (en) | 2018-06-25 | 2018-06-25 | Low-noise and high-ground-elasticity-noise-resistant output driving circuit and method |
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| CN110677021A (en) * | 2019-09-23 | 2020-01-10 | 北京时代民芯科技有限公司 | Output drive circuit of anti ground bounce noise |
| CN113346893A (en) * | 2020-12-24 | 2021-09-03 | 澜起电子科技(昆山)有限公司 | Drive output circuit, chip and drive output method |
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