JP2962759B2 - Semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having an output buffer for preventing a malfunction caused by noise generated on a ground line, a power supply voltage line, and the like.

(Prior Art) In recent years, in a semiconductor integrated circuit, with the speeding up of an output buffer circuit and the enhancement of a large current driving capability, when such output buffers are simultaneously switched, they are generated on a ground line and a power supply voltage line inside an IC chip. Malfunction due to noise is a problem. As a countermeasure, a method of separating a ground line dedicated to the output buffer circuit from a ground line of a circuit inside the IC has been adopted. However, there are still the following problems. For example, the noise generated on the ground line inside the chip due to the simultaneous switching of a plurality of output buffers propagates to the transistor of the output buffer circuit which should output a constant level at this time, and a beard-shaped noise pulse is output to the output terminal. Occurs. This will be described below with reference to the drawings. Second
FIG. 7A is a model for explaining noise generated by N output buffers that are simultaneously switched. In the figure, SB _{1 to} SB _N are N output buffer circuits (hereinafter referred to as switch buffers) for switching, and MB is an output buffer circuit (hereinafter referred to as a monitor) whose output is to have a constant logic while the switch buffer SB switches. The input is at a constant level (for example, L level) of the voltage _EO . V _CC is a power supply voltage terminal outside the IC, GND is a ground terminal outside the IC, V _CCP is a power supply voltage line inside the IC chip, GND _P is a ground line inside the IC chip, and P _{1 to PN} are on the chip. external output terminals of the switch buffer SB is internal output terminal O ₁ ~ O _N of the output buffer SB in putting that out as an IC package pin, P _M and O _M monitor buffer MB
Each internal output terminal and an external output terminal of, C ₁ -C _N load capacitance connected to the external output terminals of the switch buffer SB, C _M is the load capacitance of the external output terminals O _M of the monitor buffer MB. L _{1 to} L _N and L _M are between the internal output terminals P _{1 to} P _N and P _M (PAD of the IC chip) and the output external terminals O _{1 to} O _N and O _{M of} each output buffer circuit. LV _CC is the parasitic inductance of wires, packages, etc., LV _CC is the parasitic inductance between the internal power supply voltage line V _CCP and the external power supply voltage terminal V _CC , L _GND is the parasitic inductance between the internal ground wire GND _P and the external ground terminal GND It is.
FIG. 2B schematically shows the internal circuits of the switch buffer SB and the monitor buffer MB.
_CCP and PMOS output transistor Q ₁ between each output P _X is, NMOS output transistor Q ₂ between the internal ground line GND _P and the output P _X
Are provided, and the gate of each output transistor is connected to the control circuit K. Now the input of N switches buffers SB ₁ to SB _N now is changed from H level to L level at the same time, the load capacitance C ₁ of the external output terminals O ₁ ~ O _N
A large discharge current _IDCH flows from 流 れ る C _N through the NMOS output transistor Q ₂ of each switch buffer SB, through the internal ground line GND _P , through the parasitic inductance L _GND, and to the external ground terminal GND. Because of this, the parasitic inductance
L _GND Internal ground line noise. (T is time.)
The internal ground line noise is propagated through the NMOS output transistor Q ₂ monitors the buffer MB to the external output terminal O _M cause noise pulse, thereby malfunctioning the other circuits connected thereto. In order to reduce such noise pulses generated in the output, it is sufficient to provide a large number of GND pins on the IC. Requires a GND pin and is not realistic. Therefore, Japanese Patent Application Laid-Open No. 61-109320 proposes an output buffer circuit designed so that the charge / discharge current when each output buffer is switched flows on average throughout the charge / discharge period and the peak current becomes smaller.

(Problems to be Solved by the Invention) However, in the prior art, a device that focuses solely on reducing the noise voltage generated in the internal ground line GND _P , such as reducing the peak value of the charge / discharge current flowing through the switch buffer. Has the following problems.

That is, the external output terminal O _M monitors the buffer when the noise voltage V _NG to internal ground line GND _P caused by resonance of the parasitic inductance L _M load capacitance C _M, the noise voltage V _NG of the above GND _P Noise voltage V with high peak value
_NM (> V _NG ) may occur. Therefore, a sufficient effect cannot be obtained even if only the peak of the charge / discharge current of the switch buffer is reduced, and the external output terminal O _{M of the} monitor buffer is not obtained.
There is a problem that a malfunction of a circuit such as an IC at the next stage which is used by being connected to the IC cannot be avoided.

It is an object of the present invention to provide a semiconductor integrated circuit which can prevent a malfunction of a next stage circuit due to a large noise generated at an external output terminal of the monitor buffer.

Also, an excellent output buffer circuit that can reduce noise generated at an output terminal that should be at a constant level even when used as a monitor buffer, in addition to reducing noise generated in the internal ground line even when increasing the speed and increasing the current. It is to provide a semiconductor integrated circuit having the following.

(Means for Solving the Problems) A first aspect of the present invention is that power is supplied from a first output buffer group and the same power supply voltage terminal and ground terminal as the output transistor group of the first output buffer group. Output transistor, and the on-resistance of this output transistor is
A R _1, together with the self-inductance L is parasitic to the output terminal of the output transistor, the semiconductor integrated and a second buffer should maintain a constant logic level when the logic change of the first output buffer group of In the circuit, when a load of the load capacitance C is provided at the output terminal, The values of the on-resistance R ₁ , the parasitic inductance L, and the load capacitance C are determined so as to satisfy the following condition.

A second aspect of the present invention is a semiconductor integrated circuit having a first output buffer group and a second output buffer which should maintain a constant logic level when the first output buffer group changes logic. Each output buffer group is
A first output transistor supplied with power by a first power supply terminal and a ground terminal, and a power supply supplied by a second power supply terminal and a second ground terminal, and the first output transistor operates after the first output transistor operates. A second output transistor that outputs the same logic as the first output transistor and has an output terminal connected to the output terminal of the first output transistor. A third output transistor to which power is supplied by the power supply terminal and the ground terminal, and a third output transistor to which power is supplied by the second power supply terminal and the second ground terminal. Output transistor having the same logic as that of the third output transistor and having an output terminal connected to the output terminal of the third output transistor.
And an output transistor, the ON resistance R ₂ of the third output transistor is characterized in that it has an on-resistance of the high-resistance than the on-resistance R ₃ of the fourth output transistor.

(Operation) The first aspect of the present invention is to increase the resistance value of the second output buffer, which should maintain a constant logic level when the first output buffer group is turned on, to be larger than a predetermined value as described above. , Can be lower than the noise voltage generated in the internal power supply line.

A second aspect of the present invention is that a plurality of output transistors are provided for each of the first output buffer group and the second output buffer,
Since the output transistor with a low on-resistance operates after the output transistor with a high on-resistance operates, the output transistor with a high-resistance on-resistance as long as the change rate of the voltage is large at the start of the logical value change Operates, and after a certain period of time has passed since the start of the change, the output transistor with a lower resistance operates in a state in which the rate of change of the voltage becomes slower, so that the change in the voltage is dispersed and noise generated at the output is significantly reduced. Can be.

(Embodiment) FIG. 1 is a model diagram for explaining a first embodiment of the present invention.

In the figure, a semiconductor integrated circuit 1 has input buffers I ₁ to
I _K , an internal circuit 2 to which the outputs of the input buffers I _{1 to} I _K are input, and an output buffer SB ₁ for driving a large current of the internal circuit 2
To SB _N and the first output section 3 consisting of the output terminal O _S1 ~ O _SN, buffer MB ₁ similarly to the same operation as the monitor buffer described above is the output buffer for the internal circuit 2 to MB _J
(Hereinafter referred to as monitor buffer) and their output terminals O
The second output section 4 consisting of _M1 ~ O _MJ, input buffer I ₁ ~I _K
And a power supply voltage terminal V _CCI and a ground terminal GND _{I of} the internal circuit 2,
Composed of an output buffer SB ₁ to SB _N and monitors the buffer MB ₁ to MB _J supply voltage terminal V _CCO and the ground terminal GND _O of.

Also, self-inductances L _{S1 to} L _SN are parasitic between P _{S1 to} P _SN constituting the internal output terminals (bonding pads) of the semiconductor chip and the output terminals O _{S1 to} O _SN constituting the external leads. Load capacitors C _{S1 to} C _SN are provided externally, and a self-inductance L _M1 is similarly provided between the internal output terminals P _{M1 to} P _MJ of the semiconductor chip and each of the output terminals O _{M1 to} O _MJ constituting external leads. LL _MJ are parasitic and load capacitances C _{M1 to} C _MN are provided outside. Furthermore, parasitic inductances L _VI and L _VO are provided between the internal power supply voltage terminal V _CCIP and the external power supply voltage terminal V _CCI, and between the internal power supply voltage terminal V _CCOP and the external power supply voltage terminal V _CCO. Parasitic inductances L _GI and L _GO are parasitic between _IP and the external ground terminal GND _I, and between the internal ground terminal GND _OP and the external lead and the ground terminal GND _O.

Here, the output buffer SB ₁ to SB _N of the first output section 3 and the noise source the internal power supply between the power supply voltage terminal V _CCO and the ground terminal GND _O when switched simultaneously to an output buffer for a large current It cannot be avoided. Therefore, when the monitor buffer MB ₁ to MB _J internal power supply is common second output section 4 is to output a constant logic level, is influenced by the noise of the first output section 3.

The first embodiment of the present invention, the above second output section 4 of the monitor on the buffer M _BX in the output transistor of the on-resistance R _MX, self-inductance parasitic to the output terminal P _MX of the monitor buffer M _BX When L _MX and load capacitance C _MX are used, Is set to satisfy the following.

This will be described with reference to the model diagram of FIG. 3 which is a simplified version of FIG.

In the figure, in the first output unit 3, the on-resistance R _S and the parasitic inductance L _S of the output transistor of each buffer are ₁ / _N of R because the output buffers SB _{1 to} SBN are connected in parallel. _S / N and L _S / N are obtained, and the load capacity C _S is N times as many as C _S × N. In the second output unit 4, the output is described as an output from an arbitrary monitor buffer _MBX .

As described above, at the same time momentarily large discharge current I _DCH flows by switching noise voltage wave V _G of the parasitic inductance L _GND workings peak value within the ground line GND _OP in V _GP occurs. Here, if there are many output buffers switching, the current flows through the on-resistance R _MX in Figure I
Since the I _DCH »I _MCH compared to _MCH, the noise voltage wave V _G is I
It can be considered that it does not depend on _MCH . Therefore, the internal ground line GND ₁
Assuming a square wave as shown in FIG. 4 (a) as a noise voltage wave generated at the monitor buffer _MBX , the noise voltage wave V _MX generated at the external output terminal of the monitor buffer _MBX is I can write

Such a calculation is a calculation of a transient response of a simple LCR circuit, and is described in detail, for example, in "Transient Phenomena and Waveform Analysis", Tokai University Press, 14th edition, pages 13 to 16, so only the results will be described.

The above equation (1) has a solution each for the following three conditions, the noise voltage wave V _M of the terminal O _MX at that time is as follows.

In the condition (A), the noise voltage wave V _MX terminal O _MX resonance at the center of FIG. 4 as waveform V _M1 shown in (a), H-level voltage V _GP noise voltage V _G of the internal ground line frequency And the waveform oscillates. That is, the noise voltage wave V of the terminal O _MX
The peak value of _MX is V _MPX , and the noise voltage V _G of the internal ground line GND _OP
If the peak value is V _GP, it becomes a condition (A) in the _{V MPX> V GP ...... (2} ).

Generally, L _M is small but about 15 nH. Assuming that C _MX = 100 PF as the load capacity, the resonance frequency is 130 MHz.
The oscillation is about 4 ns in a half cycle. Therefore, recent high-speed I
If C is connected to terminal _OMX , it will malfunction.

In condition (B), the noise wave V _MX terminal O _MX fourth
Will form slowly rising chasing noise voltage wave V _G of the internal ground line GND ₁ with a time constant 2L _MX / R _MX as waveform V _M2 shown in FIG. (A), when the peak value V _MXP, V _MPX ≤
V _GP . The condition (C) is a boundary between the two. As described above, the on-resistance R _MX of the output transistor of the monitor buffer MB _X is increased, Tosureba be smaller than the noise generated in a ground line noise occurring in terminal O _MX therein. Incidentally, a circuit simulation result of the noise waveforms generated noise waveform and the terminal O _MX occurring more realistic internal ground line GND _OP in the FIG. 4 (b) and (c). Here, FIG. 4 (b) In the case of, FIG. 4 (c) Is the case. Noise voltage wave V _G generated actual GND _OP as shown is close to a sine wave rather than a square wave, the terminal
At the time the O _MX noise voltage wave V _MX reaches a peak and begins to fall, thus the peak value V _MP of the noise voltage wave V _MX is smaller than the calculated assuming a V _G a square wave. FIG. 5 shows the peak voltage V _CP of the noise of the internal ground line and the monitor buffer M.
Noise Peter voltage V generated at the external output terminal O _MX of B _X
And _MPX, the relationship between the ON resistance R _MX of the output transistor in the monitor buffer MB _X shown by simulation.

In the simulation, L _{S1 to} L _SN = 15 nH, L _VO =
L _GO = 7.5nH, V _CC = 5V, C _{S1 to} C _SN = 100PF, C _MX = 50PF,
Further, the ON resistance R _S of the output transistor in the switching buffer was set to about 8Ω. The figure shows the case where the number of simultaneous switching N = 1 and the case where N = 8. As can be seen, the peak voltage V _GP noise generated inside the ground line is substantially constant independently of the on-resistance R _MX, whereas the peak voltage V _MPX monitor buffer M _BX is large when the on-resistance R _MX smaller It becomes R _MX <20Ω and V _MPX > V _GP , indicating the validity of the above discussion. In addition, the boundary condition of the above equation (1) Is calculated to be about 35Ω, which is larger than 20Ω in the graph. As described above, the noise waveform of the internal ground line is a square wave, so that V _MPX obtained by equation (1) is larger than the actual value. It is because it becomes big. So at least Then, V _MPX ≪V _GP (V _MPX is about half of V _{GP in} the example in the figure)
Can be.

As is apparent from the above, according to the present invention, when a plurality of output buffers are simultaneously switched, the on-resistance of the output transistor of the output buffer that outputs a constant logical level is output. Since a was, a noise voltage generated on the output terminal O _M can significantly smaller than the noise generated inside the ground line, it is possible to prevent malfunction of the next stage IC connected thereto.

 Next, a second embodiment of the present invention will be described.

FIG. 6 is a circuit diagram of an output buffer according to the second embodiment of the present invention. The output terminal P has a drain of the first PMOS output transistor Q11 and a second PMOS output transistor Q11.
The drain of 21, the drain of the first NMOS output transistor Q12, and the drain of the second NMOS output transistor Q22 are connected. Regarding the sources of these output transistors, the source of the first PMOS output transistor Q11 is connected to the first internal power supply voltage line V _CCOP1 and the source of the second PMOS output transistor Q21 is connected to the second internal power supply voltage line V _CCOP1.
CCOP2 has the source of the first NMOS output transistor Q12 connected to the first internal ground line GND _OP1 , and has the second NMOS output transistor Q12 connected to the first internal ground line GND _OP1.
The source of Q22 is connected to the second internal ground line GND _OP2 . In the drawing, K11 to K14 are control gates for controlling these output transistors, terminal C is a control signal input terminal for controlling whether the output is "High-Z" or "through", and terminal D is , A data input terminal. The data input terminal D includes a first input terminal of the two-input NAND gate K11, a second input terminal of the three-input NAND gate K13, and a two-input N
A first input terminal of the OR gate K12 and a three-input NOR gate K14
Is connected to the second input terminal. The control signal input terminal C is connected to the second input terminal of the two-input NAND gate K11, the third input terminal of the three-input NAND gate K13, and the input terminal of the inverter K10. Are the second input terminal of the two-input NOR gate K12 and 3
The input is connected to the third input terminal of the NOR gate K14.
Further, an output terminal P is connected to a first input of the above-described three-input NAND gate K13 and a first input of the three-input NOR gate K14. Each of these control gates is connected to the gate of each output transistor as follows. That is, 2-input NA
The output of the ND gate K11 is the gate of the PMOS output transistor Q11, the output of the three-input NAND gate K13 is the gate of the PMOS output transistor Q21, the output of the two-input NOR gate K12 is the gate of the NMOS output transistor Q12, and the three-input NOR gate. The output of K14 is connected to the gate of the NMOS output transistor Q22, respectively.

Next, the operation will be described. Control signal input terminal C is H
Level, the data input terminal D changes from the H level to the L level.
At this time, the outputs of the two-input NAND gate K11 and the three-input NAND gate K13 both become H level, and both the PMOS output transistors Q11 and Q21 are turned off.
The output of the NOR gate K12 becomes H level, and the first NM
The OS transistor Q12 turns on. Next, when the level of the output terminal P starts to decrease from the H level to the L level, the three-input NO
The output of the R gate K14 changes from L level to H level, turning on the second NMOS output transistor. in this way,
When the output terminal P changes from H level to L level, first the first
The second NMOS output transistor Q22 is turned on a certain time after the NMOS output transistor Q12 is turned on. Similarly, when the output terminal P changes from L to H level, the first PMOS output transistor Q11 is turned on and then the second PMOS output transistor Q21 is turned on. That is,
A first point of the present embodiment is that a first output transistor and a second output transistor of the same conductivity type are connected to an output terminal,
Means for controlling so that the second output transistor is turned on after a certain period of time from when the first output transistor is turned on when the level of the output terminal is changed, wherein each source of the first output transistor and the second output transistor is provided; Are connected to two independent potential supply lines for supplying the same potential in the chip. Note that the connection and operation of the control gate are well-known logic operations, and thus the details are omitted. However, it is noted that other circuit configurations may be used as long as each output transistor can be switched as described above. deep.

Now, generation and propagation of noise in such a buffer will be described. FIG. 7 (a) shows the buffer used for this buffer.
A part circuit diagram of this IC, load buffers SB ₁ to SB _N is switched simultaneously in FIG, MB is monitored buffer should output the time constant level. The internal configuration of each buffer is as shown in FIG. 6, and the terminal symbols correspond to each other. In addition, V _CC1 , V _CC2 , GND ₁ , and GND ₂ are provided as potential supply lines inside the IC, V _CC1 is the first internal power supply voltage line, V _CC2 is the second internal power supply voltage line, and GND ₁ is ,
The first internal ground wire, GND ₂ is a second internal ground line.

_{Further, V 1, V 2, P} 1 ~P N, P M, G 1, G 2 is the bonding pads on the IC chip, the external output terminal O ₁ ~ O _N and O _M is emanating outside the IC _Where V _CC is an external power supply voltage and GND is an external ground voltage. Further, L _{1 to} L _N are the parasitic inductances at the output terminals of the output buffer to be switched, L _M is the output terminal of the monitor buffer MB, and LV _O1 is between the first internal power supply voltage terminal V _CCOP and the external terminal V _CCO1 . L _V2 is between the second internal power supply voltage terminal V _CCOP2 and the external terminal V _CCO2 , L _GO1 is between the first internal ground terminal GND _OP1 and the external terminal GND _OP1 , L _G2
Are parasitic inductances between the second internal ground terminal GND _OP2 and the external terminal GND _O2 , and C _{1 to} C _N and C _M are load capacitances of the respective external output terminals.

As shown, each potential supply terminal (connected to V _CC1 , V _CC2 , GND ₁ , and GND _{2 in} FIG. 7) of each output buffer is independently connected to each chip-level potential supply line. Although not particularly described, it is assumed that the power supply voltage and ground of each control gate in FIG. 7A are supplied from a potential supply line dedicated to input or a potential supply line dedicated to internal logic circuits.

Figure 7 (b) is Figure 7 each of the output terminals P ₁ to P when the output terminal O ₁ ~ O _N of the plurality of buffers SB ₁ to SB _N is from H to L level at the same time in the circuit of (a) _N and each GND potential supply line G
ND _1, GND ₂ and output this time is the external output terminal O _MX voltage waveform monitor buffer MB should be L level constant.

Now, in the present invention, the first in each output buffer
Both the on-resistances R _P1 and R _N1 of the PMOS output transistor and the first NMOS output transistor are sufficiently large, that is, at least with respect to the self-inductance L and the load capacitance C parasitic to the output buffer. And FIG. 7B will be described under these conditions. First, each of the first NMOS output transistor of the output buffer SB ₁ to SB _N
Q12 is turned on, the charge of the capacitance C ₁ -C _N is discharged through the first internal ground line GND _1. Thus a large noise peaks V _GP1 to internal ground line GND ₁ above occurs as illustrated, the first NMOS output transistor Q1 of the monitor buffer MB
Propagates to the output terminal O _M through 2 causes noise peak V _MP1. Here, as described above, the on-resistance R _N1 of the first NMOS output transistor Q12 in each output buffer is , So V _MP1 ≪V _GP1 as shown in the figure. Then the second in SB ₁ to SB _N output buffer that each switch
Noise peak V _GP2 to internal ground line GND ₂ NMOS output transistor Q22 is turned on may occur. At this time, the V _GP2 «V _GP1 since become a voltage lower than the firing with the output terminal O ₁ ~ O _N of each switch buffer. In this case it is needless to say that sufficiently small noise peaks V _GP2 Taking lengthen the time until the first output transistor and the second output transistor from ON to turn on. The noise generated at this time is the second NMOS output transistor of the MB that is the monitor buffer.
Through Q22, causing noise peak V _MP2 and propagated to the external output terminal O _M. The on-resistance of the second NMOS output transistor needs to be reduced in order to increase the overall driving capability, and V _MP2 > V _GP2. However, since the noise peak V _GP2 of the internal ground line itself can be reduced, it is illustrated. As a result, the output noise peak V _MP2 can be sufficiently reduced. As described above, according to the present invention, even in an output buffer having a large current driving capability, it is possible to reduce noise generated at its output terminal.

The following shows a comparison between the conventional noise voltage and the specific noise voltage.

Fig. 8 (a) shows the current specification of the output current to be switched.
Shows the relationship between the simulation results of the total sum I _OL × N noise peak voltage generated inside the ground line GND ₁ and GND ₂ of I _OL.
Here, the current standard value I _OL (hereinafter abbreviated as I _OL ) is a value often used in catalogs and the like, and is the reciprocal of the ON resistance in each output buffer. Now, as 6mA the I _OL of the first NMOS output transistor Q12, the voltage V _CL of the load capacitance during discharge initiation and 5V, I of the second NMOS output transistor Q22
Assuming that _OL is 12 mA, the second NMOS output transistor Q22
The voltage _VCL of each load capacitance at the time of turning on is about 2.5V. In this case, the noise peak voltage generated on each of the internal ground lines GND ₁ and GND ₂ when the switch buffer switches eight at the same time is V _GP1 = 1V and V _GP2 = 0.7V as shown in the figure.
The V _GP1> V _GP2 become a degree. FIG. 8 (b)
Monitor buffer current specification value I _OL that is not switched during this time
And it is an example showing a relationship between the noise peak voltage occurring on the output terminal O _M of the output buffer. Occurs first noise peak voltage as described above, be on the curve in the noise peak V _GP1 = 1V occurring internal ground line GND _1, since propagating transmitted a large first output transistor Q12 of the ON resistance I _OL = 6mA point P and its magnitude is V _MP1 = 0.8V
About. The next noise peak voltage is V
_GP2 = 0.7V on the curve, the second output transistor Q22
And the point Q of I _OL = 12 mA is obtained, and its magnitude is V
_MP2 = about 0.8V. That is, V _MP2 > V _GP2 , but V
_{Since GP2} can be reduced, V _MP2 can also be reduced. At this time, the current standard value I _{OL for} one buffer is 18 mA, which is the sum of those of the two output transistors. Here, a description will be given of a case where the output transistor is divided into two parts by devising only the noise generated in the internal ground line and the ground line is shared by each output buffer. In this case, the first noise peak point P ', and the size thereof is V _MP1' of FIG become = 13V caused the output terminal O _M one,
The next noise peak is point Q 'in the figure, and its magnitude is V _MP2 ' = 0.9V. Therefore, in the output buffer having the same current standard value, the noise peak voltage generated at the output terminal can be reduced to about 60% of the conventional one in this embodiment.

In the present embodiment, the output transistor is divided into a plurality of parts, and the noise generated on the first ground line can be made smaller than that without dividing. It is therefore it is effective to make the ON resistance R _M of the first output transistor and large, but the previous formula It is not always necessary to satisfy. That is, at least the on-resistance of the first output transistor is made larger than the on-resistance of the second output transistor, and the ground potential or the power supply voltage potential is supplied to each output transistor via an independent internal supply line in the IC chip. With this arrangement, noise can be reduced as compared with the case where the potential is supplied to each output transistor by one potential supply line, and there is a corresponding effect.

The provision of a plurality of the same potential supply lines for the output transistors of each output buffer has already been reported by a member of the group of the authors, but the purpose is that the source of each output transistor is connected to the first potential supply line. A switch means is provided between each of the first and second potential supply lines, and one is used as a current path for charging and discharging the load, and the other is used as a potential supply path for maintaining a constant level of the load. It controls the switch means. In this embodiment, there is no particular need for a circuit for controlling the switch means, and the output transistor and the switch means do not need to be connected in series, so that the gain of the output transistor is not impaired by the switch means. have.

Further, the present invention can be variously modified within the scope of the gist, and the second output transistor itself is replaced with a plurality of output transistor groups connected in parallel, and these output transistor groups are sequentially turned on. It goes without saying that a modification such as control to be performed may be performed.

(Effects of the Invention) As described above, in the present invention, when a plurality of output buffers are simultaneously switched, the on-resistance of the output transistor of the output buffer in which the output is to be maintained at a constant level during this time is increased. The nose generated at an output terminal, which should be, can be made smaller than the noise generated in the potential supply line inside the IC.

In the present invention, the output of each output buffer is driven by a plurality of MOS output transistors, and the potential is supplied to each of the sources of the output transistors by independent potential supply lines in the IC chip. Can be reduced while increasing the current driving capability of the output buffer that should maintain the current level at a constant level.

Therefore, it is possible to obtain a semiconductor integrated circuit having a high-speed and internal current drive output buffer without fear of malfunction.

Although the ground noise has been described in each embodiment, it goes without saying that the same applies to the power supply voltage terminal V _CC .

[Brief description of the drawings]

FIG. 1 is a model diagram for explaining a first embodiment of a semiconductor integrated circuit according to the present invention, FIGS. 2 (a) and (b) are model diagrams of an output section of a conventional semiconductor integrated circuit, and FIG. 4 is a model diagram of noise generation, FIGS. 4 (a), (b) and (c) are simulation waveform diagrams of noise waveforms, and FIG. 5 is a graph showing simulation results showing the relationship between the on-resistance of the output transistor and the noise peak. FIG. 6 is a circuit diagram of a buffer in the semiconductor integrated circuit according to the second embodiment of the present invention. FIG. 7A is a model diagram of an output section of the semiconductor integrated circuit according to the second embodiment of the present invention. FIG. 7 (b) is a simulation waveform diagram of noise generated in the output of FIG. 7 (a), and FIG. 8 is a graph showing a simulation result showing a relationship between a current value and a noise peak voltage. I _{1 to} I _K …… Input buffer, SB _{2 to} SB _N …… Output buffer,
MB _{1 to} MB _J …… Output buffer, V _CCI …… Input buffer power supply voltage terminal, V _CCO …… Output buffer power supply voltage terminal, GN
D _I ...... input buffer ground terminal, GND _O ...... output buffer ground terminal, O _S1 ~O _SN ...... output terminals, O _M1 ~O _MJ ...... output terminal, C _S1 ~C _SN ...... load capacity, C _{M1 to} C _MJ ...... Load capacity.

Claims (3)

(57) [Claims] A first output buffer group; and an output transistor to which power is supplied by the same power supply voltage terminal and ground terminal as the output transistor group of the first output buffer group. But
A R _1, together with the self-inductance L is parasitic to the output terminal of the output transistor, the semiconductor integrated circuit and a second buffer should maintain a constant logic level when the logic changes the first output buffer group , When a load of the load capacitance C is provided at the output terminal, Characterized in that the values of the on-resistance R ₁ , the parasitic inductance L, and the load capacitance C are determined so as to satisfy the following conditions. 2. A semiconductor integrated circuit comprising: a first output buffer group; and a second output buffer that should maintain a constant logic level when the first output buffer group changes logic. Each of the buffer groups is supplied with power from a first power supply terminal and a ground terminal, and is supplied with power from a second power supply terminal and a second ground terminal. After operating, the same logic as the first output transistor is output, and
A second output transistor having an output terminal connected to an output terminal of the first output transistor, wherein the second output buffer is supplied with power from the first power supply terminal and a ground terminal A third output transistor, and power is supplied from the second power supply terminal and the second ground terminal, and after the third output transistor operates, outputs the same logic as the third output transistor. and a fourth output transistor having a third output terminal and connected to an output terminal of the output transistor, the oN resistance R ₂ of the third output transistor, the fourth
The semiconductor integrated circuit characterized by having a high resistance on-resistance than the on-resistance R ₃ of the output transistor. 3. The semiconductor integrated circuit according to claim 2,
When the load capacitance C is provided at the output terminal due to the self-inductance L parasitic on the output terminal of the second output buffer, Wherein the values of the on-resistance R ₂ , the parasitic inductance L, and the load capacitance C are determined so as to satisfy the following conditions.