JPH0341818A - Buffer circuit - Google Patents

Abstract

PURPOSE:To obtain a high speed buffer circuit in which overshoot and undershoot of an output level is suppressed by controlling a current extracted by 1st and 2nd control sections from a common connecting point of a MOS transistor(TR) between an output terminal and a 1st or a 2nd power supply. CONSTITUTION:When an input at an input terminal 11 changes from an H level to an L level, a P-channel TR(PCT) 17 is turned on and a PCT 15 and a PCT 12 of an inverter 14 increase the output L level to an H level. Thus, the output signal reaches rapidly near the H level and since the PCT 17 is cut off, the output capability to the H level is attenuated and when the voltage at the output terminal 19 goes to a power voltage, only the PCT 12 outputs an H level to the terminal 19 and made stable. Thus, an instantaneous current being a cause to overshoot and undershoot of the output signal is suppressed at the end of output in the transient state changing L to H or H to L at the output terminal of the PCTs 15, 17 and NCTs 16, 18.

Description

[Detailed description of the invention] [Object of the invention] (Industrial application field) The present invention relates to a buffer circuit.

(Prior Art) A buffer circuit according to the prior art will be described below with reference to FIGS. 4 to 6.

Conventionally, for outputs that require high-speed operation, inverters with large current driving power are used as amplifiers to speed up charging and discharging of the load capacitance connected to the output terminal, thereby increasing the speed of signal rise and fall times. It has been operating at high speed.

FIG. 4 shows the output waveform of a conventional high-speed output circuit.

When using an inverter in this way and operating it at high speed,
Outputs a level higher than the normal signal (overshoot)
This has caused problems such as outputting signals at a lower level than the normal signal (undershoot), causing malfunctions in other circuits connected to these outputs, and deterioration of characteristics.

The cause of overshoot and undershoot is said to be due to electromotive force generated during charge transfer due to parasitic inductance components inside the IC chip, the lead frame, and the wiring to the local power source.

Therefore, if the instantaneous current is large, a larger electromotive force is generated, so by reducing this instantaneous current, overshoot and undershoot have been suppressed.

In conventional inverters, methods for reducing the instantaneous current include, for example, reducing the size of the transistor (W/L) or connecting a resistor to the gate of the output transistor connected to the output terminal. A conventional buffer circuit and its output waveform are shown in FIGS. 5 and 6.

As shown in Figure 5, the conventional buffer circuit has an input terminal (5
1) and the output terminal (52), the inverter (53) (5
4) (55) are connected in parallel, and resistors (56)' (57) are connected to the gates of MOS transistors (output transistors) constituting these inverters. The inverters of the buffer circuit configured in this manner do not operate simultaneously, but operate sequentially with a delay, resulting in a reduction in instantaneous current.

The output waveform from this circuit is shown in FIG.

As you can see from this output waveform, overshoot and undershoot can be suppressed in this kind of circuit, but
Rise (tr) and fall (tf') of output signal
This takes time and goes against high-speed operation.

(Problem to be Solved by the Invention) In the buffer circuit as described above, each inverter (53) (54 ) delaying the operation of (55);
Although the instantaneous current can be reduced, the rise time and fall time of the output signal are slowed down, which has been a big problem for LSIs that require high speed.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the conventional buffer circuits as described above, and to provide a buffer circuit capable of high-speed operation while suppressing overshoots and undershoots seen in output signals.

[Structure of the Invention] (Means for Solving the Problem) In order to achieve the above object, the present invention includes an inverter connected to an input terminal, each gate connected to the input terminal, and each A first MOS transistor and a second MOS transistor connected in series.
MOS transistor, a first control unit connected in series between the first power supply and the first MOS transistor, and a second control unit connected in series between the second power supply and the second MOS transistor. and a first and second MOS
The output terminal of the inverter is connected to the common connection point of the transistor, and the first and second control units control the amount of current between the output terminal taken out from the common connection point and the first or second power source. Provided is a buffer circuit that controls a buffer circuit.

(Function) According to such a buffer circuit, the human input signal from the input terminal changes from low level to high level or high level.
In a transient state that changes from a high level to a low level, the ability of the output transistor to charge and discharge the load capacitance is controlled by the state of the output voltage, and at the moment of the rise or fall of the output signal, the output transistor is It is possible to provide a buffer circuit that has the function of providing driving capability to the driver and suppressing the driving capability when it is no longer necessary.

(Embodiment) A buffer circuit (CMOS output buffer circuit) according to an embodiment of the present invention will be described below with reference to FIGS. 1 to 3.

FIG. 1 is a circuit diagram of a CMOS output buffer circuit according to a first embodiment of the present invention. FIG. 3 shows the output waveform of this CMOS output buffer circuit.

This CMOS output buffer circuit has a P-channel transistor (12) and an N-channel transistor (13) connected in series between a power supply and ground, and a human input signal from an input terminal (11) is supplied to each gate. an inverter (14) connected in series between the power supply and ground, P channel transistors (15), (17) and N
Channel transistors (1B) and (18) are connected in series, and an inverter (14) is connected to the gates of the P channel transistor (17) and the N channel transistor (18).
) is input, and the output signal of the P-channel transistor (
15) and an inverter (20b) having a control section (20a) to which an input signal from an input terminal is supplied to the N-channel transistor (18).

First, when the input to the input terminal (11) is at Htgh level and the output is at Low level, the gate is connected to the output terminal (11).
(9>, P-channel transistor (17) connected
is in an ONL state in response to the Low level of the output terminal <19). When the input to the input terminal (11) changes from High level to Low level, since the P-channel transistor (17) is ON, the P-channel transistor (15) and the P-channel transistor (( 2) both try to raise the output low level to high level. (Fig. 3 ■) Therefore, the output signal rapidly rises to near the high level, but as the output signal level increases, the P-channel transistor ( 17) tries to cut 0FFL, so the output ability to High level gradually decreases,
When the output terminal (19) becomes the power supply voltage -l VihP 1 or higher, the output terminal (19) is set to High level by only the P-channel transistor <12> of the inverter (I4).
Output level and stabilize. (Fig. 3 ■ to ■) Next, when the input signal of the input terminal (11) changes from Low level to High level, the N-channel transistor 08) whose gate is connected to the output terminal receives the High level of the output terminal. By being ONL, the output High level of both the N-channel transistor (i6) and the N-channel transistor (13) of the inverter (14) is set to Low.
trying to lower the level. (Fig. 2 ■) Therefore, the output signal rapidly drops to near the low level, but in response to this low level, the N-channel transistor (18) is cut.
As it tries to go OFF, the output ability to low level gradually decreases, and the N of the output terminal inverter (14) decreases.
The output terminal (
19) outputs a low level and stabilizes (Fig. 3 ■~
■).

According to such a CMOS output buffer circuit, the output terminals of the P-channel transistors (15) (17) and N-channel transistors (1B) and (1g) change from Low to High.
This contributes to speeding up the rise time and fall time of the output signal in a transient state where the output signal is about to change to a high level or from a high level to a low level.

The output signal change is completed (power level or GND
(-1 VthP l or Ih vthN), the output capability is attenuated and the output waveform becomes gentle. Therefore, an output waveform as shown in FIG. 3 can be obtained.

In other words, it can be seen that the instantaneous current that caused overshoot and undershoot is suppressed in the areas (2) and (2) in FIG. 3 near the completion of output.

FIG. 2 is a circuit diagram of a CMOS output buffer 7 circuit according to a second embodiment of the present invention.

This CMO3 output buffer 7 circuit is an inverter in which a P-channel transistor (22) and an N-channel transistor (23) are connected in series between the power supply and the ground, and each gate is supplied with a human input signal from an input terminal. P-channel transistors (25), (27) and N-channel transistors (2B), (2g) are connected in series between (24), the power supply and the ground, and the gate of the P-channel transistor (27) is connected to the P-channel transistor The potential at the common connection point of the transistors (25) and (27) is supplied, the potential at the common connection point of the N-channel transistors (2B) and (28) is supplied to the gate of the N-channel transistor (28), and the potential at the common connection point of the N-channel transistors (2B) and (28) is supplied. Channel transistor <25>
And the N-channel transistor (26) has a human input signal <
21) to which an input signal is supplied from the control unit (301).
), (302) and an inverter (31).

First, when the input of the input terminal (21) is at High level and the output is at Low level, when the human power changes from High level to Low level, the P-channel transistor (
22) , (25) is ONL. By turning on the P-channel transistor (25), the P-channel transistor (27) attempts to raise the ONL output level to High level. As the output signal level increases, the P-channel transistor (27) becomes highly resistant and the output terminal (
When the voltage of 29) exceeds the power supply voltage -VthP1, the P-channel transistor (22) of the inverter (24)
A high level is output to the output terminal (29) and stabilized.

Next, when the input signal changes from Low level to High level, N channel transistor (23), N channel transistor (2B), (28
) attempts to lower the output High level to the Low level. When the output level approaches Low level, the N-channel transistor (28) becomes high resistance, and when the voltage at the output terminal (29) becomes less than VthN, it becomes Low level only by the output of the N-channel transistor (23) of the inverter (24). is output and stabilized.

According to such a CMO3 output buffer 7 circuit, as in the first embodiment, at the moment when the human power changes from Low level to High level or from High level to Low level, the P channel transistors (25), (27)
The N-channel transistors (2B) and (28) contribute to faster rise and fall times, and their outputs are attenuated before the output signal completes its change. As a result, an output waveform similar to that shown in FIG. 3 can be obtained.

Therefore, it is possible to obtain a CMO8 output buffer 7 circuit that can suppress overshoot and undershoot and operate at high speed.

Note that the input terminals (11) and (21) may be connected to a logic circuit and connected to an output terminal (19) and an output pin.

[Effects of the Invention] As described in detail above, according to the present invention, it is possible to provide a CMOS output buffer circuit capable of high-speed operation while suppressing overshoot and undershoot of the output level.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a CMOS output buffer circuit according to a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a CMOS output buffer circuit according to a second embodiment of the present invention, and FIG. Figure 4 shows the output waveform of a CMOS output buffer circuit according to an embodiment of the present invention, Figure 4 shows the output waveform of a conventional high-speed output circuit, and Figure 5 shows a buffer circuit according to the prior art. Circuit Diagram FIG. 6 is a diagram showing an output waveform from a CMOS output buffer circuit according to the prior art. 11.21.51...Input terminal. 12.15, 17.22, 25.27...P channel transistor. 13.16, 18, 23, 26.2111...N channel transistor. 14.24.53.54.55...Inverter. 19.29.52...Output terminal 56.57...Resistor.

Claims (4)

[Claims] (1) an input terminal, a first MOS transistor and a second MOS transistor whose respective gates are connected to the input terminal and which are connected in series; a first power supply and the first MOS transistor; a first control section connected in series between a second power supply and the second MOS transistor; a first control section connected in series between the first MOS transistor and the second MOS transistor; and a means for outputting an inverted signal with respect to an input signal input to the input terminal, the first and second control sections being connected to the series connection point in response to the inversion signal. A buffer circuit that controls the amount of current between an output terminal connected to the first or second power source. (2) between an inverter connected to an input terminal, a first MOS transistor and a second MOS transistor whose respective gates are connected to the input terminal, a first power supply, and the first MOS transistor; a first control section connected in series between the first MOS transistor and the second MOS transistor; and a second control section connected in series between the second power supply and the second MOS transistor. The MOS transistors are connected in series, and the output terminal of the inverter is connected to a common connection point, and the first and second control sections are connected between the output terminal and the first or second power source. A buffer circuit characterized by controlling the amount of current. (3) between an inverter connected to an input terminal, a first MOS transistor and a second MOS transistor whose respective gates are connected to the input terminal, and a first power supply and the first MOS transistor; a third MOS transistor connected in series; and a fourth MOS transistor connected in series between the second power supply and the second MOS transistor; the first and second MOS transistors are connected in series; and an output terminal of the inverter is connected to a common connection point of the first and second MOS transistors and to respective gates of the third and fourth MOS transistors. circuit. (4) between an inverter connected to an input terminal, a first MOS transistor and a second MOS transistor whose respective gates are connected to the input terminal, and a first power supply and the first MOS transistor; a third MOS transistor connected in series; and a fourth MOS transistor connected in series between a second power supply and the second MOS transistor, the gate of the third MOS transistor is connected to the third MOS transistor. 1 M
connected to a common connection point of the OS transistor and the third MOS transistor, and a gate of the fourth MOS transistor is connected to the second MMOS transistor;
connected to a common connection point of the OS transistor and the fourth MOS transistor, the first and second MOS transistors are connected in series, and the output terminal of the inverter is connected to the common connection point of the first and second MOS transistors. A buffer circuit characterized in that it is connected to a common connection point.