JPH03266519A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction of a circuit of a next stage and to attain high speed processing and large current by selecting an onresistance, parasitic inductance and a load capacitance so as to satisfy a specific condition when a capacitive load is provided to an output terminal. CONSTITUTION:When a load whose capacitance C is provided to an output terminal, an ON-resistance R1, a parasitic inductance L and a load capacitance C are selected so as to satisfy the condition of equation I. That is, when 1st output buffer groups SB1-SBN are turned on, the resistance of 2nd output buffers MB1-MBf to keep a prescribed logic level is selected larger than a prescribed value to decrease noise voltage caused in an internal power supply line. Thus, the semiconductor integrated circuit precluding malfunction and having output buffers at fast speed for large current drive is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having an output buffer that prevents malfunction due to noise generated in a ground line, power supply voltage line, etc.

(Prior Art) In recent years, in semiconductor integrated circuits, as output buffer circuits have become faster and have a higher current drive capability, when these output buffers switch simultaneously, problems occur on the ground line and power supply voltage line inside the IC chip. Malfunctions due to noise are a problem. As a countermeasure for this problem, methods such as separating the ground line dedicated to the output buffer circuit from the ground line of the circuit inside the IC have been taken, but the following problems still occur.

For example, noise generated in the ground line inside the chip due to simultaneous switching of multiple output buffers is propagated to the transistor of the output buffer circuit, which is supposed to output a constant level, and a whisker-shaped noise pulse is generated at the output terminal. occurs. This situation will be explained below using the drawings.

FIG. 2(a) is an illustrative model of the noise caused by N output buffers switching simultaneously.

In the figure, SB1 to SBN are N output buffer circuits that switch (hereinafter referred to as switch buffers), and MB is an output buffer circuit whose output should have a constant logic while switch buffer SB switches (hereinafter referred to as monitor buffer). The input voltage is at a constant level (for example, L level) of voltage E0. Also, vcc
is the power supply voltage terminal outside the IC, GND is the ground terminal outside the IC, vccp is the power supply voltage line inside the IC chip, GND,
is the ground line inside the IC chip, P1~PN are the internal output terminals 01~O of each output buffer SH on the bat on the chip.
N is engineering Ci'? The external output terminals of each switch buffer SB come out as cage pins, PM and ON are the internal and external output terminals of monitor buffer MB, respectively, and C
1 to CN are load capacitances connected to external output terminals of each switch buffer SB, and CM is a load capacitance of external output terminal OM of monitor buffer MB. In addition, L, ~LN and RI are the internal output terminals P, ~PN and P of each output buffer circuit, (PAD of IC chip) and output external terminal 01.
~ It is the parasitic inductance of wires, packages, etc. between ON and 0M, and Lvco is the internal power supply voltage line ■ cc
LoND between p and the external power supply voltage terminal vcc is determined by the parasitic inductance between the internal ground line GNDP and the external ground terminal GND. FIG. 2(b) schematically shows the internal circuits of the switch buffer SB and monitor buffer MB.
An NMOS output transistor Q2 is provided between the MO8 output transistor Q1 and the internal ground line GND and the output PX, and the terminal of each output transistor is connected to the control circuit K. Now, if the inputs of N switch buffers SB1 to SBN change from H level to L level at the same time, NMO8 of each switch buffer SB is calculated from the load capacitances C1 to CN of external output terminals 01 to ON.
The parasitic inductance L passes through the output transistor Q2 and the internal ground line GND. A large discharge current IDcH momentarily flows through ND to external ground terminal GND.

This causes the parasitic ground line noise. (t is time.) This internal ground line noise
It propagates to the external output terminal OM through the NMO8 output transistor Q2, generates a noise pulse, and causes other circuits connected to it to malfunction. In order to reduce these noise pulses generated in the output, it is possible to install a large number of GND bins on the IC, but since the speed of the output buffer and the large current drive capability are significantly increased, it is necessary to install a large number of GND bins in order to obtain a sufficient effect. This is not practical as it requires a GND pin. Therefore, Japanese Patent Laid-Open No. 61-109320 and others have proposed an output buffer circuit designed so that the charging and discharging current when each output buffer switches flows on average throughout the charging and discharging period, and the peak current is small.

(Problem to be solved by the invention) However, in the prior art, attention has been focused only on reducing the noise voltage generated in the internal ground line GND, such as reducing the peak value of the charging/discharging current flowing through the switch buffer. Many improvements have been made to this system, and it has the following issues.

That is, when the noise voltage "NG" occurs on the internal ground line GNDP, the noise voltage "NG" of the above GND occurs on the external output terminal OM of the monitor buffer due to the resonance phenomenon of the parasitic inductance LM and the load capacitance CM. A noise voltage vNM(>vNo) may occur.

For this reason, even if only the peak of the charge/discharge current of the switch buffer is reduced, a sufficient effect cannot be obtained, and the next-stage IC connected to the external output terminal OM of the monitor buffer
The problem was that malfunctions of circuits such as these cannot be avoided.

An object of the present invention is to provide a semiconductor integrated circuit that can prevent malfunction of the next stage circuit due to large noise generated at the external output terminal of the monitor buffer.

In addition, even with higher speeds and higher currents, it is possible to reduce the noise generated in the internal grounding wire, and even when used as a monitor buffer, it is an excellent output buffer circuit that can reduce the noise generated at the output terminal, which should be at a constant level. An object of the present invention is to provide a semiconductor integrated circuit having the following features.

(Means for Solving the Problem) The first aspect of the present invention is that power is supplied from the same power supply voltage terminal and ground terminal as the first output buffer group and the output transistor group of the first output buffer group. has an output transistor whose on-resistance is R
1, the semiconductor integrated circuit has a self-inductance L parasitic on the output terminal of the output transistor, and a second buffer that is to maintain a constant logic level when the logic of the first output buffer group changes. In, when a load of load capacity C is provided to the output terminal, R1≧
This device is characterized in that the on-resistance R1, the parasitic inductance, and the value of the load capacitance C are determined so as to satisfy the negative condition at 2V Goff.

A second aspect of the present invention is a semiconductor integrated circuit having a first output buffer group and a second output buffer that is to maintain a constant logic level when the logic of the first output buffer group changes. The one output buffer group each has a first output buffer that is powered by a first power supply terminal and a ground terminal.
Power is supplied from the output transistor, the second power supply terminal, and the second ground terminal, and after the first output transistor operates, it outputs the same logic as the first output transistor, and the first output transistor outputs the same logic as the first output transistor. a second output transistor having an output terminal connected to the output terminal of the output transistor; the second output buffer has a third output transistor powered by the first power supply terminal and the ground terminal; a transistor, this second power supply terminal and the second
Power is supplied from the ground terminal of the third output transistor, and after the third output transistor operates, it outputs the same logic as the third output transistor, and has an output terminal connected to the output terminal of the third output transistor. The fourth output transistor is characterized in that the on-resistance R2 of the third output transistor is higher than the on-resistance R3 of the fourth output transistor.

(Function) As described above, the first aspect of the present invention is to increase the resistance value of the second output buffer, which should maintain a constant logic level when the first output buffer group is turned on, by a predetermined value. Therefore, the noise voltage generated in the internal power supply line can be made smaller.

Further, the second aspect of the present invention is that the first output buffer group and the second output buffer group
A plurality of output transistors are provided for each of the output buffers, and the output transistor with a high on-resistance operates after which the output transistor with a low on-resistance operates, so that the rate of change in voltage at the start of a change in logic value is reduced. While the on-resistance is large, the high-resistance on-resistance output transistor operates, and after a certain period of time has elapsed after the voltage change rate has slowed down, the low-resistance output transistor operates, so that the voltage change is dispersed. , the noise generated in the output can be significantly reduced.

(Embodiment) FIG. 1 is a model diagram for explaining a first embodiment of the present invention.

In the figure, a semiconductor integrated circuit 1 has input buffers I, ~I
K, an internal circuit 2 which receives the outputs of the input buffers 1 to IK, a first output section 3 consisting of output buffers SB1 to SBN for large current driving of this internal circuit 2, and output terminals OS1 to OsN of these; Buffers MB1 to MB are also output buffers of the internal circuit 2 and operate in the same manner as the monitor buffers described above.

(hereinafter referred to as monitor buffer) and these output terminals O
Second output section 4 consisting of M1 to OMJ, input buffer 1
1 to IK, power supply voltage terminals ccx and ground terminal GND of internal circuit 2, power supply voltage terminals vco of output buffers SB1 to sBN and monitor buffers MB1 to MB. and a ground terminal GNDo.

In addition, there is a self-inductance between Ps1 to PSN, which constitute the internal output terminals (ponding pads) of the semiconductor chip, and each output terminal, 081 to 0sNO, which constitute the external leads.
81~”SN is parasitic and external load capacitance C8
Similarly, self-inductance M is provided between the internal output terminals PM1 to PMJ of the semiconductor chip and each output terminal OM1 to OMJ constituting the external lead.
1~LMJ is parasitic, and external load capacitance CM1
~CMN is provided. Furthermore, the internal power supply voltage terminal V
. between CIP and external power supply voltage terminal VCCI, and between internal power supply voltage terminal vccop and external power supply voltage terminal V. There are parasitic inductances "Vl" and "Lvo" between the internal grounding terminal GND, P and the external grounding terminal GNDx, the internal grounding terminal GNDo, and the external lead between the internal grounding terminal GNDo and the external ground terminal GNDo.
There is a parasitic inductance L between them. 1. LGo is parasitic.

Here, the output buffers SB, ~SBN of the first output section 3
is an output buffer for large currents, so when switching at the same time, the power supply voltage terminal V. co and ground terminal GND
It is unavoidable that this becomes a noise source for the internal power supply between the two terminals. Therefore, when the monitor buffers MB1 to MB of the second output section 4, which share the same internal power supply, try to output a constant logic level, they are affected by the noise of the first output section 3.

In the first embodiment of the present invention, the on-resistance of the output transistor in any monitor buffer MBX of the second output section 4 is RMX' and the self-inductance parasitic to the output terminal PMx of this monitor buffer MBx is Mx, and When the load capacity is CMX, these relationships are set to satisfy RMX≧〆η5Z77.

This will be explained using the model diagram of FIG. 3, which is a simplified version of FIG. 1.

In the figure, in the first output section 3, the on-resistance Rs and parasitic inductance L8 of the output transducer of each buffer are 1/N of the number of output buffers SB1 to SBN, so the on-resistance Rs and parasitic inductance L8 are ^, and the load capacity C8
is multiplied by N times and becomes C6XN. Further, the second output section 4 is described as an output of an arbitrary monitor buffer MBX.

As mentioned above, simultaneous switching causes a momentary large discharge current. H flows and parasitic inductance occurs. The peak value V is applied to the internal grounding line GNDoP due to the action of ND. , the noise voltage wave V. occurs. Here, if there are many switching output buffers, the on-resistance R in the diagram
The current flowing through MX is CH > IMC compared to IMCH.
)I, so the noise voltage wave V. may be considered to be independent of IMcH. Therefore, assuming a square wave as shown in FIG. 4(, ) as the noise voltage wave generated on the internal grounding line GND1, the noise voltage wave vMx generated on the external output terminal of the monitor buffer MBX is a “Phenomena and Waveform Analysis” Tokai University Press 14th edition P13-P
16, so only the results will be described.

The above equation (1) has solutions for the following three conditions, and the noise voltage wave VM at the terminal OMx at that time is as follows.

(A) RMX < 2r (B) RMx = 2V 7; Ma (C)
RMX) 2 meters ζ 7 lines; Under condition (A), the noise voltage wave vM of the terminal OMX
X is the noise voltage V of the internal ground line, as shown in the waveform vM shown in FIG. 4(,). H level voltage V. , the waveform vibrates at a resonance frequency %π〆LMXCy x (Hz).

That is, the peak value wov of the noise voltage wave vMx at the terminal OMX
If the peak value of the noise voltage V of internal grounding line GNDo is , then under condition (A), "MPX >vCP"' (2)
becomes.

Generally, the LM is as small as about 15 nH, and assuming that the load capacitance is CMx=100PF, the resonant frequency is 130 MHz, and the vibration has a half period of about 4 ns. Therefore, if a recent high-speed IC is connected to the terminal OMX, it will malfunction.

Under condition (B), the noise wave MX at the terminal OMx has a time constant 2LMX as shown in the waveform vM2 shown in Fig. 4(a).
/RMx is the noise voltage wave V of the internal grounding line GND1. , and if this peak value is VMPX, then vMPX≦voP. Moreover, condition (C) serves as a boundary between the two. As described above, by increasing the on-resistance RMx of the output transistor of the monitor buffer MBX so that R,Ax≧2f;7η;, the noise generated at the terminal OMx can be made smaller than the noise generated at the internal ground line. Note that circuit simulation results of the noise waveform occurring on the internal ground line GNDo and the noise waveform occurring at the terminal OMX, which are more realistic, are shown in FIGS. 4(b) and 4(C). Here, FIG. 4(b) shows the case when RMx<2〆ζf; FIG. 4(c) shows the case when RMX>24f;. As shown in the figure, a noise voltage wave V occurs in the actual GNDo. is more like a sine wave than a square wave, and the terminal OMx
At the point when the noise voltage wave vMx reaches its peak, it has started to fall, so the peak value vMP of the noise voltage wave vMX
is V.

is smaller than the calculation assuming that is a square wave. In Figure 5,
Peak voltage of internal ground wire noise, V. The relationship between the noise beater voltage vMPX generated at the external output terminal OMX of the monitor buffer MBx and the on-resistance RMX of the output transistor in the monitor buffer MBX is shown in the simulation.

In the simulation, Ls1~LSN = 1
5nH.

Lvo=Lo. =7,5nH2■,. =5v, Cs1~
C5N=1ooPF.

CMx=50PF, and the on-resistance R8 of the output transistor in the switching buffer is about 8Ω. In the figure, the simultaneous switching number N=1 and N=
8 is shown. As can be seen from the figure, the peak voltage V of the noise generated on the internal ground line. P is almost constant without depending on the on-resistance RMX, and the peak voltage vM of the one-sided monitor buffer MBx, x becomes sharper as the on-resistance RMX becomes smaller. When R, The validity of the argument is shown.In addition, the above (1)
Calculating the boundary condition R8=2VTPanji5- of the equation gives 35
It is about Ω, which is larger than 200 in the graph, but as mentioned above, this difference is due to the VMPX obtained by equation (1) by making the noise waveform of the internal grounding wire a square wave.
This is because the value becomes larger than the actual value. Therefore, if at least RMX≧2VT4'MX-, then VMPX<v
6P (in the example shown, vMPX is V.

(approximately half of that).

As is clear from the above, in the present invention, when a plurality of output buffers switch simultaneously, the on-resistance RMx of the output transistor of the output buffer that outputs a constant logic level is set to RMx≧2u, so that the output terminal O
The noise voltage generated in M can be made much smaller than the noise generated in the internal ground line, and malfunction of the next stage IC connected thereto can be prevented.

Next, a second embodiment of the present invention will be described.

FIG. 6 is a circuit diagram of an output buffer in a second embodiment of the invention. The drain of the first PMO8 output transistor Qll, the drain of the second PMOS output transistor Q21, the drain of the first ONMO8 output transistor Q12, and the drain of the second NMO3 output transistor Q22 are connected to the output terminal P. . For each source of these output transistors, the first P
The source of the MO8 output transistor Qll is connected to the first internal power supply voltage line vCCOPi, and the source of the second PMO8 output transistor Q21 is connected to the second internal power supply voltage line VccOP.
2, the first NMO8 output transistor boss 12 is connected to the first internal ground line GNDo, and the second NMO8 output transistor boss 22 is connected to the second internal ground line GNDo.
Connected to DOP2.

Further, Kll~14 in the figure is a control gate that controls these output transistors, and the terminal C is a control signal input terminal that controls whether the output is "High-Z" or "through". The terminal is a data input terminal.

The data input terminals include 11 first input terminals for a 2-man powered NAND gate, 13 second input terminals for a 3-man powered NAND gate, 12 first input terminals for a 2-man powered NOR gate, and 12 first input terminals for a 3-man powered NOR gate. 14 second input terminals to the NOR gate. In addition, the control signal input terminal C is connected to a second input terminal of 11 for a two-manpower NAND gate, and a second input terminal for a three-manpower NAND gate.
13 third input terminals to the ND gate and the inverter KI
The output terminal of this inverter KIO is connected to the input terminal of the inverter KIO.
and the third input terminal of a three-power NOR gate K14. Furthermore, the output terminal P is
13 first inputs to human powered NAND gate and 3 human powered NO
It is connected to the first input of R gate K14. Each of these control darts is connected to the gate of each output transistor as follows.

That is, the output of the 2-man NAND gate Kll goes to the gate of the PMO 8 output transistor Qll, the 13 output to the 3-man NAND gate goes to the gate of the PMOS output transistor Q21, and the 12 output to the 2-man power NOR gate goes to the gate of the NMO 3 output transistor Q12. In addition, 14 outputs are added to the 3-man NOR dart, NMO 8 outputs and 22 output transistors.
connected to each port.

Next, the operation will be explained. When the control signal input terminal C is at H level, when the data input terminal goes from H level to L level, two-man NAND gate Kll and three-man NAND gate
AND 13 outputs both go to H level and PM
Both the O8 output transistors Qll and G21 are turned off, and the output of 12 to the two-manufactured NOR gate becomes H level, and the first NMO8 output transistor 12 is turned off.

Next, when the level of the output terminal P starts to fall from the H level to the L level, the output of the three-manufactured NOR gate 14 changes from the L level to the H level, and the second NMOS output transistor is turned on. In this way, the output terminal P changes from H to L.
When changing to the level, first the first NMOS output transistor Q12 is turned on, and after a certain period of time, the second NMOS output transistor Q12 is turned on.
O8 output to output transistor 22. Similarly, when the output terminal P changes from L to H level, the first PMO8 output transistor Qll is turned on and then the second PMO3 output transistor Qll is turned on. That is, the first point of this embodiment is that the first point of the same conductivity type is connected to the output terminal.
The output transistor and the second output transistor are connected, and when the level of the output terminal changes, a control means is provided so that the second output transistor is turned on after a certain period of time after the first output transistor is turned on. The sources of the first output transistor and the second output transistor are connected to two independent potential supply lines within the chip that supply the same potential. The connection and operation of the control gate is a well-known logical operation, so the details are omitted, but it should be noted that other circuit configurations may be used as long as each output transistor can be switched as described above. I'll keep it.

Now, the generation and propagation of noise in such a buffer will be explained. Figure 7 (,) shows the I used for the buffer.
This is a partial circuit diagram of C. In the figure, SB1 to SBN are output sofas that switch simultaneously, and MB is a monitor buffer that should output a constant level during this period. The internal configuration of each buffer is shown in FIG. 6, and the terminal symbols correspond to each other. Also, with the potential supply line and L inside the IC, ■oo1. voc2. GND1. G
ND2, and VCCI is the first internal power supply voltage line, vC
C2 is a second internal power supply voltage line, GNDl is a first internal ground line, and GND2 is a second internal ground line.

Also, ■4. v2. P1-PN, PM, G4. G2 is I
Cf y Pounding pad on top, 01~O
N and OM are external output terminals external to the IC, and v
co is an external power supply voltage, and GND is an external ground voltage. Further, L1 to LN are parasitic inductances at the output terminal of the output buffer to be switched, LM is the parasitic inductance at the output terminal of the monitor buffer MB, Lvo is the Lv□ between the first internal power supply voltage terminal vCCOP and the external terminal vcco. is the second internal power supply voltage terminal V. C0P2 and external terminal vcc
Between 02 and 02, Lool is the first internal ground terminal GNDoP
1 and the external terminal GNDo, , Lo2 is the respective parasitic inductance between the second internal grounding terminal GN'Do, 2 and the external terminal GND82, and C1 to CN and C
M is the load capacitance of each external output terminal.

As shown in the figure, each potential supply terminal (7th
vcc4 in the figure. vCc2. GNDl and GND2) are each independently connected to each potential supply line at the chip level. Also, although not specifically stated,
It is assumed that the power supply voltage and ground for each control point in FIG. 7(,) are supplied from a potential supply line dedicated to input or a potential supply line 9 dedicated to the internal logic circuit.

FIG. 7(b) shows each output terminal P1 to PN and each G when the output terminals 01 to ON of a plurality of buffers SB1 to SBN simultaneously go from H to L level in the circuit of FIG. 7(,).
These are the voltage waveforms of the ND potential supply lines GND, , GND2 and the external output terminal OMX of the monitor buffer MB whose output should be constant at the L level at this time.

Now, in the present invention, both the on-resistances R11 and RNl of the first PMO8 output transistor and the first NMO8 output transistor in each output buffer are set to be sufficiently large, that is, the self-inductance L parasitic to the output buffer and the load capacitance are At least RP1≧2f for C
War, R8, ≧2 mechanics π-.

FIG. 7(b) will be explained under these conditions. First, in each first NMO8 output transistor board 12L of each output buffer SB1 to SBN, the charge of each capacitor C1 to CN is
is discharged through the internal ground wire GND. As a result, as shown in the figure, a large noise peak V occurs on the internal grounding line GND1. Pl occurs and the first N of monitor buffer MB
It propagates to the output terminal OM through the MOS output transistor Q12 and generates a noise peak vMP1. Here, the first NMO 8 output transistor board 12 resistor RN1 in each of the aforementioned output buffers is RN, ≧21]
Since there are 7 teeth, V, 1<V as shown in the figure. 1.
It can be done. Next, SB1~ of the output buffer to be switched
A noise peak V is applied to the second NMO8 output in sBN from the output transistor board 22 to the internal ground line GND2. ,2
occurs. At this time, the output terminal 01 of each switch buffer
～Discharge starts when ON, and since the voltage is low, V
. , 2<■. , becomes 1. At this time, if the time from when the first output transistor is turned on until the second output transistor is turned on is lengthened, the noise peak V will be reached. , 2 can be made sufficiently small. The noise generated at this time propagates to the second NMO8 output transistor board 22 of MB, which is a monitor buffer, and its external output terminal oM, causing a noise peak vMP2. The second NMO3 output transistor resistance needs to be small in order to increase the overall driving ability, vMP2 > vGP
2, but the noise peak V of the internal grounding wire. , 2 themselves can be made small, so the output noise peak vMP2 can also be made sufficiently small as shown in the figure. in this way.

According to the present invention, it is possible to reduce the noise generated at the output terminal even in an output buffer having a large current drive capability.

A comparison of specific nozzle voltages with conventional ones is shown below.

Figure 8(a) shows the current standard value of the output current for each switch. The sum of L I. LxN and internal ground wire GND1 and GND
2 shows the simulation results of the relationship with the noise peak voltage that occurs. Here, the current standard value I. L (hereinafter abbreviated as L) is a value often used in catalogs and the like, and is the reciprocal of the on-resistance in each output buffer. Now, the first
NMO 8 output to output transistor 12, 6 mA
and L, the voltage vcL of each load capacitance at the start of discharge is 5V, and I of the second NMOS output transistor Q22. When L is 12 mA and L is 2.5 mA, the voltage vcL of each load capacitance when this second NMO3 output is connected to the output transistor V22 is 2.5.
It should be about v. In this case, the switch buffer is 8 at the same time.
Each internal grounding wire GND1. As shown in the figure, the noise peak voltage generated at GND2 is V
. pl = IV, vcp2 '' becomes about 0.7 V, and ``GPi >vGP2''.

Also, the eighth figure) is the current standard value I of the monitor buffer that does not switch during this period. L and output terminal 0M of the output buffer
This is an example showing the relationship with the noise peak voltage that occurs above. As mentioned above, the first noise peak voltage that occurs is the noise peak ■ that occurs on the internal ground line GND1. P1=1v
, and propagates through the first output transistor Q12, which has a large on-resistance, so I. L=6
The point P of mA and its size are vMPl = 0.8
It will be about V. Also, the noise peak voltage that occurs next is on the curve of vcp2 = 0.7 V and is transmitted through the second output transistor Q22. The point Q is at L=12 mA, and its magnitude is approximately vMP2 = 0.8 V. In other words, vMP2 > ”GP2, but v
Since oP2 can be made smaller, vMP2 can also be made smaller. In addition, at this time, the current standard value I for one buffer. L is the sum of the two output transistors and becomes 18 mA.

Here, a case will be described in which the output transistor is divided into two parts, and the ground line is made common to each output buffer, in order to reduce the noise generated in the internal ground line.

In this case, the first noise peak that occurs at the output terminal ON is point P' in the figure, and its magnitude is ■MP1'-13V
On the other hand, the next noise peak will be point Q' in the figure, and its magnitude will be VMP2' = 0.9 V. Therefore, in the output buffer having the same current standard value, the noise peak voltage generated at the output terminal can be reduced to about 60% of the conventional one in this embodiment.

In this embodiment, by dividing the output transistor into a plurality of parts, the noise generated in the first ground line can be made smaller than in the case where the output transistor is not divided. Therefore, it is effective to increase the on-resistance R of the first output transistor, but it is not always necessary to satisfy the above equation RM≧217. That is, the on-resistance of at least the first output transistor is made larger than the on-resistance of the second output transistor, and the ground potential and power supply voltage potential are supplied to each output transistor by independent internal supply lines within the IC chip. In this case, noise can be made smaller than in the case where a potential is supplied to each output transistor through a single potential supply line, which has a corresponding effect.

Note that a member of the authors' group has reported that multiple same-potential supply lines are provided for the output transistors of each output buffer, but the purpose of this is to connect the source of each output transistor to the first potential supply line. and a second potential supply line, so that one side is used as a current path for charging and discharging the load, and the other is used as a potential supply path for maintaining the load level at a constant level. It was for controlling the above-mentioned switch means.

In this embodiment, there is no particular need for a circuit for controlling the above-mentioned switch means, and since the output transistor and the switch means do not need to be connected in series, there is an advantage that the gain of the output transistor is not impaired by the above-mentioned switch means. have.

Furthermore, the present invention can be modified in various ways within the scope of its spirit, such as replacing the second output transistor itself with a group of a plurality of output transistors connected in parallel,
It goes without saying that modifications may be made, such as controlling these output transistor groups to be turned on sequentially.

(Effects of the Invention) As described above, in the present invention, when a plurality of output buffers are switched simultaneously, the on-resistance of the output transistor of the output buffer which is to maintain the output at a constant level during this period is increased. The noise generated at the output terminal can be made smaller than the noise generated at the potential supply line inside the IC.

Further, in the present invention, the output of each output buffer is driven by a plurality of MO8 output transistors, and a potential is supplied to each source of the output transistor by an independent potential supply line within the IC chip. It is possible to increase the current driving capacity of the output sofa that maintains the output at a constant level, while reducing the noise generated at the output terminal.

Therefore, it is possible to obtain a semiconductor integrated circuit having a high-speed, large-current drive output buffer without fear of malfunction.

In addition, although ground noise was explained in each example,
Needless to say, the same applies to the power supply voltage terminal ■cc.

[Brief explanation of drawings]

FIG. 1 is a model diagram for explaining the first embodiment of the semiconductor integrated circuit of the present invention, FIGS. 2(a) and (b) are model diagrams of the output section of a conventional semiconductor integrated circuit, and FIG. is a model diagram of noise generation, Figure 4 (a)? (b) l (e) is a simulation waveform diagram of the noise waveform, FIG. 5 is a graph showing the simulation results showing the relationship between the on-resistance of the output transistor and the noise peak, and FIG. 6 is the second diagram of the present invention.
A circuit diagram of a buffer in a semiconductor integrated circuit according to an embodiment of
7(a) is a model diagram of the output section of the semiconductor integrated circuit according to the second embodiment of the present invention; FIG. 7(a) is a simulation waveform diagram of noise occurring in the output of FIG. The figure is a graph showing simulation results showing the relationship between current value and noise peak voltage. ■, ~IK...input buffer, SB2~SBN...
Output buffer, MB1 to MB, ... Output buffer, V
ccm...Power supply voltage terminal for input buffer, ■cco...
...Power supply voltage terminal for output buffer, GNDl...ground terminal for input buffer, GNDo...ground terminal for output buffer, os1-osN...output terminal, OM1-OM
J...Output terminal, c81~csN...Load capacitance, C
M1~CMJ...Load capacity.

Claims (3)

[Claims] (1) It has a first output buffer group and an output transistor that is supplied with power from the same power supply voltage terminal and ground terminal as the output transistor group of the first output buffer group, and the on-resistance of the output transistor is R_1. In a semiconductor integrated circuit having a parasitic self-inductance L at the output terminal of the output transistor, and a second buffer that is to maintain a constant logic level when the logic of the first output buffer group changes,
When a load with load capacity C is provided to the output terminal, R_1≧
A semiconductor integrated circuit characterized in that the values of on-resistance R_1, parasitic inductance L, and load capacitance C are determined so as to satisfy the conditions of ▲There are mathematical formulas, chemical formulas, tables, etc.▼. (2) In a semiconductor integrated circuit having a first output buffer group and a second output buffer that is to maintain a constant logic level when the logic of the first output buffer group changes, the first output buffer group respectively, a first output transistor that is powered by a first power terminal and a ground terminal, and a second output transistor that is powered by a second power terminal and a second ground terminal, and the first output transistor is operated. Later, it outputs the same logic as the first output transistor, and
a second output transistor having an output terminal connected to the output terminal of the first output transistor, and the second output buffer is supplied with power from the first power supply terminal and the ground terminal. Power is supplied to the third output transistor, the second power supply terminal and the second ground terminal, and after the third output transistor operates, it outputs the same logic as the third output transistor, and the third output transistor outputs the same logic as the third output transistor; a fourth output transistor having an output terminal connected to the output terminal of the third output transistor, and the on-resistance R_2 of the third output transistor is higher than the on-resistance R_3 of the fourth output transistor. A semiconductor integrated circuit characterized by having a high on-resistance. (3) In the semiconductor integrated circuit according to claim 2, when the parasitic self-inductance at the output terminal of the second output buffer is L and the output terminal is provided with a load capacitance C,
On-resistance R_2, parasitic inductance L,
A semiconductor integrated circuit characterized in that a load capacitance C has a predetermined value.