CN204216031U - Semiconductor package body - Google Patents
Semiconductor package body Download PDFInfo
- Publication number
- CN204216031U CN204216031U CN201420677325.9U CN201420677325U CN204216031U CN 204216031 U CN204216031 U CN 204216031U CN 201420677325 U CN201420677325 U CN 201420677325U CN 204216031 U CN204216031 U CN 204216031U
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- CN
- China
- Prior art keywords
- wafer
- pad
- array
- semiconductor package
- package body
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn - After Issue
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- Wire Bonding (AREA)
Abstract
The utility model relates to semiconductor package body.A kind of semiconductor package body comprises: wafer, and one first type surface is provided with pad arrays; The wire array of centreless bar, its first first type surface is connected by gold goal and solder with described pad arrays by the mode of flip-chip packaged, second first type surface contrary with described first first type surface is provided with the array of the fan-out pad corresponding with the weld pad in described pad arrays; Packing colloid, its coated described wafer and wire array also expose the array of described fan-out pad; Wherein, the size of the array of described fan-out pad and solder pad space length than the pad arrays size of described wafer and bonding pads separation larger.This semiconductor package body can have the outward appearance same with the packaging body that traditional WLCSP technology obtains, be rendered as without pin package, and the area of the actual wafer used is much smaller, thus take full advantage of the technological ability of existing IC wafer, the wafer output quantity of a wafer is greatly increased.
Description
Technical field
The utility model relates generally to semiconductor wafer package technology.
Background technology
Wafer chip level chip-scale package (Wafer Level Chip Scale Packaging, WLCSP), i.e. wafer stage chip packaged type, be different from traditional chip package mode (first to cut and seal survey again, and after encapsulation, at least increase the area of plane of former wafer 20%), this kind of state-of-the-art technology first on full wafer wafer, carries out most of packaging technology, integrated circuit (the Integrated Circuit of final formation, IC) particle, the area of plane therefore after encapsulation is a bit larger tham the life size of wafer.
But traditional wafer chip level Chip scale packaging needs, via some layer conductor layers, the connection gasket of wafer is fanned out to packaging body surface, and conductor layer occupies most of volume in packaging body and cost is high.
Utility model content
Existing semiconductor packaging is still further improved.
In an embodiment of the present utility model, disclose a kind of semiconductor package body, this semiconductor package body comprises: wafer, and one first type surface is provided with pad arrays; The wire array of centreless bar, its first first type surface is connected by gold goal and solder with described pad arrays by the mode of flip-chip packaged, second first type surface contrary with described first first type surface is provided with the array of the fan-out pad corresponding with the weld pad in described pad arrays; Packing colloid, its coated described wafer and wire array also expose the array of described fan-out pad; Wherein, the size of the array of described fan-out pad and solder pad space length than the pad arrays size of described wafer and bonding pads separation larger.
In a specific embodiment of above-mentioned semiconductor package body, described wire array comprises multiple lead unit, and described multiple lead unit presents by the arrangement of center to surrounding divergent shape.
In a specific embodiment of above-mentioned semiconductor package body, described wire array comprises at least one lead unit be connected with multiple weld pads of described wafer.
In a specific embodiment of above-mentioned semiconductor package body, at least one center weld pad of at least one lead unit described and described wafer and the edge weld pad that at least one is adjacent thereof are connected.
In a specific embodiment of above-mentioned semiconductor package body, described gold goal has a spherical part and a neck.More specifically, the neck of at least coated described gold goal of described solder.
In another embodiment of the present utility model, disclose a kind of method for packaging semiconductor, the method comprises: provide wafer, and a first type surface of described wafer is provided with pad arrays; Pad arrays for described wafer plants the gold goal for welding; Lead frame is provided, its each grid comprises the wire array of a centreless bar, described wire array comprises the first first type surface and second first type surface contrary with the first first type surface, described second first type surface is provided with the array of the fan-out pad corresponding with the weld pad in described pad arrays, the size of the array of described fan-out pad and solder pad space length than the pad arrays size of described wafer and bonding pads separation larger; The solder bump that printing is corresponding with described gold goal on described first first type surface of described wire array; Described flip-chip is welded in described wire array; Encapsulating encapsulates described wafer and wire array, and exposes the array of described fan-out pad; Cut list.
In a specific embodiment of said method, before the step described flip-chip being welded in described wire array, also comprise the step of wafer described in wear down.
In a specific embodiment of said method, described cut single stage before also comprise for described fan-out pad plants gold goal for welding.
In a specific embodiment of said method, described wire array comprises multiple lead unit, and described multiple lead unit presents by the arrangement of center to surrounding divergent shape.
In a specific embodiment of said method, described wire array comprises at least one lead unit be connected with multiple weld pads of described wafer.
In a specific embodiment of said method, at least one center weld pad of at least one lead unit described and described wafer and the edge weld pad that at least one is adjacent thereof are connected.
Adopt the technical scheme in the utility model, the semiconductor package body obtained can have the outward appearance same with the packaging body that traditional WLCSP technology obtains, be rendered as without pin package, and the area of the actual wafer used is much smaller, thus take full advantage of the technological ability of existing IC wafer, the wafer output quantity of a wafer is greatly increased.In addition, owing to avoiding the yields loss of wafer scale fan-out in traditional WLCSP technology, overall package yields is improved further.And encapsulation volume is much smaller compared with there being the encapsulation of pin.
Accompanying drawing explanation
By reference to the accompanying drawings, will be easier to understand about the detailed description of preferred embodiment of the present utility model below.The utility model is explained by way of example, is not limited to accompanying drawing, and Reference numeral similar in accompanying drawing indicates similar element.
Fig. 1 is the schematic appearance of wafer 10;
The schematic diagram of the wafer 100 after Fig. 2 is through and plants ball;
Fig. 3 shows the partial cutaway schematic of the wafer 100 after encapsulation;
Fig. 4 show with wafer 100 with the use of wire array 200;
Fig. 5 shows the schematic diagram combined by flip chip process by wire array 200 shown in wafer 100 shown in Fig. 2 and Fig. 3;
Fig. 6 shows the floor map of a kind of wire array 600 corresponding with the pad array of 4 × 4 scales;
Fig. 7 shows the flow chart of a kind of wafer package method 700 in the utility model;
Fig. 8 shows one and cuts the packaging body 800 singly.
Embodiment
The detailed description of accompanying drawing is intended to the explanation as currently preferred embodiment of the present utility model, and is not intended to represent that the utility model can be achieved only has form.It should be understood that identical or equivalent function can complete by being intended to the different embodiments be contained within spirit and scope of the present utility model.
Fig. 1 is the schematic appearance of wafer 10.Wafer 10 shown in figure has the cell array that several rectangular wafers 100 are formed.For simplicity's sake, in figure and the weld pad of not shown cell array (or claim connection gasket).Weld pad on a first type surface of wherein each wafer 100 can be arranged into array, such as but not limited to the pad arrays of the scales such as 3 × 3,4 × 4,2 × 3,3 × 4.
By planting ball technique to whole wafer, can be the Metal Ball of pad arrays attachment for being welded to connect of cell array.For clearly illustrating the utility model, Fig. 2 illustrate only the schematic diagram of a wherein wafer 100 of the wafer after planting ball.Pad arrays on a first type surface of wafer 100 shown in figure is 3 × 3 scales, also show Metal Ball in the pad array being attached to wafer 100 after planting ball operation 121 to 129 (from the Metal Ball in corner in the counterclockwise direction by outer ring to inner ring, by 121 to 129 order labels) in figure.
In the present embodiment, ball is planted on wafer, such as but not limited to, adopt the technique of traditional wire soldering technology, on the weld pad of wafer, sharp bonding wire (gold thread, copper cash or other metal wires) ultrasonic waves technology forms Metal Ball (gold goal, copper ball or other Metal Ball) on weld pad.In the wire soldering method of prior art, bonding wire can be connected on the supporting body of carries chips.And in the present embodiment, bonding wire will be truncated after formation Metal Ball.Therefore the Metal Ball in the present embodiment is not the spherical of regular circle shapes, but the solder ball shape formed on the solder joint of chip with traditional wire soldering technology is similar.Fig. 3 shows the partial cutaway schematic of the wafer 100 after encapsulation.As shown in Figure 3, the surface of wafer 100 has weld pad 140, weld pad 140 is attached with Metal Ball 120.This Metal Ball 120 has a spherical part and a neck, and this neck has a structure of inwardly shrinking relative to spherical part.Welding material (such as scolding tin) 151 is for jointing metal ball 120 and attaching surface 153 (such as lead frame etc.), and the neck of clad metal ball 120 and spherical part are at least partially.Encapsulating material 155 is filled between wafer 100 and attaching surface 153, and coated metal ball 120 and welding material 151.
Fig. 4 show with wafer 100 with the use of wire array 200 (also can be called pin array).Before wafer welding, sealing, cutting, wire array 200 is still a part for lead frame.Lead frame also comprises grid type frame (not shown), and each wire array 200 is positioned at one of them grid and links together with frame.In order to clearly describe the utility model, this enforcement, only for one of them wire array 200 of lead frame, it will be understood by those skilled in the art that sealing, before cutting, encapsulation process is still carried out in units of lead frame in welding.As shown in the figure, wire array 200 comprises eight independently lead units 211 to 218 (also can be pin units), and this wire array does not comprise chip carrier.The solder bump 221 to 229 corresponding with the Metal Ball 121 to 129 on wafer 100 is printed with on the surface in the side of wire array 200, therefore, solder bump above wire array 200 is all arranged in the magnitude range of wafer 100, and namely solder bump region size is less than or equal to the size of wafer 100.Be provided with pad array on the surface at the opposite side of wire array 200, comprise pad 231 to 239 (because of angular relationship, the local of pad 231,237,238,239 being only shown in figure).Lead unit 211 to 218 presents substantially by the arrangement of center to surrounding divergent shape.Lead unit 211 to 217 respectively has a solder bump and a fan-out pad.Lead unit 218 has two solder bumps and two fan-out pads, comprises the solder bump 228 of the solder bump 229 of the center weld pad of connecting wafer 100 and an edge weld pad of connecting wafer 100 and corresponding two fan-out pads 238 and 239.Correspondingly, the weld pad adhered to respectively by Metal Ball 128 and 129 of wafer 100 has identical circuit node and defines, such as, be all ground connection.The pad array of wire array 200 is compared with the pad arrays of wafer 100, and size and spacing are all comparatively large, are beneficial to the signal fan-out of wafer 100.Fig. 5 shows the schematic diagram combined by flip chip (flipchip) technique by wire array 200 shown in wafer 100 shown in Fig. 2 and Fig. 4, in the present embodiment, solder bump is tin cream or the metal alloy containing tin, after wafer 100 and wire array 200 combine, in follow-up reflow soldering process, solder bump is after heating, can melt and the Metal Ball corresponding with solder bump part or all of on coating wafer 100, in the present embodiment, the bottom of the whole and spheroid of the neck of this Metal Ball at least coated after fuse.
The chip bonding pads array of different scales all has corresponding wire array, and these wire array present usually all substantially by the arrangement of center to surrounding divergent shape.Fig. 6 shows the floor map of a kind of wire array 600 corresponding with the pad arrays of 4 × 4 scales.This wire array 600 comprises 12 lead units 610, and the shown side of wire array 600 is printed with and 16 solder bumps 620 one to one of 4 × 4 scale pad arrays on wafer on the surface.Wire array 600 that side surface unshowned is provided with 16 fan-out pads.In array, four lead units are printed with two solder bumps and two fan-out pads respectively, comprise a solder bump of a solder bump of a center weld pad of connecting wafer and an edge weld pad of connecting wafer and corresponding two fan-out pads.
The wire array corresponding with the chip bonding pads array of small-scale can comprise the lead unit identical with number of pads, and each lead unit corresponds to a chip bonding pads, thus ensures abundant pinout.Such as, the wire array corresponding with the chip bonding pads of 2 × 3 scales can comprise 6 lead units, and each lead unit corresponds to a chip bonding pads.
Such as, and for fairly large chip bonding pads array, the pad design being positioned at center can be have identical circuit node with adjacent edge pad to define by the chip bonding pads array of 4 × 4 or 5 × 5 scales.Then correspondingly, the part lead unit in wire array can connect multiple chip bonding pads with identical definition.
Fig. 6 shows the flow chart of a kind of wafer package method 700 in the utility model.Step 705 is for planting ball operation, and this technique completes in a wafer, see the schematic diagram being the wafer 100 of planting after ball operation shown in Fig. 1 and Fig. 2, Fig. 2.Step 710 is wear down operation, and by wafer wear down to reduce volume, to remove the parts such as unnecessary useless substrate, this operation is optional.Step 715 is cutting action, is cut into independently wafer by wafer.Step 720 is solder printing operation, namely with wafer with the use of wire array on print and the corresponding solder bump in chip bonding pads position.Step 725 sticks operation for flip chip, and step 730 is Reflow Soldering operation, in these two steps by with the use of wafer and wire array be welded into one; These two steps also can adopt other suitable joint technologies to substitute.Step 735 is cleaning scaling powder operation, under exempting from the situations such as cleaning scaling powder, can omit this operation in employing.Step 740 is encapsulating packaging process.In encapsulating packaging process, the sub-step of the fan-out pad array adhering protective film for wire array can be comprised, after encapsulating, remove diaphragm again to expose fan-out pad array.Step 745, for planting ball operation, is the tin ball of fan-out pad array attachment for welding.Step 750, for cutting list (Singulation) operation, opens the connection of single packaging body and lead frame in this process interruption.In certain embodiments, plant ball operation 745 also can reverse with the order of cutting single operation 750.
In some other embodiments; step 745 also can be omitted or replace by other technology generations, such as, does not plant tin ball above the pad of wire array; but directly use as end terminal, also can be protected with the anti-oxidation coat of metal or organic protective film on pad.Or tin metal is beneficial to follow-up upper plate technique on pad.
Fig. 8 shows one and cuts the packaging body 800 singly.This packaging body 800 comprises wafer 100 (entity should be invisible), wire array 200 and packing colloid 300.Packing colloid 300 is depicted as dashed lined box, the tin ball 330 being included in the pad array that a first type surface (as the second first type surface) exposes in the surperficial visible part of packing colloid 300 and the cross section of cut-out lead unit exposed in surrounding side.The packaging body 700 so obtained can have the outward appearance same with the packaging body that traditional WLCSP technology obtains, be rendered as without pin package, and plant gold goal by the mode of directly planting ball on the weld pad of wafer above, and be connected directly between on the wire array of centreless bar by the mode of flip-chip packaged, thus take full advantage of the technological ability of existing IC wafer, the wafer output quantity of a wafer is greatly increased.In addition, owing to avoiding the yields loss of wafer scale fan-out in traditional WLCSP technology, overall package yields is improved further.And encapsulation volume is much smaller compared with there being the encapsulation of pin.
Although illustrated and described different embodiment of the present utility model, the utility model has been not limited to these embodiments.The technical characteristic only occurred in some claim or embodiment does not also mean that and can not combine with other features in other claims or embodiment to realize useful new technical scheme.When not deviating from the spirit and scope of the present utility model described by claims, many amendments, change, distortion, substitute and equivalent be obvious to those skilled in the art.
Claims (6)
1. a semiconductor package body, is characterized in that, this semiconductor package body comprises:
Wafer, one first type surface is provided with pad arrays;
The wire array of centreless bar, its first first type surface is connected by gold goal and solder with described pad arrays by the mode of flip-chip packaged, second first type surface contrary with described first first type surface is provided with the array of the fan-out pad corresponding with the weld pad in described pad arrays;
Packing colloid, its coated described wafer and wire array also expose the array of described fan-out pad;
Wherein, the size of the array of described fan-out pad and solder pad space length than the pad arrays size of described wafer and bonding pads separation larger.
2. semiconductor package body as claimed in claim 1, it is characterized in that, described wire array comprises multiple lead unit, and described multiple lead unit presents by the arrangement of center to surrounding divergent shape.
3. semiconductor package body as claimed in claim 2, it is characterized in that, described wire array comprises at least one lead unit be connected with multiple weld pads of described wafer.
4. semiconductor package body as claimed in claim 3, is characterized in that, at least one center weld pad of at least one lead unit described and described wafer and the edge weld pad that at least one is adjacent thereof are connected.
5. semiconductor package body as claimed in claim 1, it is characterized in that, described gold goal has a spherical part and a neck.
6. semiconductor package body as claimed in claim 5, is characterized in that, the neck of the coated described gold goal of described solder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420677325.9U CN204216031U (en) | 2014-11-13 | 2014-11-13 | Semiconductor package body |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420677325.9U CN204216031U (en) | 2014-11-13 | 2014-11-13 | Semiconductor package body |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204216031U true CN204216031U (en) | 2015-03-18 |
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ID=52984680
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420677325.9U Withdrawn - After Issue CN204216031U (en) | 2014-11-13 | 2014-11-13 | Semiconductor package body |
Country Status (1)
| Country | Link |
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| CN (1) | CN204216031U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465593A (en) * | 2014-11-13 | 2015-03-25 | 苏州日月新半导体有限公司 | Semiconductor package and packaging method |
| CN113517240A (en) * | 2021-05-21 | 2021-10-19 | 华天科技（昆山）电子有限公司 | Wafer fan-out type inverted packaging structure and manufacturing method thereof |
-
2014
- 2014-11-13 CN CN201420677325.9U patent/CN204216031U/en not_active Withdrawn - After Issue
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465593A (en) * | 2014-11-13 | 2015-03-25 | 苏州日月新半导体有限公司 | Semiconductor package and packaging method |
| CN104465593B (en) * | 2014-11-13 | 2018-10-19 | 苏州日月新半导体有限公司 | Semiconductor package and packaging method |
| CN113517240A (en) * | 2021-05-21 | 2021-10-19 | 华天科技（昆山）电子有限公司 | Wafer fan-out type inverted packaging structure and manufacturing method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20150318 Effective date of abandoning: 20181019 |