CN107564825B - A kind of chip double-side encapsulating structure and its manufacturing method - Google Patents
A kind of chip double-side encapsulating structure and its manufacturing method Download PDFInfo
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- CN107564825B CN107564825B CN201710755489.7A CN201710755489A CN107564825B CN 107564825 B CN107564825 B CN 107564825B CN 201710755489 A CN201710755489 A CN 201710755489A CN 107564825 B CN107564825 B CN 107564825B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
The present invention relates to a kind of chip double-side encapsulating structure and its manufacturing methods.Encapsulating structure includes：Memory chip storehouse body is disposed on the substrate, and first, which reroutes layer, forms on memory chip storehouse body；Cache chip is arranged on the surface of the substrate；Terminal is set on substrate；First plastic-sealed body sealed storage device chip stack body；Second plastic-sealed body seals at cache chip and terminal and substrate connection.Manufacturing method includes：Memory chip storehouse body is disposed on the substrate；Form the first plastic-sealed body sealed storage device chip stack body；Cache chip is disposed on the substrate；Form the second plastic-sealed body sealing cache chip；Thinning is carried out to cache chip and the second plastic-sealed body；It drills to the second plastic-sealed body, the terminal that implantation is connect with metal gasket in the borehole is simultaneously welded and fixed.The chip stack stereo encapsulation structure overall structure size of the present invention is small, and signal transmission distance is short, and can be needed to performance flexible configuration according to using.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of chip double-side encapsulating structure and its manufacturing method.
Background technology
In existing multichip packaging structure, each chip is packaged in the side of substrate, as shown in Figure 1, existing
Multi-chip stack packaging structure includes substrate 200, and a side surface of substrate 200 is provided with cache chip 201, cache chip
201 are electrically connected by rerouting layer 202 with substrate 200, and the surface storehouse of cache chip 201 is provided with memory chip
203, it is formed with plastic-sealed body 204 in the side surface of substrate 200, to seal cache chip 201 and memory chip 203, to
Form single side molding kenel.Another side surface of substrate 200 is provided with ball grid array terminals 205, ball grid array terminals 205 are logical
It crosses substrate 200 and is electrically connected cache chip 201 and memory chip 203, ball grid array terminals 205 are by being located in substrate 200
Conducting wire 206 and memory chip 203,201 electrical communication of cache chip.Due to 201 heap of memory chip 203 and cache chip
Stack causes the thickness of encapsulating structure to become larger in 200 the same side of substrate.The encapsulating structure manufactured through the above way simultaneously needs
Complete package is disposably realized in process of production, therefore not only causes the production cycle long, but also chip functions configuration
Flexibility is poor, and the model and type that adjust each chip in real time can not be needed according to user, and it is impossible to meet the need that personalization is ordered
It asks.
Disclosed above- mentioned information is only used for reinforcing the understanding of the background to the present invention in the background technology, therefore it may be wrapped
Containing the information for not being formed as the prior art that those of ordinary skill in the art are known.
Invention content
In view of this, the embodiment of the present application is desirable to provide a kind of chip double-side encapsulating structure and its manufacturing method, at least
Solve problems of the prior art.
The technical solution of the embodiment of the present application is achieved in that one embodiment according to the application, provides a kind of core
Piece double-faced packaging structure, including：
Substrate has the first surface and second surface being oppositely arranged；
Memory chip storehouse body, chip bonding mode is arranged on the first surface of the substrate, mainly by more
A storage chip storehouse composition, the memory chip storehouse body have an installation surface；
First reroutes layer, is formed in the installation surface of the memory chip storehouse body, is electrically connected each institute
Storage chip is stated to the substrate；
The middle section in the second surface of the substrate is arranged in cache chip, chip bonding mode；
Terminal is set on the second surface of the substrate；And
First plastic-sealed body and the second plastic-sealed body；First plastic-sealed body is formed on the first surface of the substrate,
Seal the memory chip storehouse body；Second plastic-sealed body is formed on the second surface of the substrate, seals institute
Cache chip and the terminal are stated at the link position of the second surface of the substrate, constitutes two-sided molding kenel.
In some embodiments, the substrate includes electrically running through the conducting circuit of the substrate and in the second surface
On fan-out circuit, the conducting circuit is electrically connected the cache chip and the terminal and reroutes layer, institute to described first
It states fan-out circuit and is electrically connected the cache chip to the terminal.
In some embodiments, on each storage chip include multiple conductive through holes for electrical communication,
Described first, which reroutes layer, is electrically connected each conductive through holes to the substrate.
In some embodiments, each storage chip is by being arranged the first convex block phase in each conductive through holes end
Mutually it is electrically connected.
In some embodiments, further include the first primer, be formed in the memory chip storehouse body and the substrate
Between the first surface.
In some embodiments, the terminal includes the multiple soldered balls being arranged in cache chip periphery.
In some embodiments, the substrate forms metal gasket on the second surface, makes the soldered ball and the base
The engagement of plate is more firm.
In some embodiments, the thickness of the cache chip is less than the Diameter of Solder Ball of the terminal.
In some embodiments, further include the second primer, be formed in a side surface of the cache chip and the substrate
The second surface between.
In some embodiments, so substrate is the silicon that there is the second surface single side to reroute layer and silicon perforation structure
Intermediate plate.
A kind of manufacturing method of chip double-side encapsulating structure, including：
There is provided has the substrate of the first surface and second surface that are oppositely arranged；
The memory chip storehouse body being made of multiple storage chip storehouses is provided, in the memory chip storehouse body
Installation surface forms first and reroutes layer, and multiple conductive through holes for electrical communication are formed on each storage chip,
The first rewiring layer is electrically connected each conductive through holes of each memory chip to the substrate；
The memory chip storehouse body is arranged by chip bonding mode in the substrate for first time chip bonding
On the first surface；
First time molding processing procedure forms the first plastic-sealed body on the first surface of the substrate, seals the storage
Device chip stack body；
Second of chip bonding provides cache chip and it is arranged by chip bonding mode described in the substrate
On second surface middle section, and multiple metal gaskets are formed on the second surface；
Second of molding processing procedure forms the second plastic-sealed body on the second surface of the substrate, seals the caching
Chip；
Thinning is handled, and carries out thinning to the cache chip and second plastic-sealed body by lapping mode, and ensure institute
The cache chip after sealing thinning is remained to after stating the second plastic-sealed body thinning；
It drills at the position corresponding with each metal gasket of second plastic-sealed body surface, until exposing institute
State each metal gasket on second surface；
It is implanted into the terminal being connect with the metal gasket in the drilling and is welded and fixed.
In some embodiments, first time dispensing is carried out before the first time molding processing procedure, in the memory chip
The first primer is formed between storehouse body and the first surface of the substrate；
Second of dispensing is carried out before second of molding processing procedure, in a side surface of the cache chip and the base
The second primer is formed between the second surface of plate.
In some embodiments, the terminal includes the multiple soldered balls being arranged in cache chip periphery.
In some embodiments, the thickness of the cache chip after thinning is less than the Diameter of Solder Ball.
In some embodiments, the memory chip storehouse body is directly by multiple individually storage chip storehouse groups
At, or by being cut again after multiple uncut wafer storehouses being made of several storage chips it is independent the memory
Chip stack body.
The present invention due to using the technology described above, has the following advantages：1, cache chip of the invention is due to setting
In the second surface of substrate, therefore when being packaged to the present apparatus, can first to the memory chip storehouse body of substrate side into
Row encapsulation, and cache chip can be according to need of work and the demand of chip performance, in the installation for subsequently carrying out cache chip
And encapsulation, it is not necessary to whole encapsulation process are completed primary, to improve the flexibility of encapsulating structure of the invention, according to different need
It asks and is flexibly configured and encapsulated at any time, not only reduce the manufacturing cycle while also reducing production cost.2, the present invention by
The subregion of entire cache chip and terminal is sealed by the second plastic-sealed body in the second surface in substrate, therefore
Can play a protective role to cache chip prevents chip fracture, and keeps terminal connection more firm, reduces and is manufacturing and filling
External impacts during fortune are damaged caused by chip.3, the present invention is due to first setting cache chip by chip bonding mode
Set the second surface in substrate, re-form the second plastic-sealed body in second surface and seal cache chip, finally again to sealing after
Cache chip carries out thinning processing, therefore since the second plastic-sealed body plays a protective role to the cladding of cache chip so that thin
The problems such as cache chip is not in rupture and chip thermal deformation when changing processing, while the second plastic-sealed body can balance thermal expansion system
Number reduces the state modulator to thermal deformation, improves the stability of technology controlling and process.4, the present invention is due to by cache chip and storage
Device chip stack body is separately positioned on opposite two surfaces of substrate, and memory chip storehouse body is encapsulated by plastic-sealed body, and
Be arranged cache chip is exposed in the middle part of the ball grid array of soldered ball, due to will originally together by plastic-sealed body be encapsulated in it is slow
It deposits chip layout and has arrived the soldered ball side being connect with outer member, therefore effectively reduce the size of the encapsulating structure of the present invention,
The distance for shortening signal transmission simultaneously, improves signal quality.5, the diameter of soldered ball of the invention is more than the thickness of cache chip
Degree, therefore support and protective effect can be played to exposed cache chip, it is to avoid when outer member connection slow
It is impaired to deposit chip.
Above-mentioned general introduction is merely to illustrate that the purpose of book, it is not intended to be limited in any way.Except foregoing description
Schematical aspect, except embodiment and feature, by reference to attached drawing and the following detailed description, the present invention is further
Aspect, embodiment and feature, which will be, to be readily apparent that.
Description of the drawings
In the accompanying drawings, unless specified otherwise herein, otherwise run through the identical reference numeral of multiple attached drawings and indicate same or analogous
Component or element.What these attached drawings were not necessarily to scale.It should be understood that these attached drawings are depicted only according to the present invention
Some disclosed embodiments, and should not serve to limit the scope of the present invention.
Fig. 1 is multi-chip stack packaging structure schematic diagram in the prior art；
Fig. 2 is the schematic diagram of the chip double-side encapsulating structure of the present invention；
Fig. 3 is the first of the present invention the part connection enlarged diagram for rerouting the first surface of layer and substrate；
Fig. 4 is the part connection enlarged diagram of the cache chip of the present invention and the second surface of substrate；
Fig. 5 is the manufacturing flow chart of the chip double-side encapsulating structure of the present invention；
Fig. 6 is installation and the molding schematic diagram of the memory chip storehouse body of the present invention；
Fig. 7 is installation and the molding schematic diagram of the cache chip of the present invention；
Fig. 8 is cache chip thinning processing and the drilling schematic diagram of the present invention；
Reference numeral：
1- substrates；11- first surfaces；12- second surfaces；
13- metal gaskets；The second connection gaskets of 14-；The 4th connection gaskets of 15-；
Circuit is connected in 16-；17- fan-out circuits；2- memory chip storehouse bodies；
21- storage chips；22- conductive through holes；The first convex blocks of 23-；
3- first reroutes layer；The first connection gaskets of 31-；The second convex blocks of 32-；
4- cache chips；41- third connection gaskets；42- third convex blocks；
5- terminals；The first primers of 6-；The first plastic-sealed bodies of 7-；
The second primers of 8-；The second plastic-sealed bodies of 9-；91- drills
200- substrates；201- cache chips；202- reroutes layer；
203- memory chips；204- plastic-sealed bodies；205- ball grid array terminals；
206- conducting wires.
Specific implementation mode
Hereinafter, certain exemplary embodiments are simply just described.As one skilled in the art will recognize that
Like that, without departing from the spirit or scope of the present invention, described embodiment can be changed by various different modes.
Therefore, attached drawing and description are considered essentially illustrative rather than restrictive.
In the description of the present invention, it is to be understood that, term "center", " longitudinal direction ", " transverse direction ", " length ", " width ",
" thickness ", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outside", " up time
The orientation or positional relationship of the instructions such as needle ", " counterclockwise ", " axial direction ", " radial direction ", " circumferential direction " be orientation based on ... shown in the drawings or
Position relationship is merely for convenience of description of the present invention and simplification of the description, and does not indicate or imply the indicated device or element must
There must be specific orientation, with specific azimuth configuration and operation, therefore be not considered as limiting the invention.
In addition, term " first ", " second " are used for description purposes only, it is not understood to indicate or imply relative importance
Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include one or more this feature.In the description of the present invention, the meaning of " plurality " is two or more,
Unless otherwise specifically defined.
In the present invention unless specifically defined or limited otherwise, term " installation ", " connected ", " connection ", " fixation " etc.
Term shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or integral；Can be that machinery connects
It connects, can also be electrical connection, can also be communication；It can be directly connected, can also indirectly connected through an intermediary, it can be with
It is the interaction relationship of the connection or two elements inside two elements.For the ordinary skill in the art, may be used
To understand the concrete meaning of above-mentioned term in the present invention as the case may be.
In the present invention unless specifically defined or limited otherwise, fisrt feature the "upper" of second feature or "lower"
It may include that the first and second features are in direct contact, can also not be to be in direct contact but pass through it including the first and second features
Between other characterisation contact.Moreover, fisrt feature second feature " on ", " side " and " above " include fisrt feature
Right over second feature and oblique upper, or it is merely representative of fisrt feature level height and is higher than second feature.Fisrt feature is
Two features " under ", " lower section " and " following " include fisrt feature right over second feature and oblique upper, or be merely representative of
One characteristic level height is less than second feature.
Following disclosure provides many different embodiments or example is used for realizing the different structure of the present invention.In order to
Simplify disclosure of the invention, hereinafter the component of specific examples and setting are described.Certainly, they are merely examples, and
And it is not intended to limit the present invention.In addition, the present invention can in different examples repeat reference numerals and/or reference letter,
This repetition is for purposes of simplicity and clarity, itself not indicate between discussed various embodiments and/or setting
Relationship.In addition, the present invention provides various specific techniques and material example, but those of ordinary skill in the art can be with
Recognize the application of other techniques and/or the use of other materials.
Specifically, a kind of chip double-side encapsulating structure is provided as shown in Fig. 2,3 and 4, in the present embodiment, including：
Substrate 1 has the first surface 11 being oppositely arranged and second surface 12；
Memory chip storehouse body 2, chip bonding mode are arranged on the first surface 11 of substrate 1, are mainly deposited by multiple
21 storehouse of chip composition is stored up, memory chip storehouse body 2 has an installation surface；Wherein, include on each storage chip 21
It is memory chip storehouse body 2 close to 11 side of first surface to have multiple conductive through holes 22 for electrical communication, installation surface
Surface, each storage chip 21 is combined into one and mutually electrically by the first convex block 23 for being arranged in 22 end of each conductive through holes
Connection；
Memory chip storehouse body 2 further includes the first rewiring layer 3, is formed in the installation table of memory chip storehouse body 2
On face, each conductive through holes 22 of each storage chip 21 are electrically connected to substrate 1；
Cache chip 4, chip bonding mode are arranged on the middle section of the second surface 12 of substrate 1；
Terminal 5 is set on the second surface 12 of substrate 1；And
First plastic-sealed body 7 and the second plastic-sealed body 9；
First plastic-sealed body 7, is formed on the first surface 11 of substrate 1, with sealed storage device chip stack body 2, and has
There is single side molding kenel, to not interfere the setting of cache chip 4.Make cache chip 4 that can be used according to need of work and chip
The demand of performance, in the installation for subsequently carrying out cache chip 4, it is not necessary to whole encapsulation process are completed primary, to improve this hair
The flexibility of bright encapsulating structure is flexibly configured and is encapsulated at any time according to different demands, not only reduces the manufacturing cycle
Also reduce production cost simultaneously；
Second plastic-sealed body 9, is formed on the second surface 12 of substrate 1, seals the of cache chip 4 and terminal 5 and substrate 1
At the link position on two surfaces 12, to constitute two-sided molding kenel, the second plastic-sealed body 9 can play cache chip 4 and terminal 5
To protective effect, cache chip 4 is avoided splintering problem occur, while improving the stable connection of terminal 5.
Wherein, conducting circuit 16 of the substrate 1 including electrically running through substrate 1 and the fan-out circuit 17 on second surface 12,
Circuit 16 is connected and is electrically connected the rewiring layer 3 of cache chip 4 to the first, fan-out circuit 17 is electrically connected cache chip 4 to terminal
5。
It should be noted that metallic conducting media is filled in conductive through holes 22, for connecting progress with the first convex block 23
It is conductive.Simultaneously as there are element silicons in most storage chips 21, therefore conductive through holes 22 are silicon perforation.
Further include being formed in memory chip storehouse body 2 and substrate in some embodiments to improve stable connection
The first primer 6 between 1 first surface 11；
It is installed for the ease of subsequent chip, terminal 5 includes the multiple soldered balls being arranged in 4 periphery of cache chip, and soldered ball is used
It is connect in external other elements.
In a preferred embodiment, welded ball array encapsulation (BGA, Ball Grid Array) can be used in each soldered ball
Mode plants on the second surface 12 of the substrate 1 outside cache chip 4；Specifically, the arrangement mode of welded ball array can be：Edge
The circumferential direction of cache chip 4 is spacedly distributed, or arranges at equal intervals multiple soldered balls along the opposite sides of cache chip 4.It needs to illustrate
, the arrangement mode of each soldered ball is not limited to above-mentioned mentioned content, and the arrangement of specific soldered ball can be according to work need
It wants and the size of substrate 1 and cache chip 4 is adaptively adjusted.
In some embodiments, in order to improve the connective stability of each storage chip 21, and ensure each storage chip
21 keep horizontal, can be distributed on conductive through holes 22 are equally spaced in storage chip 21, and run through storage chip 21.Preferably,
Multigroup conductive connection part can be arranged at intervals on storage chip 21, every group of conductive connection part is worn by multiple spaced conductions
Hole 22 forms.Wherein, the quantity of conductive through holes 22 can basis in the group number of the conductive connection part of setting and every group of conductive connection part
Need of work and chip size are adaptively adjusted, if being bonded between disclosure satisfy that each storage chip 21, and connect
21 horizontal interval of each storage chip is arranged after conjunction.
As shown in Fig. 2, in some embodiments, substrate 1 formed on second surface 11 metal gasket 13 (UBM pad,
Under Bump Metallurgy pad), keep the engagement of soldered ball and substrate 1 more firm.Metal gasket 13 can be used as aoxidizing
Play the role of protective substrate 1 in barrier layer.It should be noted that metal gasket 13 can be multiple, and the quantity phase of quantity and soldered ball
Together.
In a preferred embodiment, implanting is consistent in the height of each soldered ball on the second surface 12 of substrate 1,
So as to the stable connection when the chip stack stereo encapsulation structure of the present embodiment to be connect with outer member, when avoiding influencing to use
Signal transmission is unstable.
In order to reduce package dimension and signal transmission distance, although cache chip 4 and memory chip storehouse body 2 are distinguished
Opposite sides in substrate 1 is set, but since cache chip 4 is exposed in the outside of substrate 1, is installed with outer member
Shi Rongyi causes to damage to cache chip 4；Therefore, in a preferred embodiment, the thickness of cache chip 4 is less than terminal 5
Diameter of Solder Ball, when ensureing that chip stack stereo encapsulation structure is connect with outer member, soldered ball can play support protection make
With, so that cache chip 4 is located at the inside of external welded ball array, avoid cache chip 4 install or work in by ectocine, shadow
Ring performance.
As shown in figure 3, in some embodiments, the first primer 6 is also formed between each storage chip 21, to seal first
Convex block 23.
As shown in figure 3, in some embodiments, forming multiple first connections on a side surface of the first rewiring layer 3
Pad 31 forms multiple second connection gaskets 14 corresponding with the first connection gasket 31, each first connection on the first surface 11 of substrate 1
Pad 31 is connect with each second connection gasket 14 by the second convex block electrical 32 being formed on the first connection gasket 31.Wherein, each first
Connection gasket 31 is evenly distributed on the side surface that array reroutes layer 3 first, and the second connection gasket 14 is evenly distributed with array the first of substrate 1
On surface 11, to ensure the first connective stability for rerouting layer 3 and substrate 1.
As shown in figure 4, in some embodiments, multiple third connection gaskets 41 are formed on a side surface of cache chip 4,
Multiple the 4th connection gaskets 15 corresponding with third connection gasket 41, each third connection gasket 41 are formed on the second surface 12 of substrate 1
It is electrically connected by the third convex block 42 being formed on third connection gasket 41 with each 4th connection gasket 15.Wherein, each third connection
Pad 41 is evenly distributed with array on a side surface of cache chip 4, the 4th connection gasket 15 be evenly distributed with array substrate 1 second surface 12
On, to ensure the connective stability of cache chip 4 and substrate 1.
In some embodiments, after the engagement of each first connection gasket 31, each second connection gasket 14 and each second convex block 32, shape
Expire the first primer 6 at being filled in the gap between the side surface and the first surface 11 of substrate 1 for rerouting layer 3 in first, with
Seal the second convex block 32；First primer 6 more extends the outer rim for being diffused into memory chip storehouse body 2 close to 1 one end of substrate, with even
Connect the position between storage chip 21.That is the first primer 6 is covered in outer rim of the memory chip storehouse body 2 close to 1 one end of substrate
First, which reroutes layer 3 and first, reroutes the part substrate 1 of layer 3 outer rim circumferential direction, and then completes memory chip storehouse body 2
(FOWLP, Fan-Out Wafer-Level Package) is encapsulated with the fan-out wafer grade of substrate 1.
It should be noted that one can be formed after the engagement of the first connection gasket 31, the second connection gasket 14 and the second convex block 32
Post-like conductive structure, since the first connection gasket 31 and the second connection gasket 14 are uniformly distributed arrays, each column formed is led
There can be gap between electric structure, it is therefore desirable to which full primer 6 is filled in gap enables the first rewiring layer 3 to be connect with substrate 1
It is more firm, while primer 6 wraps up each post-like conductive structure and can play a protective role.
In a preferred embodiment, the primer 6 at the outer rim coated in 2 one end of memory chip storehouse body, which is formed, to fall
Corner structure further strengthens the stable connection of memory chip storehouse body 2 and substrate 1.
In some embodiments, further include the second primer 8, be formed in a side surface and the second of substrate 1 for cache chip 4
Between surface 12.
Specifically, after the engagement of each third connection gasket 41, each 4th connection gasket 15 and each third convex block 42, it is formed in caching
Full second primer 8 is filled in gap between one side surface of chip 4 and the second surface 12 of substrate 1；It is close in cache chip 4
The outer rim of 1 one end of substrate is coated with the second primer 6 of the part substrate 1 of covering cache chip 4 outer rim circumferential direction.
It should be noted that one can be formed after the engagement of third connection gasket 41, the 4th connection gasket 15 and third convex block 42
Post-like conductive structure, since third connection gasket 41 and the 4th connection gasket 15 are uniformly distributed arrays, each column formed is led
There can be gap between electric structure, it is therefore desirable to which full second primer 8 is filled in gap enables cache chip 4 to be connect with substrate 1
It is more firm, while the second primer 8 wraps up each post-like conductive structure and can play a protective role.
In a preferred embodiment, it is coated in the second primer 8 at the outer rim of 4 one end of cache chip and forms chamfering knot
Structure further strengthens the stable connection of cache chip 4 and substrate 1.
In the above-described embodiments, the material of the first primer 6 and the second primer 8 includes cilicon oxide filler.
In the above-described embodiments, the material of the first plastic-sealed body 7 includes silica and/or alumina packing.
In the above-described embodiments, substrate 1 selected from printed wiring board (pcb board), silicon intermediate plate (Si interposer) with
Reroute one of film (RDL) constituted group.In one preferred embodiment, substrate 1 is silicon intermediate plate, substrate
1 second surface 12 has the second rewiring layer formed by fan-out circuit 17, and conducting circuit 16 is silicon perforation (Through
Silicon Via) structure and with second reroute layer be electrically connected.The second surface 12 of substrate 1 is to reroute layer with single side
With the silicon intermediate plate of silicon perforation structure.
In the above-described embodiments, cache chip 4 is symmetrical arranged with memory chip storehouse body 2 in the both sides of substrate 1, i.e. axis
Line overlaps, to ensure to minimize the distance of signal transmission.
As shown in figure 5, the present embodiment additionally provides a kind of manufacturing method of chip double-side encapsulating structure, including：
There is provided has the substrate 1 of the first surface 11 and second surface 12 that are oppositely arranged；
The memory chip storehouse body 2 being made of 21 storehouse of multiple storage chips is provided；In memory chip storehouse body 2
Installation surface forms first and reroutes layer 3, and multiple conductive through holes 22 for electrical communication are formed on each storage chip 21,
First rewiring layer 3 is electrically connected each conductive through holes 22 of each storage chip 21 to substrate 1；
The first table in substrate 1 is arranged by chip bonding mode in memory chip storehouse body 2 by first time chip bonding
On face 11 (as shown in Figure 6)；
First time molding processing procedure forms the first plastic-sealed body 7 on the first surface 11 of substrate 1, with sealed storage device chip
Storehouse body 2 (as shown in Figure 6)；
Second of chip bonding provides cache chip 4 and it is arranged by chip bonding mode to the second table in substrate 1
On the middle section in face 12, and multiple metal gaskets 13 (as shown in Figure 6) are formed on the second surface；
Second of molding processing procedure forms the second plastic-sealed body 9 on the second surface 12 of substrate 1, and sealing cache chip 4 is (such as
Shown in Fig. 7)；
Thinning is handled, and carries out thinning to cache chip 4 and the second plastic-sealed body 9 by lapping mode, and ensure the second plastic packaging
The cache chip 4 (as shown in Figure 8) after sealing thinning is remained to after 9 thinning of body；
Drilling 91 is carried out at the position corresponding with each metal gasket 13 of 9 surface of the second plastic-sealed body, until exposing second
Each metal gasket 13 (as shown in Figure 8) on surface 12；
It is implanted into the terminal 5 being connect with metal gasket 13 in drilling 91 and is welded and fixed (as shown in Figure 2).
Wherein, the conducting circuit 16 for electrically running through substrate 1 is formed in substrate 1, and fan-out line is formed on second surface 12
Road 17 makes conducting circuit 16 be electrically connected cache chip 4 to the first and reroutes layer 3, and fan-out circuit 17 is electrically connected cache chip 4
To terminal 5.
In some embodiments, before first time molding processing procedure carry out first time dispensing, memory chip storehouse body 2 with
The first primer 6 is formed between the first surface 11 of substrate 1；
In some embodiments, second of dispensing is carried out before second of molding processing procedure, in a side surface of cache chip 4
The second primer 8 is formed between the second surface 12 of substrate 1.
In some embodiments, the middle section in the second surface 12 of substrate 1 is arranged in cache chip 4, and terminal 5 includes to set
Set multiple soldered balls in 4 periphery of cache chip.
In some embodiments, the thickness of the cache chip 4 after thinning is less than Diameter of Solder Ball.
In some embodiments, after the completion of memory chip storehouse body 2, first reroutes layer 3 and substrate 1 engages,
The first primer 6 is perfused with the gap of substrate 1 in first rewiring layer 3, and the extension of the first primer 6 is made to be diffused into memory chip heap
Outer rim of the stack body 2 close to 1 one end of substrate forms the first plastic-sealed body after three is bonded on the first surface 11 of substrate 1
7, it is packaged with sealed storage device chip stack body 2.
In some embodiments, the second primer 8 is perfused in the gap between cache chip 4 and substrate 1, and makes the second bottom
The extension of glue 8 is diffused into outer rim of the cache chip 4 close to 1 one end of substrate, improves the two stable connection.
In some embodiments, memory chip storehouse body 2 is directly made of multiple 21 storehouses of individual storage chip, or
It is independent memory chip storehouse body by being cut again after multiple uncut wafer storehouses being made of several storage chips 21.
It should be noted that when using multiple individual 21 storehouses of storage chip, conductive through holes 22 are formed on each storage chip 21
It is engaged with after the first convex block 23；Or conductive through holes 22 and the first convex block 23 will be formed on each storage chip 21 on wafer
Afterwards, each wafer storehouse is engaged by the first convex block 23, the wafer storehouse body after storehouse is then cut into single storage again
Device chip stack body 2.
In the above-described embodiments, cache chip 4 is carried out by grinding back surface (backside grinding) technology at thinning
Reason.
In the above-described embodiments, realize that the surface in the second plastic-sealed body 9 drills by laser drill mode.
In the above-described embodiments, terminal 5 realizes that terminal 5 is implanted into the second plastic packaging by printing technology, galvanoplastic or globule method
In the drilling 91 of body 9, and by Reflow Soldering by 5 firm welded of terminal.
In this manufacturing method, it should be strongly noted that when each component envelope positioned at 11 side of first surface of substrate 1
After dress, cache chip 4 can not be encapsulated on the second surface 12 of substrate 1 immediately, when client selects not according to need of work
When with chip, the particular cache chip 4 of needs can be installed to the second surface 12 of substrate 1 again according to performance and model demand
On, to improve apparatus of the present invention encapsulation and production flexibility, meet different use demands.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can readily occur in its various change or replacement,
These should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the guarantor of the claim
It protects subject to range.
Claims (15)
1. a kind of chip double-side encapsulating structure, which is characterized in that including：
Substrate has the first surface and second surface being oppositely arranged；
Memory chip storehouse body, chip bonding mode are arranged on the first surface of the substrate, are mainly deposited by multiple
Chip stack composition is stored up, the memory chip storehouse body has an installation surface；
First reroutes layer, is formed in the installation surface of the memory chip storehouse body, is electrically connected each described deposit
Chip is stored up to the substrate；
The middle section in the second surface of the substrate is arranged in cache chip, chip bonding mode；
Terminal is set on the second surface of the substrate；And
First plastic-sealed body and the second plastic-sealed body；First plastic-sealed body is formed on the first surface of the substrate, sealing
The memory chip storehouse body；Second plastic-sealed body is formed on the second surface of the substrate, is sealed described slow
Chip and the terminal are deposited at the link position of the second surface of the substrate, constitutes two-sided molding kenel；
First primer is formed between the memory chip storehouse body and the first surface of the substrate, and is made described
The extension of first primer is diffused into outer rim of the memory chip storehouse body close to described substrate one end, and first primer exists
The cover height of the side of the external edge of memory chip storehouse makes to be equipped with the described first storage chip for rerouting layer
Side substantially covered；
Multiple first connection gaskets are formed on one side surface of the first rewiring layer, shape on the first surface of the substrate
At multiple the second connection gaskets corresponding with first connection gasket, each first connection gasket and each second connection gasket are electrical
Connection.
2. chip double-side encapsulating structure as described in claim 1, which is characterized in that the substrate includes electrically running through the base
The conducting circuit of plate and the fan-out circuit on the second surface, the conducting circuit are electrically connected the cache chip and institute
Terminal is stated to the first rewiring layer, the fan-out circuit is electrically connected the cache chip to the terminal.
3. chip double-side encapsulating structure as described in claim 1, which is characterized in that include on each storage chip
Multiple conductive through holes for electrical communication, described first, which reroutes layer, is electrically connected each conductive through holes to the substrate.
4. chip double-side encapsulating structure as claimed in claim 3, which is characterized in that each storage chip is by being arranged each
First convex block of the conductive through holes end is electrically connected with each other.
5. chip double-side encapsulating structure as described in claim 1, which is characterized in that the terminal includes to be arranged in the caching
Multiple soldered balls of chip periphery.
6. chip double-side encapsulating structure as claimed in claim 5, which is characterized in that substrate shape on the second surface
At metal gasket, keep the engagement of the soldered ball and the substrate more firm.
7. chip double-side encapsulating structure as claimed in claim 5, which is characterized in that the thickness of the cache chip is less than described
The Diameter of Solder Ball of terminal.
8. chip double-side encapsulating structure as described in claim 1, which is characterized in that further include the second primer, be formed in described
Between one side surface of cache chip and the second surface of the substrate.
9. chip double-side encapsulating structure as described in claim 1, which is characterized in that the substrate, which is the second surface, to be had
Single side reroutes the silicon intermediate plate of layer and silicon perforation structure.
10. chip double-side encapsulating structure as described in claim 1, which is characterized in that each first connection gasket with it is each described
Second connection gasket is electrically connected by the second convex block being formed on first connection gasket.
11. a kind of manufacturing method of chip double-side encapsulating structure, which is characterized in that including：
There is provided has the substrate of the first surface and second surface that are oppositely arranged；
The memory chip storehouse body being made of multiple storage chip storehouses is provided, in the installation of the memory chip storehouse body
Surface forms first and reroutes layer, and multiple conductive through holes for electrical communication are formed on each storage chip, described
First rewiring layer is electrically connected each conductive through holes of each storage chip to the substrate；
The memory chip storehouse body is arranged by chip bonding mode described in the substrate for first time chip bonding
On first surface, including：Multiple first connection gaskets are formed on a side surface of the first rewiring layer, in the substrate
Multiple the second connection gaskets corresponding with first connection gasket, each first connection gasket and each institute are formed on the first surface
State the electric connection of the second connection gasket；
First time dispensing forms the first bottom between the memory chip storehouse body and the first surface of the substrate
Glue, and the first primer extension is made to be diffused into the memory chip storehouse body close to the outer rim of described substrate one end, make to set
There is the side of the storage chip of the first rewiring layer substantially to be covered；
First time molding processing procedure forms the first plastic-sealed body on the first surface of the substrate, seals the storage core
Piece storehouse body；
Second of chip bonding provides cache chip and it is arranged by chip bonding mode described the second of the substrate
On face center region, and multiple metal gaskets are formed on the second surface；
Second of molding processing procedure forms the second plastic-sealed body on the second surface of the substrate, seals the cache chip；
Thinning is handled, and thinning is carried out to the cache chip and second plastic-sealed body by lapping mode, and ensures described the
The cache chip after sealing thinning is remained to after two plastic-sealed body thinnings；
It drills at the position corresponding with each metal gasket of second plastic-sealed body surface, until exposing described the
Each metal gasket on two surfaces；
It is implanted into the terminal being connect with the metal gasket in the drilling and is welded and fixed, second plastic-sealed body seals the end
At the sub link position with the second surface of the substrate.
12. the manufacturing method of chip double-side encapsulating structure as claimed in claim 11, which is characterized in that
Second of dispensing is carried out before second of molding processing procedure, in a side surface of the cache chip and the substrate
The second primer is formed between the second surface.
13. the manufacturing method of chip double-side encapsulating structure as claimed in claim 11, which is characterized in that the terminal includes to set
Set multiple soldered balls in cache chip periphery.
14. the manufacturing method of chip double-side encapsulating structure as claimed in claim 13, which is characterized in that described slow after thinning
The thickness for depositing chip is less than the Diameter of Solder Ball.
15. the manufacturing method of chip double-side encapsulating structure as claimed in claim 11, which is characterized in that the memory chip
Storehouse body is directly made of multiple individually storage chip storehouses, or will be multiple uncut by several storage chips
It is cut again after the wafer storehouse of composition and is independent the memory chip storehouse body.
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| CN201710755489.7A CN107564825B (en) | 2017-08-29 | 2017-08-29 | A kind of chip double-side encapsulating structure and its manufacturing method |
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| CN201710755489.7A CN107564825B (en) | 2017-08-29 | 2017-08-29 | A kind of chip double-side encapsulating structure and its manufacturing method |
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| CN112447534B (en) * | 2019-08-30 | 2023-12-15 | 天芯互联科技有限公司 | Package and method for manufacturing the same |
| CN111540686A (en) * | 2020-03-23 | 2020-08-14 | 江苏长电科技股份有限公司 | Packaging process for laser post-planting balls |
| CN115101519A (en) * | 2022-08-29 | 2022-09-23 | 盛合晶微半导体(江阴)有限公司 | Three-dimensional stacked fan-out type packaging structure and preparation method thereof |
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| US7616470B2 (en) * | 2006-06-16 | 2009-11-10 | International Business Machines Corporation | Method for achieving very high bandwidth between the levels of a cache hierarchy in 3-dimensional structures, and a 3-dimensional structure resulting therefrom |
| KR101784507B1 (en) * | 2011-12-14 | 2017-10-12 | 에스케이하이닉스 주식회사 | Semiconductor stack package and manufacturing method for the same, and electronic system comprising the same |
| CN202394963U (en) * | 2011-12-28 | 2012-08-22 | 日月光半导体制造股份有限公司 | Multi-chip wafer-level semiconductor packaging structure |
| KR20160122021A (en) * | 2015-04-13 | 2016-10-21 | 에스케이하이닉스 주식회사 | Semiconductor package having metal post |
| KR101712288B1 (en) * | 2015-11-12 | 2017-03-03 | 앰코 테크놀로지 코리아 주식회사 | Package of semiconductor and method for manufacturing the same |
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Effective date of registration: 20180928 Address after: 230000 room 630, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Patentee after: Changxin Storage Technology Co., Ltd. Address before: 230000 room 526, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Patentee before: Ever power integrated circuit Co Ltd |