CN107045992A - Imaging sensor wafer-level encapsulation method and encapsulating structure - Google Patents
Imaging sensor wafer-level encapsulation method and encapsulating structure Download PDFInfo
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- CN107045992A CN107045992A CN201710256171.4A CN201710256171A CN107045992A CN 107045992 A CN107045992 A CN 107045992A CN 201710256171 A CN201710256171 A CN 201710256171A CN 107045992 A CN107045992 A CN 107045992A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Abstract
The present invention provides a kind of imaging sensor wafer-level encapsulation method and encapsulating structure, comprises the following steps：Image sensor chip is provided, described image sensor chip includes image sensing cell and pad electrode, and in forming the first solder bump on the pad electrode；A substrate is provided, in substrate back formation groove；Interconnection structure is formed on the substrate；Described image sensor flip-chip is welded on the interconnection structure of the bottom portion of groove；In described image sensor chip back and substrate back formation dielectric layer；Form the second solder bump.The present invention reduces the thickness of whole encapsulating structure using face-down bonding technique twice；The back side uses medium Rotating fields; interconnection structure can not only be protected, image sensing cell can be more sealed in airtight cavity, it also avoid moisture while pollution is avoided enters; improve reliability, it is to avoid the warpage issues that the heterogeneous bonding tape of conventional wafer level packaging comes.
Description
Technical field
The present invention relates to image sensor package manufacturing technology field, more particularly to a kind of imaging sensor wafer level envelope
Dress method and encapsulating structure.
Background technology
With the development of information technology, imaging sensor is widely used in the electronic product of daily life, while industry is raw
Production and detection are to intelligentized demand so that imaging sensor has obtained wider application.
The imaging sensor wafer-level package structure of existing T-shaped connected mode is as shown in figure 1, in sensor disk 101
It is upper by predetermined process formation multiple images sensor chip, image sensor chip include sensing unit 102 and with will described in
The pad electrode 103 that sensing unit 102 is drawn；Sensor disk 101 is bonded with a transparency carrier 104, jointing material is tree
Fat 105；Expose the pad electrode 103 in the back side dry etching of the pad electrode 103；In the imaging sensor wafer back of the body
Face and covering resin 105 in groove, and be bonded with a substrate 106.Positive electricity is exposed in the mechanical paddle-tumble mode of wafer rear
Pole, then carries out metal deposit, forms T-shaped connection 110 so that the pad electrode 103 is drawn out to the back side, and make back electricity
Pole 108；The scribing of line of cut 109 at the last centers of Yan Cao 107 obtains one single chip.However, this structure completes to carry out in encapsulation
After scribing, interconnection area is fairly small, and lead easily causes moisture and chemical substance to enter encapsulation along lead exposed to outside
In vivo, cause dissimilar materials lamination, ultimately result in interconnection failure, cause the low problem of reliability；The heterogeneous key of sandwich construction
Close, easily in high-power operation, high temperature causes warpage issues.
The image sensor package structure of existing wire bonding interconnection mode is as shown in Fig. 2 by image sensing to be packaged
The active area 205 of device chip 201 is fixed on substrate 204 upwardly through adhesive, then by lead 203 imaging sensor
On pad electrode 202 interconnected with substrate pads electrode 206.This packing forms, encapsulation flow is simple, and cost is low, but has
Apparent shortcoming, reliability is low, and packaging density is small, and active face is exposed to outside, easily causes pollution.
The content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of imaging sensor wafer level envelope
Dress method and encapsulating structure, for solving the packaging density that imaging sensor wafer-level package structure of the prior art is present
It is small, to easily cause pollution, reliability low and the problem of easily cause warpage.
In order to achieve the above objects and other related objects, the present invention provides a kind of above-mentioned imaging sensor wafer level packaging side
Method, described image sensor wafer-level encapsulation method comprises the following steps：
Image sensor chip is provided, described image sensor chip includes image sensing cell and sensed with described image
Unit is connected and positioned at the pad electrode of described image sensor chip front side, and formation first is welded on the pad electrode
Expect salient point；
A substrate is provided, in substrate back formation groove；
Interconnection structure is formed on the substrate, and the interconnection structure prolongs from the bottom portion of groove via the recess sidewall
Extend the back side of the substrate；
Described image sensor flip-chip is welded on the interconnection structure of the bottom portion of groove；
In described image sensor chip back and substrate back formation dielectric layer, the dielectric layer is by described image
Recess space between sensor chip and the substrate seals to form seal cavity；
The second solder bump is formed, second solder bump is connected with the interconnection structure positioned at the substrate back
Connect.
As a kind of preferred scheme of the imaging sensor wafer-level encapsulation method of the present invention, the depth of the groove is more than
Or equal to the thickness sum of the interconnection structure, first solder bump and described image sensor chip three, it is described recessed
The lateral dimension of groove is more than the lateral dimension of described image sensor chip.
As a kind of preferred scheme of the imaging sensor wafer-level encapsulation method of the present invention, formed using laser ball implanting method
First solder bump and second solder bump.
As a kind of preferred scheme of the imaging sensor wafer-level encapsulation method of the present invention, formed using laser ball implanting method
Reflux temperature during second solder bump is less than the fusing point of first solder bump.
As a kind of preferred scheme of the imaging sensor wafer-level encapsulation method of the present invention, the substrate is photosensitive glass
Glass, by photoetching, is developed in the substrate back and forms the groove.
As a kind of preferred scheme of the imaging sensor wafer-level encapsulation method of the present invention, first solder is formed convex
Point comprises the following steps：
Opening is formed in the dielectric layer, the opening exposes the interconnection structure positioned at the substrate back；
In exposed interconnection structure surface formation UBM layer；
Second solder bump is formed on the UBM layer surface.
As a kind of preferred scheme of the imaging sensor wafer-level encapsulation method of the present invention, second solder is formed convex
Point after, in addition to by obtained structure carry out scribing to form independent packaging the step of.
The present invention also provides a kind of imaging sensor wafer-level package structure, described image sensor wafer-level package structure
Including：
Substrate, the substrate back forms fluted；
Interconnection structure, the back side of the substrate is extended to from the bottom portion of groove via the recess sidewall；
Image sensor chip, described image sensor chip include image sensing cell and with described image sensing unit
It is connected and positioned at the pad electrode of described image sensor chip front side；
First solder bump, positioned at the pad electrode surface；Described image sensor chip is via first solder
Salient point upside-down mounting is welded on the interconnection structure of the bottom portion of groove；
Dielectric layer, positioned at described image sensor chip back and the substrate back, the dielectric layer is by described image
Recess space between sensor chip and the substrate seals to form seal cavity；
Second solder bump, is connected positioned at the substrate back, and with the interconnection structure positioned at the substrate back
Connect.
As a kind of preferred scheme of the imaging sensor wafer-level package structure of the present invention, the substrate is photosensitive glass
Glass.
As a kind of preferred scheme of the imaging sensor wafer-level package structure of the present invention, the depth of the groove is more than
Or equal to the thickness sum of the interconnection structure, first solder bump and described image sensor chip three, it is described recessed
The lateral dimension of groove is more than the lateral dimension of described image sensor chip.
It is used as a kind of preferred scheme of the imaging sensor wafer-level package structure of the present invention, described image sensor chip
Edge to the recess sidewall spacing be 10 μm~20 μm.
As a kind of preferred scheme of the imaging sensor wafer-level package structure of the present invention, the side wall of the groove and institute
The back side for stating substrate is perpendicular.
It is used as a kind of preferred scheme of the imaging sensor wafer-level package structure of the present invention, described image sensor disk
Class encapsulation structure also includes UBM layer, and the UBM layer is located at the mutual link of second solder bump and the substrate back
Between structure, the UBM layer is connected with the interconnection structure positioned at the substrate back.
As described above, the imaging sensor wafer-level encapsulation method and encapsulating structure of the present invention, have the advantages that：
The present invention greatly reduces the thickness of whole encapsulating structure using face-down bonding technique twice；The back side uses dielectric layer knot
Structure, can not only be protected to interconnection structure, the image sensing cell in image sensor chip can be more sealed in close
In closed chamber body, moisture entrance is it also avoid while pollution is avoided, reliability is improved；Meanwhile, this wafer level packaging side
Method avoids the warpage issues that the heterogeneous bonding tape of conventional wafer level packaging comes, by reducing the technique directly to chip, it is to avoid
Chip is damaged, and improves yield rate.
Brief description of the drawings
Fig. 1 is shown as the cross section structure of the imaging sensor wafer-level package structure of T-shaped interconnection mode of the prior art
Schematic diagram.
The cross section structure that Fig. 2 is shown as the image sensor package structure of wire bonding interconnection mode of the prior art shows
It is intended to.
Fig. 3 is shown as the flow chart of the imaging sensor wafer-level encapsulation method provided in the embodiment of the present invention one.
Fig. 4 to Fig. 9 is shown as the imaging sensor wafer-level encapsulation method provided in the embodiment of the present invention one in each step
Cross section structure schematic diagram..
Component label instructions
101 sensor disks
102 image sensing cells
103 pad electrodes
104 transparency carriers
105 resins
106 substrates
107 grooves
108 back electrodes
109 lines of cut
110 T-shaped connections
201 image sensor chips to be packaged
202 first pad electrodes
203 leads
204 substrates
205 active areas
206 second pad electrodes
3 image sensor chips
31 image sensing cells
32 pad electrodes
33 first solder bumps
34 substrates
4 substrates
41 grooves
5 interconnection structures
6 dielectric layers
7 second solder bumps
S1~S6 steps
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Fig. 3 is referred to Fig. 9.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, though only display is with relevant component in the present invention rather than according to package count during actual implement in schema
Mesh, shape and size are drawn, and form, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout kenel may also be increasingly complex.
Embodiment one
As shown in figure 3, the present invention provides a kind of imaging sensor wafer-level encapsulation method, described image sensor wafer level
Method for packing at least comprises the following steps：
S1：Image sensor chip is provided, described image sensor chip includes image sensing cell and and described image
Sensing unit is connected and positioned at the pad electrode of described image sensor chip front side, and forms on the pad electrode the
One solder bump；
S2：A substrate is provided, in substrate back formation groove；
S3：Interconnection structure is formed on the substrate, and the interconnection structure is from the bottom portion of groove via the groove side
Wall extends to the back side of the substrate；
S4：Described image sensor flip-chip is welded on the interconnection structure of the bottom portion of groove；
S5：In described image sensor chip back and substrate back formation dielectric layer, the dielectric layer will be described
Recess space between image sensor chip and the substrate seals to form seal cavity；
S6：Form the second solder bump, second solder bump and the interconnection structure positioned at the substrate back
It is connected.
The S1 steps and Fig. 4 in Fig. 3 are referred to there is provided image sensor chip 3, described image sensor chip 3 includes
Image sensing cell 31 and it is connected with described image sensing unit 31 and positioned at the positive pad of described image sensor chip 3
Electrode 32, and form on the pad electrode 32 first solder bump 33.
As an example, described image sensing unit 31 is located at the active area in the substrate 34 of described image sensor chip 3
It is interior, and positioned at the front of described image sensor chip 3.
As an example, extraction electrode of the pad electrode 32 as described image sensing unit 31, material can be but
It is not limited only to aluminium.The pad electrode 32 is located in the non-active area of the periphery of described image sensing unit 31.
As an example, first solder bump 33 can be formed using plating or laser ball implanting method；Preferably, this implementation
In example, first solder bump 33 is formed using laser ball implanting method, laser ball implanting method is well known to those skilled in the art, this
Place is not repeated.
As an example, the melting temperature of first solder bump 33 can be but be not limited only to 230 DEG C~250 DEG C；Institute
Stating the first solder bump 33 can be but be not limited only to SAC salient point or indium bump.
As an example, being shaped as first solder bump 33 is spherical, with reference to the pad electrode 32 size and can
By property, the diameter of first solder bump 33 can be but be not limited only to 40 μm~50 μm.
The S2 steps and Fig. 5 in Fig. 3 are referred to there is provided a substrate 4, groove 41 is formed at the back side of substrate 4.
As an example, the material of the substrate 4 can be selected according to actual needs, it is preferable that in the present embodiment, institute
Substrate 4 is stated for photosensitive glass, the photosensitive glass can reach more than 92% in visible-range iuuminting rate.
Preferably, in the present embodiment, by photoetching, it is developed in the back side of substrate 4 and forms the groove 41.Specifically,
By controlling photoetching, the time developed to form required depth, side wall and the substrate 4 the back of the body at the back side of substrate 4
The vertical groove 41 of face type.Using photosensitive glass as the substrate 4, directly it can be exposed with photolithography plate as mask
Light, without photoresist used in spin coating conventional lithographic.
As an example, the depth of the groove 41 is more than or equal to the interconnection structure 5 subsequently to be formed, described first
Solder bump 33 and the thickness sum of the three of described image sensor chip 3, the lateral dimension of the groove 41 are more than the figure
As the lateral dimension of sensor chip 3, to ensure described image sensor chip 3 can be sealed into envelope in follow-up encapsulation process
Loaded in the groove 41.
As an example, the spacing of the edge of described image sensor chip 3 to the side wall of groove 41 is 10 μm~20 μm.
As an example, the thickness of the substrate 4 and the difference of depth of the groove 41 can be 150 μm~200 μm, i.e. institute
The depth of stating groove 41 described in the thickness ratio of substrate 4 is big 150 μm~and 200 μm, that is, the bottom of the groove 41 to the substrate
4 positive distances are 150 μm~200 μm.
As an example, the quantity for the groove 41 that the back side of the substrate 4 is formed can be set according to actual needs；It is excellent
Selection of land, the substrate 4 is wafer level substrate, and the back side of the substrate 4 forms multiple grooves 41, for multiple described images
Sensor chip 3 is packaged simultaneously.
S3 steps and Fig. 6 in Fig. 3 are referred to, interconnection structure 5 is formed on the substrate 4, the interconnection structure 5 is from institute
State the back side that the bottom of groove 41 extends to the substrate 4 via the side wall of groove 41.
Comprise the following steps as an example, forming interconnection structure 5 on the substrate 4：
S31：Layer of metal layer (not shown), tool are formed at the back side, the bottom of the groove 41 and side wall of the substrate 4
Body, magnetron sputtering technique can be used to form one layer of TiW/ at the back side, the bottom of the groove 41 and side wall of the substrate 4
Cu；
S32：The layer on surface of metal spray photoresist layer, by the photoetching offset plate figure be defined as it is described it is mutual link
The figure of structure 5；Specifically, removing part photoresist using photoetching process, the photoresist of reservation is defined as the mutual link
The shape of structure 5；
S33：Exposed metal level is removed using metal erosion technique, the photoresist layer is removed, that is, obtains the interconnection
Structure 5.
In other examples, the interconnection structure 5 can also be multiple layer metal Rotating fields, the material of the interconnection structure 5
Can be TiW/Cu, Ti/Cu or Ni/Cu.
It should be noted that in other examples, step S1 can be exchanged with step S2 and step S3 order, i.e.,
Both step S1~step S3 can be performed successively as described above, step S2, step S3 can also be first carried out, step is performed again afterwards
S1。
S4 steps and Fig. 7 in Fig. 3 are referred to, the upside-down mounting of described image sensor chip 3 is welded in positioned at the groove 41
On the interconnection structure 5 of bottom.
As an example, Bumping Technology can be used, i.e., as described above by positive described in described image sensor chip 3
The upside-down mounting of described image sensor chip 3 is welded in positioned at the groove by the method that the first solder bump 33 is formed on pad electrode 32
On the interconnection structure 5 of 41 bottoms, the positive pad electrode 32 of described image sensor chip 3 is via the described first weldering
Material salient point 33 is connected with the interconnection structure 5 positioned at the bottom of groove 41.
S5 steps and Fig. 8 in Fig. 3 are referred to, is formed at the back side of described image sensor chip 3 and the back side of the substrate 4
Dielectric layer 6, the dielectric layer 6 is close to be formed by the recess space sealing between described image sensor chip 3 and the substrate 4
Seal cavity.
As an example, can be in the back side of described image sensor chip 3 and the substrate 4 back side spin coating, one layer of organic media
Layer is used as the dielectric layer 6 of the invention.The organic dielectric layer of institute's spin coating can pass through described image sensor chip 3 and institute
Gap between substrate 4 is stated to flow into the groove 41, due to the front of described image sensor chip 3 be formed with it is highdensity
First solder bump 33, first solder bump 33 can stop the organic media being flowed into the groove 41
Layer so that the organic dielectric layer will not reach described image sensing unit 31, will not be caused to described image sensing unit 31
Pollution, does not interfere with its luminous flux.
S6 steps and Fig. 9 in Fig. 3 are referred to, the second solder bump 7 is formed, second solder bump 7 is with being located at institute
The interconnection structure 5 for stating the back side of substrate 4 is connected.
As an example, second solder bump 7 can be formed using plating or laser ball implanting method, it is preferable that this implementation
In example, two solder bump 7 is formed using laser ball implanting method.It should be noted that forming described using laser ball implanting method
Reflux temperature during two solder bumps 7 is less than the fusing point of first solder bump 33, to ensure forming described second
First solder bump 33 will not be caused during solder bump 7 to damage.
As an example, the distance of the bottom of second solder bump 7 to the bottom of groove 41 is than first solder
The distance at the top of salient point 33 to the back side of described image sensor chip 3 is big 150 μm~and 200 μm.
Comprise the following steps as an example, forming second solder bump 7：
S61：Opening (not shown) is formed in the dielectric layer 6, the opening is exposed positioned at the back side of substrate 4
The interconnection structure 5；
S62：UBM layer (ubm layer) is formed on the exposed surface of the interconnection structure 5；Specifically, first sputtering one
Layer TiW/Cu Seed Layers, then expose etching window by photoetching, are thickeied, are gone finally by metal erosion technique by electroplating
Except Seed Layer to form the UBM layer；
S63：Second solder bump 7 is formed on the UBM layer surface using laser ball implanting method.
As an example, being shaped as second solder bump 7 is spherical, the diameter of second solder bump 7 can be
90 μm~100 μm, to ensure the reliability of interconnection.
As an example, being formed after second solder bump 7, in addition to obtained structure is carried out scribing to be formed solely
The step of vertical packaging.
Embodiment two
Please continue to refer to Fig. 9, the present invention also provides a kind of imaging sensor wafer-level package structure, described image sensor
Wafer-level package structure is encapsulated by the method for packing in embodiment one and obtained, described image sensor wafer-level package structure bag
Include：Substrate 4, the back side of substrate 4 forms fluted 41；Interconnection structure 5, the interconnection structure 5 is passed through from the bottom of groove 41
The back side of the substrate 4 is extended to by the side wall of groove 41；Image sensor chip 3, described image sensor chip 3 includes
Image sensing cell 31 and it is connected with described image sensing unit 31 and positioned at the positive pad of described image sensor chip 3
Electrode 32；First solder bump 33, first solder bump 33 is located at the surface of pad electrode 32；Described image sensor
Chip 3 is welded on the interconnection structure 5 of the bottom of groove 41 via the upside-down mounting of the first solder bump 33；Dielectric layer
6, the dielectric layer 6 is located at the back side of described image sensor chip 3 and the back side of the substrate 4, and the dielectric layer 6 is by described image
Recess space between sensor chip 3 and the substrate 4 seals to form seal cavity；Second solder bump 7, described second
Solder bump 7 is located at the back side of substrate 4, and is connected with the interconnection structure 5 positioned at the back side of substrate 4.
As an example, the substrate 4 is photosensitive glass.
As an example, the quantity of the groove 41 at the back side of substrate 4 can for one, it is two or more, it is preferable that
In the present embodiment, the substrate 4 is wafer level substrate, and the quantity of the groove 41 at the back side of substrate 4 is multiple.
As an example, extraction electrode of the pad electrode 32 as described image sensing unit 31, material can be but
It is not limited only to aluminium.The pad electrode 32 is located in the non-active area of the periphery of described image sensing unit 31.
As an example, the melting temperature of first solder bump 33 can be but be not limited only to 230 DEG C~250 DEG C；Institute
Stating the first solder bump 33 can be but be not limited only to SAC salient point or indium bump.
As an example, being shaped as first solder bump 33 is spherical, with reference to the pad electrode 32 size and can
By property, the diameter of first solder bump 33 can be but be not limited only to 40 μm~50 μm.
As an example, the depth of the groove 41 be more than or equal to the interconnection structure 5, first solder bump 33 and
The thickness sum of the three of described image sensor chip 3, the lateral dimension of the groove 41 is more than described image sensor chip 3
Lateral dimension.
As an example, the spacing of the edge of described image sensor chip 3 to the side wall of groove 41 is 10 μm~20 μm.
As an example, the back side of the side wall of the groove 41 and the substrate 4 is perpendicular.
As an example, the thickness of the substrate 4 and the difference of depth of the groove 41 can be 150 μm~200 μm, i.e. institute
The depth of stating groove 41 described in the thickness ratio of substrate 4 is big 150 μm~and 200 μm, that is, the bottom of the groove 41 to the substrate
4 positive distances are 150 μm~200 μm.
As an example, the distance of the bottom of second solder bump 7 to the bottom of groove 41 is than first solder
The distance at the top of salient point 33 to the back side of described image sensor chip 3 is big 150 μm~and 200 μm.
As an example, being shaped as second solder bump 7 is spherical, the diameter of second solder bump 7 can be
90 μm~100 μm, to ensure the reliability of interconnection.
As an example, described image sensor wafer-level package structure also includes UBM layer (not shown), the UBM layer position
It is between the interconnection structure 5 at second solder bump 7 and the back side of the substrate 4, the UBM layer is described with being located at
The interconnection structure 5 at the back side of substrate 4 is connected.
In summary, the present invention provides a kind of imaging sensor wafer-level encapsulation method and encapsulating structure, and described image is passed
Sensor wafer-level encapsulation method comprises the following steps：There is provided one includes the image sensor chip of image sensor chip, described
Image sensor chip includes image sensing cell and is connected with described image sensing unit and positioned at described image sensor
The pad electrode of chip front side, and form on the pad electrode the first solder bump；A substrate is provided, in the substrate back of the body
Face forms groove；Interconnection structure is formed on the substrate, and the interconnection structure is from the bottom portion of groove via the groove side
Wall extends to the back side of the substrate；Described image sensor flip-chip is welded in the interconnection positioned at the bottom portion of groove
In structure；In described image sensor chip back and substrate back formation dielectric layer, the dielectric layer is by described image
Recess space between sensor chip and the substrate seals to form seal cavity；Form the second solder bump, described
Two solder bumps are connected with the interconnection structure positioned at the substrate back.The present invention uses face-down bonding technique twice, very
The thickness of whole encapsulating structure is reduced in big degree；The back side uses medium Rotating fields, and not only interconnection structure can be protected
Shield, can more be sealed in the image sensing cell in image sensor chip in airtight cavity, while pollution is avoided
Moisture entrance is avoided, reliability is improved；Meanwhile, this wafer-level encapsulation method avoids the heterogeneous of conventional wafer level packaging
The warpage issues that bonding tape comes, by reducing the technique directly to chip, it is to avoid chip is damaged, and improves yield rate.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (13)
1. a kind of imaging sensor wafer-level encapsulation method, it is characterised in that described image sensor wafer-level encapsulation method bag
Include following steps：
There is provided image sensor chip, described image sensor chip include image sensing cell and with described image sensing unit
It is connected and positioned at the pad electrode of described image sensor chip front side, and it is convex to form on the pad electrode the first solder
Point；
A substrate is provided, in substrate back formation groove；
Interconnection structure is formed on the substrate, and the interconnection structure is extended to from the bottom portion of groove via the recess sidewall
The back side of the substrate；
Described image sensor flip-chip is welded on the interconnection structure of the bottom portion of groove；
In described image sensor chip back and substrate back formation dielectric layer, the dielectric layer senses described image
Recess space between device chip and the substrate seals to form seal cavity；
The second solder bump is formed, second solder bump is connected with the interconnection structure positioned at the substrate back.
2. imaging sensor wafer-level encapsulation method according to claim 1, it is characterised in that：The depth of the groove is big
In or equal to the interconnection structure, first solder bump and described image sensor chip three thickness sum, it is described
The lateral dimension of groove is more than the lateral dimension of described image sensor chip.
3. imaging sensor wafer-level encapsulation method according to claim 1, it is characterised in that：Using laser ball implanting method shape
Into first solder bump and second solder bump.
4. imaging sensor wafer-level encapsulation method according to claim 3, it is characterised in that：Using laser ball implanting method shape
It is less than the fusing point of first solder bump into the reflux temperature during second solder bump.
5. imaging sensor wafer-level encapsulation method according to claim 1, it is characterised in that：The substrate is photosensitive glass
Glass, by photoetching, is developed in the substrate back and forms the groove.
6. imaging sensor wafer-level encapsulation method according to claim 1, it is characterised in that：Form second solder
Salient point comprises the following steps：
Opening is formed in the dielectric layer, the opening exposes the interconnection structure positioned at the substrate back；
In exposed interconnection structure surface formation UBM layer；
Second solder bump is formed on the UBM layer surface.
7. imaging sensor wafer-level encapsulation method according to claim 1, it is characterised in that：Form second solder
After salient point, in addition to by obtained structure carry out scribing to form independent packaging the step of.
8. a kind of imaging sensor wafer-level package structure, it is characterised in that described image sensor wafer-level package structure bag
Include：
Substrate, the substrate back forms fluted；
Interconnection structure, the back side of the substrate is extended to from the bottom portion of groove via the recess sidewall；
Image sensor chip, described image sensor chip includes image sensing cell and is connected with described image sensing unit
Connect and positioned at the pad electrode of described image sensor chip front side；
First solder bump, positioned at the pad electrode surface；Described image sensor chip is via first solder bump
Upside-down mounting is welded on the interconnection structure of the bottom portion of groove；
Dielectric layer, positioned at described image sensor chip back and the substrate back, the dielectric layer senses described image
Recess space between device chip and the substrate seals to form seal cavity；
Second solder bump, is connected positioned at the substrate back, and with the interconnection structure positioned at the substrate back.
9. imaging sensor wafer-level package structure according to claim 8, it is characterised in that：The substrate is photosensitive glass
Glass.
10. imaging sensor wafer-level package structure according to claim 8, it is characterised in that：The depth of the groove
More than or equal to the thickness sum of the interconnection structure, first solder bump and described image sensor chip three, institute
The lateral dimension for stating groove is more than the lateral dimension of described image sensor chip.
11. imaging sensor wafer-level package structure according to claim 8, it is characterised in that：Described image sensor
The edge of chip to the spacing of the recess sidewall is 10 μm~20 μm.
12. imaging sensor wafer-level package structure according to claim 8, it is characterised in that：The side wall of the groove
The back side with the substrate is perpendicular.
13. imaging sensor wafer-level package structure according to claim 8, it is characterised in that：Described image sensor
Wafer-level package structure also includes UBM layer, the UBM layer be located at second solder bump and the substrate back it is described mutually
Link between structure, the UBM layer is connected with the interconnection structure positioned at the substrate back.
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