CN204204898U - The LED graphics-optimized substrate of a kind of circular cone bunch type pattern and LED chip - Google Patents

The LED graphics-optimized substrate of a kind of circular cone bunch type pattern and LED chip Download PDF

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Publication number
CN204204898U
CN204204898U CN201420740377.6U CN201420740377U CN204204898U CN 204204898 U CN204204898 U CN 204204898U CN 201420740377 U CN201420740377 U CN 201420740377U CN 204204898 U CN204204898 U CN 204204898U
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China
Prior art keywords
circular cone
bunch
substrate
led
pattern
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CN201420740377.6U
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Chinese (zh)
Inventor
李国强
钟立义
林志霆
乔田
周仕忠
王海燕
王凯诚
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South China University of Technology SCUT
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South China University of Technology SCUT
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Abstract

The utility model discloses LED graphics-optimized substrate and the LED chip of a kind of circular cone bunch type pattern, the pattern of substrate is made up of the circular cone bunch that the multiple shapes being arranged in substrate surface are identical; Described circular cone bunch is made up of a large circular cone, multiple middle circular cone and multiple conicle; Described multiple middle circular cone is arranged in a circle around large circular cone, circular cone circle in formation; Described multiple conicle is arranged in a circle around middle circular cone circle, forms conicle circle.Compared with prior art, have the light extraction efficiency more excellent than general substrate LED chip, circular cone bunch adds reflective surface area to the utility model, has obvious gain effect, be particularly suitable for chip package to bottom bright dipping; Actual handling ease obtains target pattern, easy to utilize.

Description

The LED graphics-optimized substrate of a kind of circular cone bunch type pattern and LED chip
Technical field
The utility model relates to LED graphics-optimized substrate, particularly the LED graphics-optimized substrate of a kind of circular cone bunch type pattern and LED chip.
Background technology
GaN base LED has the advantages such as brightness is high, energy consumption is low, the life-span is long, is widely used in the field such as full-color display and general illumination.But current GaN base LED technology of preparing can not give play to its whole potentiality, effect of general commercial LED has been about 130lm/W, far below effect 360lm/W that LED is maximum in theory.The factor that restriction LED effect promotes is mainly concerned with two aspects, is namely internal quantum efficiency and the light extraction efficiency of LED.On the one hand, between GaN epitaxial layer and sapphire epitaxial substrate, there is the lattice mismatch of about 16% and the coefficient of thermal expansion mismatch degree of about 26%, make the interior existence of GaN epitaxial layer on plane sapphire substrate up to 10 8~ 10 10cm -2dislocation density, cause the internal quantum efficiency of LED not high.On the other hand, Sapphire Substrate, be respectively 1.7,2.5 and 1.0 between GaN layer and the refractive index of air, difference is huge, makes the photon escape angle of LED surface be only 23 °, greatly reduces light extraction efficiency.
In order to improve the problem of these two aspects, many new technologies are suggested and are applied to rapidly in the preparation of LED.These technology include low temperature buffer layer technology, transversal epitaxial growth technology, surface coarsening, patterned substrate technology and nanometer embossing etc.In recent years, patterned substrate technology receives extensive concern because of having dual gain effect to LED, becomes the study hotspot in this field.Patterned substrate technology can make the GaN epitaxy on substrate occur the effect of horizontal extension, decreases crystal defect, improves internal quantum efficiency.Meanwhile, on substrate micro-pattern can change light transmition path by scattering, light is diminished (being less than the cirtical angle of total reflection) in the incidence angle of Air Interface, has made more light transmissives and gone out, thus having improve light extraction efficiency.For meeting the requirement of device performance, the design several kinds of renewals of graph substrate, from initial flute profile to hexagon, taper, prismatic table shape etc., the effect of graph substrate technology is approved.
At present, the development of patterned substrate has two kinds of trend.A kind of trend increases pattern dimension, and give pattern some particular design in shape, and another kind of trend be reduce pattern size until Nano grade.The people such as Y.K.Su, by the research to pattern-pitch in graph substrate, in conjunction with ICP technique, conventional lithographic techniques and nanometer embossing, make the pattern that spacing is respectively 150nm, 2um and 3um on a sapphire substrate.Compared with traditional Sapphire Substrate, the graph substrate of 150nm spacing demonstrates higher external quantum efficiency, reaches the level of 16.39%.The people such as R.Hsueh prepare with nanometer embossing the circular hole pattern that diameter, interval and the degree of depth are respectively 240nm, 450nm, 165nm, the light intensity of the LED chip that this graph substrate is prepared and light extraction efficiency improve 67% and 38% than common Sapphire Substrate LED respectively, and this light efficiency promotes effect and is better than micron order graph substrate LED.But not dimension of picture is less, and the performance of LED is better, the relation between dimension of picture and LED performance still needs balance.Research shows: along with the reduction of pattern-pitch, the cavity produced because GaN growth has little time to heal easily is there is at GaN and sapphire interface, and cause the more dislocation of epitaxial loayer, even if light extraction efficiency promotes to some extent, but the increase of epitaxial loayer dislocation can reduce the LED chip life-span.In addition, nano-scale patterns manufacturing cost is high, and industrialization difficulty, greatly limit the propagation and employment of nano-scale pattern substrate LED chip.
Utility model content
In order to overcome the above-mentioned shortcoming of prior art with not enough, the purpose of this utility model is the LED graphics-optimized substrate providing a kind of circular cone bunch type pattern, substantially increases the ability that reflects photons arrives LED chip top and bottom.
Another object of the present utility model is that providing package contains the LED chip of the LED graphics-optimized substrate of above-mentioned circular cone bunch type pattern.
The purpose of this utility model is achieved through the following technical solutions:
A LED graphics-optimized substrate for circular cone bunch type pattern, the pattern of substrate is made up of the circular cone bunch that the multiple shapes being arranged in substrate surface are identical;
Described circular cone bunch is made up of a large circular cone, multiple middle circular cone and multiple conicle; Described multiple middle circular cone is arranged in a circle around large circular cone, circular cone circle in formation; Described multiple conicle is arranged in a circle around middle circular cone circle, forms conicle circle;
The height H of each large circular cone lbe 1.0 ~ 2.0 μm, bottom surface radius R lit is 0.6 ~ 1.2 μm;
The height H of each middle circular cone mbe 0.75 ~ 1.25 μm, bottom surface radius R mit is 0.25 ~ 0.5 μm;
The height H of each conicle sbe 0.3 ~ 0.67 μm, bottom surface radius R sit is 0.15 ~ 0.4 μm;
The back gauge d of adjacent circular cone bunch is 1 ~ 4 μm.
The circular cone bunch that described multiple shape is identical adopts rectangular arrangement pattern.
The circular cone bunch that described multiple shape is identical adopts hexagonal arrangement mode.
The circular cone bunch that described multiple shape is identical adopts circular arrangement mode.
The circular cone bunch that described multiple shape is identical adopts diamond array mode.
A kind of LED chip, comprises the LED graphics-optimized substrate of above-mentioned circular cone bunch type pattern.
Compared with prior art, the utility model has the following advantages and beneficial effect:
(1) the utility model is by circular cone bunch type graph substrate, substantially increase the ability that reflects photons arrives LED chip top and bottom, thus make more light reflections to chip top, bottom, considerably increase the effective sunlight that can be fully used, strengthen the light extraction efficiency of graphical sapphire substrate GaN base LED, thus improve the external quantum efficiency of LED.Compare common pattern-free substrate LED, total light flux increases to 2.56 times, and top light flux increases to 2.48 times, and bottom light flux increases to 2.77 times.
(2) the utility model has the light extraction efficiency more excellent than general substrate LED chip, and circular cone bunch adds reflective surface area, has obvious gain effect, be particularly suitable for chip package to bottom bright dipping.
(3) the circular cone bunch type graph substrate technological process in the utility model does not need secondarily etched, comparatively other complex pattern substrates, greatly reduce difficulty of processing.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the LED chip of embodiment 1 of the present utility model.
Fig. 2 is the schematic diagram of the circular cone bunch of embodiment 1 of the present utility model.
Fig. 3 is the arrangement schematic diagram of the circular cone bunch of embodiment 1 of the present utility model.
Fig. 4 is the arrangement schematic diagram of the circular cone bunch of embodiment 2 of the present utility model.
Fig. 5 is the arrangement schematic diagram of the circular cone bunch of embodiment 3 of the present utility model.
Fig. 6 is the arrangement schematic diagram of the circular cone bunch of embodiment 4 of the present utility model.
Embodiment
Below in conjunction with embodiment, the utility model is described in further detail, but execution mode of the present utility model is not limited thereto.
Embodiment 1
Fig. 1 is the schematic diagram of the LED chip of the present embodiment, is made up of the LED graphics-optimized substrate 11 of the circular cone bunch type pattern be arranged in order, N-type GaN layer 12, MQWs quantum well layer 13, P type GaN layer 14.
As shown in Figure 2, the pattern of the substrate of the present embodiment is made up of the circular cone bunch that the multiple shapes being arranged in substrate surface are identical, and arrangement mode is rectangular arranged.As shown in Figure 3, each circular cone bunch is made up of a large circular cone, multiple middle circular cone and multiple conicle; Described multiple middle circular cone is arranged in a circle around large circular cone, circular cone circle in formation; Described multiple conicle is arranged in a circle around middle circular cone circle, forms conicle circle; The height H of each large circular cone lbe 2.0 μm, bottom surface radius R lit is 1.2 μm; The height H of each middle circular cone mbe 1.25 μm, bottom surface radius R mit is 0.5 μm; The height H of each conicle sbe 0.67 μm, bottom surface radius R sit is 0.4 μm; The back gauge d of adjacent circular cone bunch is 3 μm.
Embodiment 2
The LED chip of the present embodiment is by LED graphics-optimized substrate, the N-type GaN layer of the circular cone bunch type pattern be arranged in order, and MQWs quantum well layer, P type GaN layer forms.
As shown in Figure 4, the pattern of the substrate of the present embodiment is made up of the circular cone bunch that the multiple shapes being arranged in substrate surface are identical, and arrangement mode is hexagonal arrangement.Each circular cone bunch is made up of a large circular cone, multiple middle circular cone and multiple conicle; Described multiple middle circular cone is arranged in a circle around large circular cone, circular cone circle in formation; Described multiple conicle is arranged in a circle around middle circular cone circle, forms conicle circle; The height H of each large circular cone lbe 1.0 μm, bottom surface radius R lit is 0.6 μm; The height H of each middle circular cone mbe 0.75 μm, bottom surface radius R mit is 0.25 μm; The height H of each conicle sbe 0.3 μm, bottom surface radius R sit is 0.15 μm; The back gauge d of adjacent circular cone bunch is 1 μm.
Embodiment 3
The present embodiment is except following characteristics, and all the other features and embodiment 1 are together.
The circular cone bunch that multiple shapes of the present embodiment are identical adopts diamond array mode as shown in Figure 5.
Embodiment 4
The present embodiment is except following characteristics, and all the other features and embodiment 1 are together.
The circular cone bunch that multiple shapes of the present embodiment are identical adopts circular arrangement mode as shown in Figure 6.
Test case:
Adopt the graph substrate of optical analysis software TracePro to LED chip of the present utility model to do simulation test, simulation test process is as follows:
(1) substrate builds: the modeling function adopting TracePro to carry realizes the making of substrate, and substrate dimension is 120 μm × 120 μm × 100 μm, in rectangular-shaped.
(2) circular cone bunch design producing: adopt the Plotting Function of Solidworks to realize the making of circular cone bunch pattern: the height H of each large circular cone of circular cone bunch lbe 1.0 ~ 2.0 μm, bottom surface radius is R l0.6 ~ 1.2 μm; The height H of each middle circular cone mbe 0.75 ~ 1.25 μm, bottom surface radius R mit is 0.25 ~ 0.5 μm; The height H of each roundlet sbe 0.3 ~ 0.67 μm, bottom surface radius R sbe 0.15 ~ 0.4 μm, the back gauge d of adjacent circular cone bunch is 1 ~ 4 μm.In hexagonal arrange, or rectangular arrangement, circular arrangement, rhombus arrangement.
(3) epitaxial loayer builds: the modeling function adopting TracePro to carry realizes the making of n-type GaN layer, MQWs quantum well layer, p-type GaN layer, n-type GaN layer is of a size of 120 μm × 120 μm × 4 μm, MQW quantum well layer is of a size of 120 μm × 120 μm × 50nm, and p-type GaN layer is of a size of 120 μm × 120 μm × 3 μm.
(4) target surface builds: the modeling function adopting TracePro to carry realizes the making of six layers of target surface, six layers of target surface are placed in upper and lower, the direction, front, rear, left and right of LED chip respectively, upper and lower target surface is of a size of 120 μm × 120 μm × 3 μm, forward and backward target surface (the long limit of opposite chip) is of a size of 120 μm × 120 μm × 3 μm, and left and right target surface (minor face of opposite chip) is of a size of 120 μm × 120 μm × 3 μm.
(5) n-type GaN layer and graph substrate contact-making surface corresponding pattern build: insert patterned layer that Solidworks sets up on substrate layer, adopt the difference of TracePro to subtract functional realiey n-GaN layer corresponding pattern and build.
(6) setting parameter of each material layer: the refractive index of Sapphire Substrate is 1.67, N-shaped GaN, MQWs quantum well, p-type GaN material refractive index are 2.45, four is all the light of 450nm for wavelength, and temperature is set to 300K, does not consider to absorb the impact with extinction coefficient.
(7) quantum well layer surface source of light setting, it is characterized in that: quantum well layer upper and lower surface respectively arranges a surface source of light attribute, transmitting form is luminous flux, rink corner is distributed as the luminous field pattern of Lambertian, luminous flux is 5000a.u., total light number 3000, minimum light number 10.
(8) ray tracing: utilize software subsidiary clear off system, ray tracing is carried out to the LED chip model of above-mentioned structure, obtains the luminous flux data of top, bottom, side respectively.
The test result of embodiment 1 is as follows:
Top light flux 1827.4a.u., bottom light flux 2477.5a.u., ambient light flux 4304.9a.u., total light flux 7945.94a.u..Compared with pattern-free substrate, the top of circular cone bunch type graph substrate LED chip, bottom and ambient light flux improve 1.48,1.77 and 1.48 times respectively, and its total light flux promotes 1.56 times.
Above-described embodiment is the utility model preferably execution mode; but execution mode of the present utility model is not limited by the examples; change, the modification done under other any does not deviate from Spirit Essence of the present utility model and principle, substitute, combine, simplify; all should be the substitute mode of equivalence, be included within protection range of the present utility model.

Claims (6)

1. a LED graphics-optimized substrate for circular cone bunch type pattern, is characterized in that, the pattern of substrate is made up of the circular cone bunch that the multiple shapes being arranged in substrate surface are identical;
Described circular cone bunch is made up of a large circular cone, multiple middle circular cone and multiple conicle; Described multiple middle circular cone is arranged in a circle around large circular cone, circular cone circle in formation; Described multiple conicle is arranged in a circle around middle circular cone circle, forms conicle circle;
The height H of each large circular cone lbe 1.0 ~ 2.0 μm, bottom surface radius R lit is 0.6 ~ 1.2 μm;
The height H of each middle circular cone mbe 0.75 ~ 1.25 μm, bottom surface radius R mit is 0.25 ~ 0.5 μm;
The height H of each conicle sbe 0.3 ~ 0.67 μm, bottom surface radius R sit is 0.15 ~ 0.4 μm;
The back gauge d of adjacent circular cone bunch is 1 ~ 4 μm.
2. the LED graphics-optimized substrate of circular cone according to claim 1 bunch type pattern, is characterized in that, the circular cone bunch that described multiple shape is identical adopts rectangular arrangement pattern.
3. the LED graphics-optimized substrate of circular cone according to claim 1 bunch type pattern, is characterized in that, the circular cone bunch that described multiple shape is identical adopts hexagonal arrangement mode.
4. the LED graphics-optimized substrate of circular cone according to claim 1 bunch type pattern, is characterized in that, the circular cone bunch that described multiple shape is identical adopts circular arrangement mode.
5. the LED graphics-optimized substrate of circular cone according to claim 1 bunch type pattern, is characterized in that, the circular cone bunch that described multiple shape is identical adopts diamond array mode.
6. a LED chip, is characterized in that, comprises the LED graphics-optimized substrate of the circular cone bunch type pattern as described in any one of Claims 1 to 5.
CN201420740377.6U 2014-11-28 2014-11-28 The LED graphics-optimized substrate of a kind of circular cone bunch type pattern and LED chip Withdrawn - After Issue CN204204898U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104465927A (en) * 2014-11-28 2015-03-25 华南理工大学 Pattern optimized LED substrate with cone cluster type patterns and LED chip

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104465927A (en) * 2014-11-28 2015-03-25 华南理工大学 Pattern optimized LED substrate with cone cluster type patterns and LED chip
CN104465927B (en) * 2014-11-28 2017-08-25 华南理工大学 The LED graphics-optimizeds substrate and LED chip of a kind of circular cone cluster type pattern

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Granted publication date: 20150311

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