CN204167288U - Flat no-lead packages body - Google Patents
Flat no-lead packages body Download PDFInfo
- Publication number
- CN204167288U CN204167288U CN201420478741.6U CN201420478741U CN204167288U CN 204167288 U CN204167288 U CN 204167288U CN 201420478741 U CN201420478741 U CN 201420478741U CN 204167288 U CN204167288 U CN 204167288U
- Authority
- CN
- China
- Prior art keywords
- pin
- chip
- flat
- lead portion
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model is about flat no-lead packages body.According to an embodiment of the present utility model, a flat no-lead packages body has the first relative side and the second side, comprises: a chip, an injection-moulded housing covering this chip, and some pins being respectively in this first side and the second side.Each in this some pin comprises and is shielded in interior lead portion in this injection-moulded housing and bottom surface and exposes to outer lead portion outside this injection-moulded housing, in this some pin, at least both interior lead portion have different planar dimensions, this chip be not at least directly installed on by base wherein there is lead portion in large-size one on.The utility model by the pin of symmetry design change into asymmetrical, thus when chip without base and biased still can ensure that it obtains enough supports of pin, do not have obviously unsettled.Ensure that the quality of packaging body on the one hand, also avoid the restriction of base technique simultaneously.
Description
Technical field
The utility model is about integrated circuit package body, particularly flat no-lead packages body (QFN, Quad FlatNo-lead Package).
Background technology
Chip is normally connected on pin by base by typical integrated circuit package body.With flat no-lead packages body, chip notacoria or gum technique can be used to be installed on base by chip, then use routing technique that chip is connected with corresponding pin.
But along with the development of electronic technology, industry expects that the size of chip is more and more less of the trend adapting to product miniaturization.This just proposes a new difficult problem for the encapsulation of integrated circuit, and main cause is that existing footmaker's skill is difficult to meet the demand of this miniaturization.Therefore, existing packaging technology needs to improve the package requirements that can meet small-size chips further.
Utility model content
An object of the utility model embodiment is to provide an integrated circuit package body, and particularly flat no-lead packages body does not use base to install chip, thus avoids the process technology limit of base but can not affect the performance of integrated circuit package body.
An embodiment of the present utility model provides a flat no-lead packages body, has the first relative side and the second side.This flat no-lead packages body comprises: a chip, an injection-moulded housing covering this chip, and some pins being respectively in this first side and the second side.Each in this some pin comprises and is shielded in interior lead portion in this injection-moulded housing and bottom surface and exposes to outer lead portion outside this injection-moulded housing, in this some pin, at least both interior lead portion have different planar dimensions, this chip be not at least directly installed on by base wherein there is lead portion in large-size one on.
According to another embodiment of the present utility model, in one embodiment, the size of this flat no-lead packages body is less than 2mm × 2mm.This chip rotates an angle relative to the horizontal-extending direction of this some pin to place.This chip is not positioned at the center of this flat no-lead packages body.The outer lead portion of each in this some pin is measure-alike.The interior lead portion of this some pin is half-etching structure.In this some pin, at least both comprise two the relative pins laying respectively at this first side and the second side.The spacing of these two relative pins is not less than 0.07mm.This chip be only installed on be arranged in this first side and the second side one pin on.In another embodiment, this chip is installed on this some pins all.
Flat no-lead packages body of the present utility model compared to traditional structure, by the pin of symmetry design change into asymmetrical, thus when chip without base and biased still can ensure that it obtains enough supports of pin, do not have obviously unsettled.Ensure that the quality of packaging body on the one hand, also avoid the restriction of base technique simultaneously.
Accompanying drawing explanation
It is the structural profile schematic diagram of the integrated circuit package body according to the utility model one embodiment shown in Fig. 1.
Shown in Fig. 2 be in Fig. 1 integrated circuit package body look up structural representation, illustrate only the layout of its chips and pin for the purpose of simple.
Be look up structural representation according to the integrated circuit package body of another embodiment of the utility model shown in Fig. 3, for the purpose of simple, illustrate only the layout of its chips and pin.
Be look up structural representation according to the integrated circuit package body of the another embodiment of the utility model shown in Fig. 4, for the purpose of simple, illustrate only the layout of its chips and pin.
Be look up structural representation according to the integrated circuit package body of other embodiment of the utility model shown in Fig. 5, for the purpose of simple, illustrate only the layout of its chips and pin.
Embodiment
For better understanding spirit of the present utility model, below in conjunction with part preferred embodiment of the present utility model, it is described further.
For small size as the chip being less than 2mm × 2mm, be limited to existing base technique, the packaged type without base can be adopted.That is, chip is directly installed on pin.But due to the multifactor consideration of design, chip sometimes can not be in the center of whole packaging body but can be partial to side.So, the symmetric arrays pin of traditionally design rule design may occur that a row pin all cannot touch the situation of chip, and it is unsettled that corresponding chip there will be large area.Because chip large area is unsettled, when routing operation, causing due to chip bearing instability cannot routing.
Embodiment of the present utility model can avoid above-mentioned technical problem.According to an embodiment of the present utility model, a flat no-lead packages body, has the first relative side and the second side, comprises: the chip of, an injection-moulded housing covering this chip, and is respectively in some pins of this first side and the second side.Each wherein in this some pin comprises and is shielded in interior lead portion in this injection-moulded housing and bottom surface and exposes to outer lead portion outside this injection-moulded housing, in this some pin, at least both interior lead portion have different planar dimensions, this chip be not at least directly installed on by base wherein there is lead portion in large-size one on.
It is the structural profile schematic diagram of the integrated circuit package body 10 according to the utility model one embodiment shown in Fig. 1.
Shown in Fig. 2 be in Fig. 1 integrated circuit package body 10 look up structural representation, illustrate only the layout of its chips 12 and pin 14 for the purpose of simple.
Shown in composition graphs 1,2, this integrated circuit package body 10 is flat no-lead packages bodies, comprises chip 12, covers the injection-moulded housing 16 of this chip 12, and four pins 14.This flat no-lead packages body 10 has the first relative side 100 and the second side 102.These four pins 14 lay respectively at the first side 100 and the second side 102 of this chip 12.Each pin 14 comprises and is shielded in interior lead portion 140 in injection-moulded housing 16 and bottom surface and exposes to outer lead portion 142 outside this injection-moulded housing 16.This interior lead portion 140 has thinner thickness relative to outer lead portion 142, interior lead portion 140 is formed by etch process, namely in, lead portion 140 is half-etching structure, and in encapsulation process, interior lead portion 140 will be completely enclosed within injection moulding colloid, and the bottom surface of outer lead portion 142 exposes the bottom surface of integrated circuit package body 10.Pin 14 is for supporting this chip 12 and realizing being electrically connected with this chip 12 by electric connection line.In the present embodiment, although the outer lead portion 142 of these four pins 14 has same size (in other embodiments, outer lead portion 142 also may have different size), but interior lead portion 140 is also incomplete same, a pair respective pins 14 being positioned at relative both sides has a longer lead portion 140 and a shorter lead portion 140 respectively.The spacing of this two relative pin is not less than 0.07mm, preferably desirable 0.1mm.In the present embodiment, the pin 14 with longer interior lead portion 140 is interspersed in the first side 100 and the second side 102.This chip 12 is not positioned at the center of integrated circuit package body 10, but be not directly installed on two pins 14 with longer interior lead portion 140 by base, and be offset to side (being the second side in the present embodiment) and have on the pin 14 of shorter interior lead portion 140.So can ensure, most of area of chip 12 all can contact with pin 14, and there will not be the obvious overhanging portion at edge, and then chip 12 there will not be downward distortion when routing operation.
Be look up structural representation according to the integrated circuit package body 10 of another embodiment of the utility model shown in Fig. 3, for the purpose of simple, illustrate only the layout of its chips 12 and pin 14.
Be similar to embodiment illustrated in fig. 2, this integrated circuit package body 10 is flat no-lead packages bodies with four pins 14.The interior lead portion 140 of these four pins 14 is also incomplete same, and a pair respective pins 14 being positioned at relative both sides has a longer lead portion 140 and a shorter lead portion 140 respectively.In the present embodiment, the pin 14 with longer interior lead portion 140 is interspersed in the first side 100 and the second side 102.Unlike, this chip 12 rotates an angle relative to the horizontal-extending direction of these four pins 14 place thus all contact with lead portion 140 in four pins 14, avoids obviously unsettled marginal portion.
Be look up structural representation according to the integrated circuit package body 10 of the another embodiment of the utility model shown in Fig. 4, for the purpose of simple, illustrate only the layout of its chips 12 and pin 14.
As shown in Figure 4, this integrated circuit package body 10 is flat no-lead packages bodies with six pins 14, and each pin 14 is respectively in the first side 100 of this integrated circuit package body 10 and the second relative side 102.The interior lead portion 140 of these six pins 14 is also incomplete same, and a pair respective pins 14 being positioned at relative both sides has a longer lead portion 140 and a shorter lead portion 140 respectively, and the pin 14 with longer interior lead portion 140 is all positioned at the first side 100.This chip 12 is offset to the second side 102 and places, and thus can contact shorter interior lead portion 140 and longer interior lead portion 140 simultaneously and obtain enough supports.
Be look up structural representation according to the integrated circuit package body 10 of the another embodiment of the utility model shown in Fig. 5, for the purpose of simple, illustrate only the layout of its chips 12 and pin 14.
As shown in Figure 5, this integrated circuit package body 10 is flat no-lead packages bodies with eight pins 14, and each pin 14 is respectively in the first side 100 of this integrated circuit package body 10 and the second relative side 102.The interior lead portion 140 of these eight pins 14 is also incomplete same, and a pair respective pins 14 being positioned at relative both sides has a longer lead portion 140 and a shorter lead portion 140 respectively.The pin 14 with longer interior lead portion 140 can be positioned at the first side 100 or the second side 102, and every a pair relative pin 14 can have different dimension combination and be not limited to rule arrangement.This chip 12 can be offset to any side and place, and can avoid obvious Hanging sectionally equally and obtain enough supports.
Above-described embodiment is only and essence of the present utility model is described, those skilled in the art should know that concrete number of pins and arrangement can have a lot of change, and are not limited to above enumerating.And this two couple's two row's pins 14 arrange easily extensible to the integrated circuit package body 10 with four row's pins 14, other two row's terminals are suitable for the design rule of above-mentioned two rows completely.
The utility model is by having different planar dimensions by relative two row's pins 14 at least two corresponding pins 14 of being improved to opposite side by the identical symmetric design of interior lead portion 140, as longer in one or wider and another one is shorter or narrower; Or there is multiple pin to have longer interior lead portion 140, and be also of different sizes (length or width) between the plurality of longer interior lead portion 140.As long as chip 12 can be made can to obtain the support of most of pin 14 and avoid obvious hanging part.
Technology contents of the present utility model and technical characterstic disclose as above, but those of ordinary skill in the art still may do all replacement and the modification that do not deviate from the utility model spirit based on teaching of the present utility model and announcement.Therefore, protection range of the present utility model should be not limited to the content that embodiment discloses, and should comprise various do not deviate from replacement of the present utility model and modification, and is contained by present patent application claims.
Claims (10)
1. a flat no-lead packages body, has the first relative side and the second side; Comprise:
One chip;
One injection-moulded housing, covers this chip;
Some pins, are respectively in this first side and this second side;
The each that it is characterized in that in this some pin comprises and is shielded in interior lead portion in this injection-moulded housing and bottom surface and exposes to outer lead portion outside this injection-moulded housing, in this some pin, at least both interior lead portion have different planar dimensions, this chip be not at least directly installed on by base wherein there is lead portion in large-size one on.
2. flat no-lead packages body as claimed in claim 1, is characterized in that this flat no-lead packages body size is less than 2mm × 2mm.
3. flat no-lead packages body as claimed in claim 1, is characterized in that this chip rotates an angle relative to the horizontal-extending direction of this some pin to place.
4. flat no-lead packages body as claimed in claim 1, is characterized in that this chip is not positioned at the center of this flat no-lead packages body.
5. flat no-lead packages body as claimed in claim 1, is characterized in that the outer lead portion of each in this some pin is measure-alike.
6. flat no-lead packages body as claimed in claim 1, is characterized in that the interior lead portion of this some pin is half-etching structure.
7. flat no-lead packages body as claimed in claim 1, to is characterized in that in this some pin that at least both comprise two the relative pins laying respectively at this first side and the second side.
8. flat no-lead packages body as claimed in claim 7, is characterized in that the spacing of these two relative pins is not less than 0.07mm.
9. flat no-lead packages body as claimed in claim 1, it is characterized in that this chip be only installed on be arranged in this first side and the second side one pin on.
10. flat no-lead packages body as claimed in claim 1, is characterized in that this chip is installed on this some pins all.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420478741.6U CN204167288U (en) | 2014-08-22 | 2014-08-22 | Flat no-lead packages body |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420478741.6U CN204167288U (en) | 2014-08-22 | 2014-08-22 | Flat no-lead packages body |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204167288U true CN204167288U (en) | 2015-02-18 |
Family
ID=52540948
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420478741.6U Active CN204167288U (en) | 2014-08-22 | 2014-08-22 | Flat no-lead packages body |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204167288U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104157620A (en) * | 2014-08-22 | 2014-11-19 | 苏州日月新半导体有限公司 | Flat pin-free packaging body |
-
2014
- 2014-08-22 CN CN201420478741.6U patent/CN204167288U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104157620A (en) * | 2014-08-22 | 2014-11-19 | 苏州日月新半导体有限公司 | Flat pin-free packaging body |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI528632B (en) | Electronic package and manufacturing method thereof | |
| CN202888164U (en) | Novel TO (Triode)-series matrix type lead frame | |
| CN204167288U (en) | Flat no-lead packages body | |
| US20150137337A1 (en) | Semiconductor package and lead frame | |
| KR20120056624A (en) | Semiconductor package | |
| KR20090060148A (en) | Integrated circuit package-in-package system | |
| US7812431B2 (en) | Leadframe with die pad and leads corresponding thereto | |
| CN203733783U (en) | Lead frame | |
| CN202443957U (en) | Chip package module and mother board | |
| CN103000794B (en) | LED package structure | |
| CN104157620A (en) | Flat pin-free packaging body | |
| CN211125694U (en) | L ED packaging support and packaging structure | |
| KR20150053916A (en) | Dual row quad flat no-lead semiconductor package | |
| CN103354226B (en) | Stack packaged device | |
| CN203367269U (en) | Lead frame | |
| CN202434503U (en) | DIP10 integrated circuit device and lead frame, and lead frame matrix | |
| TWI424525B (en) | Carrier and carrier assembly for chip packages | |
| CN205984972U (en) | Lead frame structure | |
| CN204271072U (en) | Lead-frame packages structure | |
| CN202363446U (en) | Chip packaging structure | |
| CN209880599U (en) | Lead frame | |
| CN205159315U (en) | Lead frame strip | |
| CN108615715A (en) | Semiconductor package and lead frame strip used by same | |
| CN211670207U (en) | LED packaging frame capable of improving space utilization rate | |
| CN202917478U (en) | A packaging structure of single-row vertical pins |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 215101 No. 188, Suhong West Road, Suzhou Industrial Park, Suzhou City, Jiangsu Province Patentee after: Riyuexin semiconductor (Suzhou) Co.,Ltd. Address before: No. 188, Suhong West Road, Suzhou Industrial Park, Suzhou, Jiangsu Province Patentee before: SUZHOU ASEN SEMICONDUCTORS Co.,Ltd. |
|
| CP03 | Change of name, title or address |