CN104157620A - Flat pin-free packaging body - Google Patents
Flat pin-free packaging body Download PDFInfo
- Publication number
- CN104157620A CN104157620A CN201410417894.4A CN201410417894A CN104157620A CN 104157620 A CN104157620 A CN 104157620A CN 201410417894 A CN201410417894 A CN 201410417894A CN 104157620 A CN104157620 A CN 104157620A
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- CN
- China
- Prior art keywords
- pin
- pins
- chip
- packaging body
- flat non
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention relates to a flat pin-free packaging body. According to one embodiment of the invention, the flat pin-free packaging body is provided with a first side and a second side which are opposite and comprises a chip, an injection molding housing which shields the chip, and a plurality of pins arranged at the first side and the second side. Each of the plurality of pins comprises an inner pin portion which is shielded in the injection molding housing and an outer pin portion whose bottom surface is exposed outside the injection molding housing. The inner pin portions of at least two of the plurality of pins have different planar dimensions, and the chip is at least directly installed on the one whose inner pin portion has larger dimensions without the base. According to the invention, a symmetrical pin design is changed to an asymmetric design, such that under the condition that the chip is free from the base and is biased, it can still be ensured that the chip can get sufficient support from the pins and is not obviously suspended, thus on one hand, the quality of the packaging body is guaranteed, and on the other hand, restrictions on a base process are avoided at the same time.
Description
Technical field
The invention relates to integrated circuit package body, particularly flat non-pin packaging body (QFN, Quad Flat No-lead Package).
Background technology
Typical integrated circuit package body is normally connected to chip on pin by base.With flat non-pin packaging body, can use chip notacoria or gum technique that chip is installed on base, then use routing technique that chip is connected with corresponding pin.
Yet along with the development of electronic technology, the size of industry expectation chip is more and more less of to adapt to the trend of product miniaturization.This is with regard to for the encapsulation of integrated circuit has proposed a new difficult problem, and main cause is that existing footmaker's skill is difficult to meet the demand of this miniaturization.Therefore, existing packaging technology needs further improvement can meet the package requirements of small-size chips.
Summary of the invention
An object of the embodiment of the present invention is to provide an integrated circuit package body, and particularly flat non-pin packaging body, is not used base to install chip, thereby avoids the process technology limit of base but can not affect the performance of integrated circuit package body.
One embodiment of the invention provide a flat non-pin packaging body, have the first relative side and the second side.This flat non-pin packaging body comprises: a chip, one covers the injection-moulded housing of this chip, and some pins that is respectively in this first side and the second side.Each in these some pins comprises the interior pin portion that is shielded in this injection-moulded housing and bottom surface and exposes to the outer pin portion outside this injection-moulded housing, in these some pins, at least there is different planar dimensions in both interior pin portions, and this chip is not at least directly installed in the one wherein with pin portion in large-size by base.
According to another embodiment of the present invention, in one embodiment, the size of this flat non-pin packaging body is less than 2mm * 2mm.This chip is to place with respect to horizontal-extending direction rotation one angle of these some pins.This chip is not positioned at the center of this flat non-pin packaging body.The outer pin portion of each in these some pins is measure-alike.The interior pin portion of these some pins etches partially structure.In these some pins, at least both comprise two relative pins that lay respectively at this first side and the second side.The spacing of these two relative pins is not less than 0.07mm.This chip is only installed on the pin that is arranged in this first side and the second side one.In another embodiment, this chip is installed on all these some pins.
Flat non-pin packaging body of the present invention is compared to traditional structure, symmetrical pin design is changed into asymmetrical, thereby at chip, still can guarantee that it obtains enough supports of pin, does not have obviously unsettled without base and biasing in the situation that.Guarantee on the one hand the quality of packaging body, also avoided the restriction of base technique simultaneously.
Accompanying drawing explanation
It shown in Fig. 1, is the structural profile schematic diagram of integrated circuit package body according to an embodiment of the invention.
Shown in Fig. 2, be in Fig. 1 integrated circuit package body look up structural representation, only show the layout of its chips and pin for the purpose of simple.
Shown in Fig. 3, be according to another embodiment of the present invention integrated circuit package body look up structural representation, only show the layout of its chips and pin for the purpose of simple.
Shown in Fig. 4, be the structural representation of looking up according to the integrated circuit package body of further embodiment of this invention, only show the layout of its chips and pin for the purpose of simple.
Shown in Fig. 5, be other embodiment according to the present invention integrated circuit package body look up structural representation, only show the layout of its chips and pin for the purpose of simple.
Embodiment
Spirit for a better understanding of the present invention, is described further it below in conjunction with part preferred embodiment of the present invention.
For small size, as being less than for the chip of 2mm * 2mm, be limited to existing base technique, can adopt the packaged type without base.That is, chip is directly installed on pin.But due to the multifactor consideration of design, the center that chip sometimes can not be in whole packaging body but can be partial to a side.So, according to the symmetric arrays pin of traditional design Design with Rule, may occur that a row pin all cannot touch the situation of chip, corresponding chip there will be large area unsettled.Because chip large area is unsettled, when routing operation, because chip bearing is unstable, causing cannot routing.
Embodiments of the invention can be avoided above-mentioned technical problem.According to one embodiment of the invention, a flat non-pin packaging body, has the first relative side and the second side, comprises: one chip, one covers the injection-moulded housing of this chip, and is respectively in some pins of this first side and the second side.Wherein each in these some pins comprises the interior pin portion that is shielded in this injection-moulded housing and bottom surface and exposes to the outer pin portion outside this injection-moulded housing, in these some pins, at least there is different planar dimensions in both interior pin portions, and this chip is not at least directly installed in the one wherein with pin portion in large-size by base.
It shown in Fig. 1, is the structural profile schematic diagram of integrated circuit package body 10 according to an embodiment of the invention.
Shown in Fig. 2, be in Fig. 1 integrated circuit package body 10 look up structural representation, only show the layout of its chips 12 and pin 14 for the purpose of simple.
Shown in Fig. 1,2, this integrated circuit package body 10 is flat non-pin packaging bodies, comprise chip 12, cover the injection-moulded housing 16 of this chip 12, and four pins 14.This flat non-pin packaging body 10 has the first relative side 100 and the second side 102.These four pins 14 lay respectively at the first side 100 and second side 102 of this chip 12.Each pin 14 comprises the interior pin portion 140 that is shielded in injection-moulded housing 16 and bottom surface and exposes to the outer pin portion 142 outside this injection-moulded housing 16.This interior pin portion 140 has thinner thickness with respect to outer pin portion 142, interior pin portion 140 can form by etch process, in, pin portion 140 is for etching partially structure, and in encapsulation process, interior pin portion 140 will be completely enclosed within injection moulding colloid, and the bottom surface of outer pin portion 142 exposes the bottom surface of integrated circuit package body 10.Pin 14 is for supporting this chip 12 and being realized and being electrically connected to this chip 12 by electric connection line.In the present embodiment, although the outer pin portion 142 of these four pins 14 has same size (in other embodiments, outer pin portion 142 also may have different size), but interior pin portion 140 is also incomplete same, a pair of respective pins 14 that is positioned at relative both sides has respectively long pin portion 140 and a shorter pin portion 140.The spacing of these two relative pins is not less than 0.07mm, preferably desirable 0.1mm.In the present embodiment, there is the pin 14 of the interior pin of length portion 140 and be interspersed in the first side 100 and the second side 102.This chip 12 is not positioned at integrated circuit package body 10 center, but not by base be directly installed on two have long on the pin 14 of pin portion 140, and be offset on the pin 14 that a side (being the second side in the present embodiment) has shorter interior pin portion 140.So can guarantee, most of area of chip 12 all can contact with pin 14, and there will not be the obvious overhanging portion at edge, and then chip 12 there will not be downward distortion when routing operation.
Shown in Fig. 3, be according to another embodiment of the present invention integrated circuit package body 10 look up structural representation, only show the layout of its chips 12 and pin 14 for the purpose of simple.
Be similar to embodiment illustrated in fig. 2ly, this integrated circuit package body 10 is one to have the flat non-pin packaging body of four pins 14.The interior pin portion 140 of these four pins 14 is also incomplete same, and a pair of respective pins 14 that is positioned at relative both sides has respectively long pin portion 140 and a shorter pin portion 140.In the present embodiment, there is the pin 14 of the interior pin of length portion 140 and be interspersed in the first side 100 and the second side 102.Different, thus this chip 12 is to place with the interior pin portion 140 of four pins 14 and all contact with respect to horizontal-extending direction rotation one angle of these four pins 14, has avoided obvious unsettled marginal portion.
Shown in Fig. 4, be the structural representation of looking up according to the integrated circuit package body 10 of further embodiment of this invention, only show the layout of its chips 12 and pin 14 for the purpose of simple.
As shown in Figure 4, this integrated circuit package body 10 is one to have the flat non-pin packaging body of six pins 14, and each pin 14 is respectively in the first side 100 of this integrated circuit package body 10 and the second relative side 102.The interior pin portion 140 of these six pins 14 is also incomplete same, and a pair of respective pins 14 that is positioned at relative both sides has respectively long pin portion 140 and a shorter pin portion 140, and have long in the pin 14 of pin portion 140 be all positioned at the first side 100.This chip 12 is offset to the second side 102 and places, thereby can contact compared with short interior pin portion 140 simultaneously and obtain enough supports compared with pin portion 140 in long.
Shown in Fig. 5, be the structural representation of looking up according to the integrated circuit package body 10 of further embodiment of this invention, only show the layout of its chips 12 and pin 14 for the purpose of simple.
As shown in Figure 5, this integrated circuit package body 10 is one to have the flat non-pin packaging body of eight pins 14, and each pin 14 is respectively in the first side 100 of this integrated circuit package body 10 and the second relative side 102.The interior pin portion 140 of these eight pins 14 is also incomplete same, and a pair of respective pins 14 that is positioned at relative both sides has respectively long pin portion 140 and a shorter pin portion 140.Have long in the pin 14 of pin portion 140 can be positioned at the first side 100 or the second side 102, and every a pair of relative pin 14 can have different size combinations and is not limited to rule and arranges.This chip 12 can be offset to any one and be sidelong and put, and can avoid obvious Hanging sectionally equally and obtain enough supports.
Above-described embodiment is only explanation essence of the present invention, and those skilled in the art should know concrete number of pins and arrange can a lot of variations, and is not limited to above enumerating.And two row's pins 14 of this two couple arrange and can extend to the integrated circuit package body 10 with four row's pins 14, completely applicable above-mentioned two rows' of other two row's terminal design rule.
The present invention has different planar dimensions by least two corresponding pins 14 that relative two row's pins 14 are improved to opposite side by interior pin portion 140 identical symmetric designs, if one is compared with long or compared with wide and another one is shorter or narrower; Or there are a plurality of pins to there is long interior pin portion 140, and are also of different sizes (length or width) between the plurality of long interior pin portion 140.As long as can make chip 12 can obtain the support of most of pins 14, avoid obvious hanging part.
Technology contents of the present invention and technical characterstic disclose as above, yet those of ordinary skill in the art still may be based on teaching of the present invention and announcements and done all replacement and modifications that does not deviate from spirit of the present invention.Therefore, protection scope of the present invention should be not limited to the content that embodiment discloses, and should comprise various do not deviate from replacement of the present invention and modifications, and is contained by present patent application claims.
Claims (10)
1. a flat non-pin packaging body, has the first relative side and the second side; Comprise:
One chip;
One injection-moulded housing, covers this chip;
Some pins, are respectively in this first side and this second side;
Wherein each in these some pins comprises the interior pin portion that is shielded in this injection-moulded housing and bottom surface and exposes to the outer pin portion outside this injection-moulded housing, in these some pins, at least there is different planar dimensions in both interior pin portions, and this chip is not at least directly installed in the one wherein with pin portion in large-size by base.
2. flat non-pin packaging body as claimed in claim 1, its size is less than 2mm * 2mm.
3. flat non-pin packaging body as claimed in claim 1, wherein this chip is to place with respect to horizontal-extending direction rotation one angle of these some pins.
4. flat non-pin packaging body as claimed in claim 1, wherein this chip is not positioned at the center of this flat non-pin packaging body.
5. flat non-pin packaging body as claimed in claim 1, wherein the outer pin portion of each in these some pins is measure-alike.
6. flat non-pin packaging body as claimed in claim 1, wherein the interior pin portion of these some pins etches partially structure.
7. flat non-pin packaging body as claimed in claim 1, wherein in these some pins, at least both comprise two relative pins that lay respectively at this first side and the second side.
8. flat non-pin packaging body as claimed in claim 7, wherein the spacing of these two relative pins is not less than 0.07mm.
9. flat non-pin packaging body as claimed in claim 1, wherein this chip is only installed on the pin that is arranged in this first side and the second side one.
10. flat non-pin packaging body as claimed in claim 1, wherein this chip is installed on all these some pins.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910327120.5A CN110071078A (en) | 2014-08-22 | 2014-08-22 | Flat no-lead packages body |
| CN201410417894.4A CN104157620A (en) | 2014-08-22 | 2014-08-22 | Flat pin-free packaging body |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410417894.4A CN104157620A (en) | 2014-08-22 | 2014-08-22 | Flat pin-free packaging body |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910327120.5A Division CN110071078A (en) | 2014-08-22 | 2014-08-22 | Flat no-lead packages body |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104157620A true CN104157620A (en) | 2014-11-19 |
Family
ID=51883093
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910327120.5A Pending CN110071078A (en) | 2014-08-22 | 2014-08-22 | Flat no-lead packages body |
| CN201410417894.4A Pending CN104157620A (en) | 2014-08-22 | 2014-08-22 | Flat pin-free packaging body |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910327120.5A Pending CN110071078A (en) | 2014-08-22 | 2014-08-22 | Flat no-lead packages body |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN110071078A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1630945A (en) * | 2000-12-14 | 2005-06-22 | 国际整流器公司 | Semiconductor device package and lead frame with die overhanging lead frame pad |
| CN201262956Y (en) * | 2008-09-04 | 2009-06-24 | 浙江华越芯装电子股份有限公司 | High-power multi-chip packaging structure of integrated circuit |
| CN201417765Y (en) * | 2009-04-01 | 2010-03-03 | 苏州固锝电子股份有限公司 | Base island free semi-conductor chip package structure |
| US20130221507A1 (en) * | 2012-02-29 | 2013-08-29 | Zhiqiang Niu | Aluminum alloy lead-frame and its use in fabrication of power semiconductor package |
| CN204167288U (en) * | 2014-08-22 | 2015-02-18 | 苏州日月新半导体有限公司 | Flat no-lead packages body |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201838575U (en) * | 2010-07-12 | 2011-05-18 | 无锡华润安盛科技有限公司 | Flipchip thin-small outline packaged lead frame and package structure thereof |
| KR20120081459A (en) * | 2011-01-11 | 2012-07-19 | 삼성전자주식회사 | Semiconductor packages having lead frames |
| CN202196776U (en) * | 2011-06-13 | 2012-04-18 | 西安天胜电子有限公司 | Flat carrier-free leadless pin exposed packaging part |
-
2014
- 2014-08-22 CN CN201910327120.5A patent/CN110071078A/en active Pending
- 2014-08-22 CN CN201410417894.4A patent/CN104157620A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1630945A (en) * | 2000-12-14 | 2005-06-22 | 国际整流器公司 | Semiconductor device package and lead frame with die overhanging lead frame pad |
| CN201262956Y (en) * | 2008-09-04 | 2009-06-24 | 浙江华越芯装电子股份有限公司 | High-power multi-chip packaging structure of integrated circuit |
| CN201417765Y (en) * | 2009-04-01 | 2010-03-03 | 苏州固锝电子股份有限公司 | Base island free semi-conductor chip package structure |
| US20130221507A1 (en) * | 2012-02-29 | 2013-08-29 | Zhiqiang Niu | Aluminum alloy lead-frame and its use in fabrication of power semiconductor package |
| CN204167288U (en) * | 2014-08-22 | 2015-02-18 | 苏州日月新半导体有限公司 | Flat no-lead packages body |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110071078A (en) | 2019-07-30 |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20141119 |