CN204145515U - The chen chaos switched system circuit that a kind of fractional-order is different - Google Patents

Abstract

The utility model provides a chaotic switching system circuit with different fractional orders. The operational amplifier U1, operational amplifier U2, resistors and capacitors are used to form an inverting adder and fractional inverting integrators of different orders. The multiplier U3 is used And multiplier U4 realizes multiplication, utilizes analog switch U5 to realize the selection output of analog signal, described operational amplifier U1 and operational amplifier U2 adopt LF347D, described multiplier U3 and multiplier U4 adopt AD633JN, described analog switch U5 adopts ADG888 , the operational amplifier U1 is connected to the multiplier U3, the multiplier U4 and the analog switch U5, the operational amplifier U2 is connected to the multiplier U3 and the analog switch U5, the multiplier U3 is connected to the operational amplifier U1, and the multiplier U4 is connected to the operation Amplifier U2, the analog switch U5 is connected to operational amplifier U1 and operational amplifier U2, a novel switching circuit of a novel chaotic system is proposed, which provides a method for increasing the switching type of chaotic system and the application of this chaotic system in engineering practice new ideas.

Description

A chen chaotic switching system circuit with different fractional orders

technical field

The utility model relates to a chaotic system and circuit realization, in particular to a chaotic switching system circuit with different fractional orders. the

Background technique

At present, the existing circuits for switching chaotic systems mainly include the switching between different linear items or nonlinear items in the chaotic system, and the fractional order form based on these two switching modes. The switching circuit has not been proposed yet. The utility model proposes a classical chen chaotic switching circuit with different fractional orders. The present invention proposes a new switching circuit of a new type of chaotic system, which is helpful for increasing the switching type of the chaotic system and this The application of chaotic system to engineering practice provides a new way of thinking. the

Contents of the invention

The technical problem to be solved by the utility model is to provide a classical chen chaotic switching circuit with different fractional orders. The utility model adopts the following technical means to achieve the purpose of the invention:

A kind of chen chaotic switching system circuit with different fractional orders is characterized in that, comprising the following steps:

(1) The equation of chen chaotic system i is:

(2) The equation of the 0.9-order chen chaotic system ii is:

(3) The equation of the 0.1-order chen chaotic system iii is:

(4) Construct switching function q=f(x), where the expression iv of f(x) is:

$\mathrm{<span\; class="notranslate">\; q</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; f</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\left\{\begin{array}{cc}\mathrm{<span\; class="notranslate">\; 0.9</span>}& \mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; ></span>\mathrm{<span\; class="notranslate">\; 0</span>}\\ \mathrm{<span\; class="notranslate">\; 0.1</span>}& \mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; \&le;</span>\mathrm{<span\; class="notranslate">\; 0</span>}\end{array}\right.<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; iv</span>}$

(5) A chen chaotic switching system v with different fractional orders constructed from ii, iii and iv is:

(6) Construct an analog circuit system according to the chen chaotic switching system v with different fractional orders, use the operational amplifier U1, operational amplifier U2, resistors and capacitors to form an inverting adder and fractional inverting integrators of different orders, and use multiplication The multiplier U3 and the multiplier U4 realize the multiplication operation, utilize the analog switch U5 to realize the selective output of the analog signal, the operational amplifier U1 and the operational amplifier U2 adopt LF347D, the multiplier U3 and the multiplier U4 adopt AD633JN, and the analog switch U5 Adopt ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4 and analog switch U5, described operational amplifier U2 connects multiplier U3 and analog switch U5, described multiplier U3 connects operational amplifier U1, described multiplier U4 Connect the operational amplifier U2, the analog switch U5 connects the operational amplifier U1 and the operational amplifier U2;

The first pin of the operational amplifier U1 is connected to the second pin of the operational amplifier U1 through a resistor R3, and connected to the sixth pin of the operational amplifier U1 through a resistor R8, and the third, fifth, and tenth pins of the operational amplifier U1 are , Pin 12 is grounded, pin 4 is connected to VCC, pin 11 is connected to VEE, pin 6 of operational amplifier U1 is connected in parallel with resistor Ry11 and capacitor Cy11, connected in parallel with resistor Ry12 and capacitor Cy12, and then connected with resistor Ry13 After connecting in parallel with the capacitor Cy13, connect the 7th pin of the analog switch U5, through the parallel connection of the resistor Ry21 and the capacitor Cy21, connect the parallel connection of the resistor Ry22 and the capacitor Cy22, then connect the parallel connection of the resistor Ry23 and the capacitor Cy23, and then connect the analog The 5th pin of the switch U5, the 7th pin of the operational amplifier U1 is connected to the 13th pin of the operational amplifier U1 through the resistor R2, the 2nd pin of the operational amplifier U1 is connected through the resistor R5, and the 3rd pin of the multiplier U4 pin, the 8th pin of the operational amplifier U1 is connected to the 9th pin of the operational amplifier U1 through the resistor R6, the 6th pin of the operational amplifier U1 is connected through the resistor R4, the 2nd pin of the operational amplifier U2 is connected to the multiplier U3 The 1st pin of the multiplier U4 is connected to the 1st pin of the multiplier U4, and the 9th pin of the operational amplifier U1 is connected to the parallel connection of the resistor Rx11 and the capacitor Cx11, connected to the parallel connection of the resistor Rx12 and the capacitor Cx12, and then connected to the resistor Rx13 and the capacitor Cx13 After connecting in parallel, connect the second pin of the analog switch U5, through the parallel connection of the resistor Rx21 and the capacitor Cx21, connect the parallel connection of the resistor Rx22 and the capacitor Cx22, then connect the parallel connection of the resistor Rx23 and the capacitor Cx23, and then connect the first pin of the analog switch U5 4 pins, the 14th pin of the operational amplifier U1 is connected to the 13th pin of the operational amplifier U1 through the resistor R1, and the 9th pin of the operational amplifier U1 is connected through the resistor R7;

The 6th and 7th pins of the operational amplifier U2 are suspended, the 3rd, 5th, 10th, and 12th pins of the operational amplifier U2 are grounded, the 4th pin is connected to VCC, the 11th pin is connected to VEE, and the 11th pin of the operational amplifier U2 is connected to VEE. The first pin is connected to the ground through the series connection of resistors R14 and R15, connected to the 8th and 9th pins of the analog switch U5 through R14, the 8th pin of the operational amplifier U2 is connected to the 9th pin of the operational amplifier U2 through the resistor R12, and then multiplied The 3rd pin of the amplifier U3, the 9th pin of the operational amplifier U2 is connected in parallel with the resistor Rz11 and the capacitor Cz11, connected in parallel with the resistor Rz12 and the capacitor Cz12, then connected in parallel with the resistor Rz13 and the capacitor Cz13, and then connected with the analog switch U5 The 10th pin, through the parallel connection of resistor Rz21 and capacitor Cz21, the parallel connection of resistor Rz22 and capacitor Cz22, and then the parallel connection of resistor Rz23 and capacitor Cz23, and then connect the 12th pin of analog switch U5, the operational amplifier U2 The 14th pin is connected to the 13th pin of the operational amplifier U2 through the resistor R11, and connected to the 9th pin of the operational amplifier U2 through the resistor R13;

The first pin of the multiplier U3 is connected to the eighth pin of the operational amplifier U1, the third pin is connected to the eighth pin of the operational amplifier U2, the second, fourth, and sixth pins are all grounded, and the fifth pin is connected to the eighth pin of the operational amplifier U2. VEE, the 7th pin is connected to the 6th pin of the operational amplifier U1 through the resistor R9, and the 8th pin is connected to VCC;

The first pin of the multiplier U4 is connected to the 8th pin of the operational amplifier U1, the 3rd pin is connected to the 7th pin of the operational amplifier U1, the 2nd, 4th and 6th pins are all grounded, and the 5th pin is connected to the VEE, the 7th pin is connected to the 13th pin of the operational amplifier U2 through the resistor R10, and the 8th pin is connected to VCC;

The first pin of the analog switch U5 is connected to VCC, the 16th pin is grounded, the 13th, 14th and 15th pins are suspended, the 3rd pin is connected to the 8th pin of the operational amplifier U1, and the 6th pin is connected to the operational amplifier The 7th pin of U1 and the 11th pin are connected to the 8th pin of the operational amplifier U2. the

The beneficial effect of the utility model is that a novel switching circuit of a new chaotic system is proposed, which provides a new idea for increasing the switching types of the chaotic system and applying the chaotic system to engineering practice. the

Description of drawings

Fig. 1a, Fig. 1b and Fig. 1c are schematic diagrams of the circuit connection structure of the preferred embodiment of the present invention. the

Figure 2a is a circuit diagram of U1 and U3, and Figure 2b and Figure 2c are fractional-order integral circuits. the

Figure 3a is the actual connection diagram of the circuit of U2, U4 and U5, and Figure 3b is the fractional-order integral circuit. the

Detailed ways

The utility model will be further described in detail below in conjunction with the accompanying drawings and preferred embodiments, see Fig. 1-Fig. 3 . the

A kind of chen chaotic switching system circuit with different fractional orders is characterized in that, comprising the following steps:

(1) The equation of chen chaotic system i is:

(2) The equation of the 0.9-order chen chaotic system ii is:

(3) The equation of the 0.1-order chen chaotic system iii is:

(4) Construct switching function q=f(x), where the expression iv of f(x) is:

$\mathrm{<span\; class="notranslate">\; q</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; f</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\left\{\begin{array}{cc}\mathrm{<span\; class="notranslate">\; 0.9</span>}& \mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; ></span>\mathrm{<span\; class="notranslate">\; 0</span>}\\ \mathrm{<span\; class="notranslate">\; 0.1</span>}& \mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; \&le;</span>\mathrm{<span\; class="notranslate">\; 0</span>}\end{array}\right.<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; iv</span>}$

(5) A chen chaotic switching system v with different fractional orders constructed from ii, iii and iv is:

(6) Construct an analog circuit system according to the chen chaotic switching system v with different fractional orders, use the operational amplifier U1, operational amplifier U2, resistors and capacitors to form an inverting adder and fractional inverting integrators of different orders, and use multiplication The multiplier U3 and the multiplier U4 realize the multiplication operation, utilize the analog switch U5 to realize the selective output of the analog signal, the operational amplifier U1 and the operational amplifier U2 adopt LF347D, the multiplier U3 and the multiplier U4 adopt AD633JN, and the analog switch U5 Adopt ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4 and analog switch U5, described operational amplifier U2 connects multiplier U3 and analog switch U5, described multiplier U3 connects operational amplifier U1, described multiplier U4 Connect the operational amplifier U2, the analog switch U5 connects the operational amplifier U1 and the operational amplifier U2;

The first pin of the operational amplifier U1 is connected to the second pin of the operational amplifier U1 through a resistor R3, and connected to the sixth pin of the operational amplifier U1 through a resistor R8, and the third, fifth, and tenth pins of the operational amplifier U1 are , Pin 12 is grounded, pin 4 is connected to VCC, pin 11 is connected to VEE, pin 6 of operational amplifier U1 is connected in parallel with resistor Ry11 and capacitor Cy11, connected in parallel with resistor Ry12 and capacitor Cy12, and then connected with resistor Ry13 After connecting in parallel with the capacitor Cy13, connect the 7th pin of the analog switch U5, through the parallel connection of the resistor Ry21 and the capacitor Cy21, connect the parallel connection of the resistor Ry22 and the capacitor Cy22, then connect the parallel connection of the resistor Ry23 and the capacitor Cy23, and then connect the analog The 5th pin of the switch U5, the 7th pin of the operational amplifier U1 is connected to the 13th pin of the operational amplifier U1 through the resistor R2, the 2nd pin of the operational amplifier U1 is connected through the resistor R5, and the 3rd pin of the multiplier U4 pin, the 8th pin of the operational amplifier U1 is connected to the 9th pin of the operational amplifier U1 through the resistor R6, the 6th pin of the operational amplifier U1 is connected through the resistor R4, the 2nd pin of the operational amplifier U2 is connected to the multiplier U3 The 1st pin of the multiplier U4 is connected to the 1st pin of the multiplier U4, and the 9th pin of the operational amplifier U1 is connected to the parallel connection of the resistor Rx11 and the capacitor Cx11, connected to the parallel connection of the resistor Rx12 and the capacitor Cx12, and then connected to the resistor Rx13 and the capacitor Cx13 After connecting in parallel, connect the second pin of the analog switch U5, through the parallel connection of the resistor Rx21 and the capacitor Cx21, connect the parallel connection of the resistor Rx22 and the capacitor Cx22, then connect the parallel connection of the resistor Rx23 and the capacitor Cx23, and then connect the first pin of the analog switch U5 4 pins, the 14th pin of the operational amplifier U1 is connected to the 13th pin of the operational amplifier U1 through the resistor R1, and the 9th pin of the operational amplifier U1 is connected through the resistor R7;

The 6th and 7th pins of the operational amplifier U2 are suspended, the 3rd, 5th, 10th, and 12th pins of the operational amplifier U2 are grounded, the 4th pin is connected to VCC, the 11th pin is connected to VEE, and the 11th pin of the operational amplifier U2 is connected to VEE. The first pin is connected to the ground through the series connection of resistors R14 and R15, connected to the 8th and 9th pins of the analog switch U5 through R14, the 8th pin of the operational amplifier U2 is connected to the 9th pin of the operational amplifier U2 through the resistor R12, and then multiplied The 3rd pin of the circuit breaker U3, the 9th pin of the operational amplifier U2 connects the parallel connection of the resistor Rz11 and the capacitor Cz11, connects the parallel connection of the resistor Rz12 and the capacitor Cz12, then connects the parallel connection of the resistor Rz13 and the capacitor Cz13, and then connects the analog switch U5 The 10th pin, through the parallel connection of resistor Rz21 and capacitor Cz21, the parallel connection of resistor Rz22 and capacitor Cz22, and then the parallel connection of resistor Rz23 and capacitor Cz23, and then connect the 12th pin of analog switch U5, the operational amplifier U2 The 14th pin is connected to the 13th pin of the operational amplifier U2 through the resistor R11, and connected to the 9th pin of the operational amplifier U2 through the resistor R13;

The first pin of the multiplier U3 is connected to the eighth pin of the operational amplifier U1, the third pin is connected to the eighth pin of the operational amplifier U2, the second, fourth, and sixth pins are all grounded, and the fifth pin is connected to the eighth pin of the operational amplifier U2. VEE, the 7th pin is connected to the 6th pin of the operational amplifier U1 through the resistor R9, and the 8th pin is connected to VCC;

The first pin of the multiplier U4 is connected to the 8th pin of the operational amplifier U1, the 3rd pin is connected to the 7th pin of the operational amplifier U1, the 2nd, 4th and 6th pins are all grounded, and the 5th pin is connected to the VEE, the 7th pin is connected to the 13th pin of the operational amplifier U2 through the resistor R10, and the 8th pin is connected to VCC;

The first pin of the analog switch U5 is connected to VCC, the 16th pin is grounded, the 13th, 14th and 15th pins are suspended, the 3rd pin is connected to the 8th pin of the operational amplifier U1, and the 6th pin is connected to the operational amplifier The 7th pin of U1 and the 11th pin are connected to the 8th pin of the operational amplifier U2. the

Resistance in the circuit R1=R7=R3=R8=R11=R13=10kΩ, R2=R6=2.86kΩ, R4=14.3kΩ, R5=3.57kΩ, R9=R10=1kΩ, R12=33.3kΩ, R14=100kΩ, R15 =80kΩ, Rx11=Ry11=Rz11=62.84MΩ, Rx12=Ry12=Rz12=250kΩ, Rx13=Ry13=Rz13=2.5kΩ, Rx21=Ry21=Rz21=0.636MΩ, Rx22=Ry22=Rz22=0.3815MΩ, Rx23=Ry =Rz23=0.5672MΩ, Cx11=Cy11=Cz11=1.2μF, Cx12=Cy12=Cz13=1.8μF, Cx13=Cy13=Cz13=1.1μF, Cx21=Cy21=Cz21=15.75μF, Cx22=Cy22=Cz22=0.1575μF , Cx23=Cy23=Cz23=633.5nF. the

Claims (1)

1. the chen chaos switched system circuit that fractional-order is different, is characterized in that being: the different chen chaos switched system of a kind of fractional-order is:

x in formula, y, z is state variable, the chen chaos switched system constructing analog Circuits System different according to fractional-order, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form the fractional order inverting integrator of anti-phase adder and different order, multiplier U3 and multiplier U4 is utilized to realize multiplying, the selection utilizing analog switch U5 to realize analog signal exports, described operational amplifier U1 and operational amplifier U2 adopts LF347D, described multiplier U3 and multiplier U4 adopts AD633JN, described analog switch U5 adopts ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4 and analog switch U5, described operational amplifier U2 connects multiplier U3 and analog switch U5, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2, described analog switch U5 concatenation operation amplifier U1 and operational amplifier U2,

1st pin of described operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance R3, connected with the 6th pin of operational amplifier U1 by resistance R8, the 3rd of operational amplifier U1, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U1 is in parallel by resistance Ry11 and electric capacity Cy11's, connecting resistance Ry12 is in parallel with electric capacity Cy12's, connecting resistance Ry13 and electric capacity Cy13 again in parallel after, connect the 7th pin of analog switch U5 again, in parallel by resistance Ry21 and electric capacity Cy21, connecting resistance Ry22 is in parallel with electric capacity Cy22's, connecting resistance Ry23 and electric capacity Cy23 again in parallel after, connect the 5th pin of analog switch U5 again, 7th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R2, the 2nd pin of operational amplifier U1 is connect by resistance R5, connect the 3rd pin of multiplier U4, 8th pin of operational amplifier U1 connects the 9th pin of operational amplifier U1 by resistance R6, the 6th pin of operational amplifier U1 is connect by resistance R4, connect the 2nd pin of operational amplifier U2, connect the 1st pin of multiplier U3, connect the 1st pin of multiplier U4, 9th pin of operational amplifier U1 is in parallel by resistance Rx11 and electric capacity Cx11's, connecting resistance Rx12 is in parallel with electric capacity Cx12's, connecting resistance Rx13 and electric capacity Cx13 again in parallel after, connect the 2nd pin of analog switch U5 again, in parallel by resistance Rx21 and electric capacity Cx21, connecting resistance Rx22 is in parallel with electric capacity Cx22's, connecting resistance Rx23 and electric capacity Cx23 again in parallel after, connect the 4th pin of analog switch U5 again, 14th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R1, the 9th pin of operational amplifier U1 is connect by resistance R7,

The 6th of described operational amplifier U2, 7 pins are unsettled, the 3rd of described operational amplifier U2, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 1st pin of operational amplifier U2 passes through the series connection ground connection of resistance R14 and R15, the 8th of analog switch U5 the is connect by R14, 9 pins, 8th pin of operational amplifier U2 connects the 9th pin of operational amplifier U2 by resistance R12, connect the 3rd pin of multiplier U3, 9th pin of operational amplifier U2 is in parallel by resistance Rz11 and electric capacity Cz11's, connecting resistance Rz12 is in parallel with electric capacity Cz12's, connecting resistance Rz13 and electric capacity Cz13 again in parallel after, connect the 10th pin of analog switch U5 again, in parallel by resistance Rz21 and electric capacity Cz21, connecting resistance Rz22 is in parallel with electric capacity Cz22's, connecting resistance Rz23 and electric capacity Cz23 again in parallel after, connect the 12nd pin of analog switch U5 again, 14th pin of operational amplifier U2 connects the 13rd pin of operational amplifier U2 by resistance R11, the 9th pin of operational amplifier U2 is connect by resistance R13,

1st pin of described multiplier U3 connects the 8th pin of operational amplifier U1,3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 6th pin of operational amplifier U1 by resistance R9, and the 8th pin meets VCC;

1st pin of described multiplier U4 connects the 8th pin of operational amplifier U1,3rd pin connects the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 13rd pin of operational amplifier U2 by resistance R10, and the 8th pin meets VCC;

1st pin of described analog switch U5 meets VCC, the 16th pin ground connection, the 13rd, 14,15 pins are unsettled, the 3rd pin connects the 8th pin of operational amplifier U1, and the 6th pin connects the 7th pin of operational amplifier U1, and the 11st pin connects the 8th pin of operational amplifier U2.