CN204145515U - The chen chaos switched system circuit that a kind of fractional-order is different - Google Patents
The chen chaos switched system circuit that a kind of fractional-order is different Download PDFInfo
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- CN204145515U CN204145515U CN201420113773.6U CN201420113773U CN204145515U CN 204145515 U CN204145515 U CN 204145515U CN 201420113773 U CN201420113773 U CN 201420113773U CN 204145515 U CN204145515 U CN 204145515U
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Abstract
The chen chaos switched system circuit that the utility model provides a kind of fractional-order different, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form the fractional order inverting integrator of anti-phase adder and different order, multiplier U3 and multiplier U4 is utilized to realize multiplying, the selection utilizing analog switch U5 to realize analog signal exports, described operational amplifier U1 and operational amplifier U2 adopts LF347D, described multiplier U3 and multiplier U4 adopts AD633JN, described analog switch U5 adopts ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4 and analog switch U5, described operational amplifier U2 connects multiplier U3 and analog switch U5, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2, described analog switch U5 concatenation operation amplifier U1 and operational amplifier U2, propose the novel commutation circuit of a novel chaos system, this is applied to engineering practice to the type and this chaos system that increase chaos system switching and provides a kind of new approaches.
Description
Technical field
The utility model relates to a chaos system and circuit realiration, the chen chaos switched system circuit that particularly a kind of fractional-order is different.
Background technology
At present, the main circuit of the switching chaos system that oneself has will comprise the switching between different linear term in chaos system or nonlinear terms, and based on the fractional order form of these 2 kinds of switch modes, commutation circuit about the chaotic systems with fractional order of different order is not also suggested, the utility model proposes the classical chen chaos commutation circuit that a kind of fractional-order is different, the present invention proposes the novel commutation circuit of a novel chaos system, this is applied to engineering practice provides a kind of new approaches to increasing type that chaos system switches and this chaos system.
Summary of the invention
The technical problems to be solved in the utility model is to provide the different classical chen chaos commutation circuit of a kind of fractional-order, and the utility model adopts following technological means to realize goal of the invention:
The chen chaos switched system circuit that fractional-order is different, is characterized in that being, comprises the following steps:
(1) equation of chen chaos system i is:
The equation of (2) 0.9 rank chen chaos system ii is:
The equation of (3) 0.1 rank chen chaos system iii is:
(4) construct switching function q=f (x), wherein the expression formula iv of f (x) is:
(5) the chen chaos switched system v constructing a kind of fractional-order different by ii, iii and iv is:
(6) different according to fractional-order chen chaos switched system v constructing analog Circuits System, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form the fractional order inverting integrator of anti-phase adder and different order, multiplier U3 and multiplier U4 is utilized to realize multiplying, the selection utilizing analog switch U5 to realize analog signal exports, described operational amplifier U1 and operational amplifier U2 adopts LF347D, described multiplier U3 and multiplier U4 adopts AD633JN, described analog switch U5 adopts ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4 and analog switch U5, described operational amplifier U2 connects multiplier U3 and analog switch U5, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2, described analog switch U5 concatenation operation amplifier U1 and operational amplifier U2,
1st pin of described operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance R3, connected with the 6th pin of operational amplifier U1 by resistance R8, the 3rd of operational amplifier U1, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U1 is in parallel by resistance Ry11 and electric capacity Cy11's, connecting resistance Ry12 is in parallel with electric capacity Cy12's, connecting resistance Ry13 and electric capacity Cy13 again in parallel after, connect the 7th pin of analog switch U5 again, in parallel by resistance Ry21 and electric capacity Cy21, connecting resistance Ry22 is in parallel with electric capacity Cy22's, connecting resistance Ry23 and electric capacity Cy23 again in parallel after, connect the 5th pin of analog switch U5 again, 7th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R2, the 2nd pin of operational amplifier U1 is connect by resistance R5, connect the 3rd pin of multiplier U4, 8th pin of operational amplifier U1 connects the 9th pin of operational amplifier U1 by resistance R6, the 6th pin of operational amplifier U1 is connect by resistance R4, connect the 2nd pin of operational amplifier U2, connect the 1st pin of multiplier U3, connect the 1st pin of multiplier U4, 9th pin of operational amplifier U1 is in parallel by resistance Rx11 and electric capacity Cx11's, connecting resistance Rx12 is in parallel with electric capacity Cx12's, connecting resistance Rx13 and electric capacity Cx13 again in parallel after, connect the 2nd pin of analog switch U5 again, in parallel by resistance Rx21 and electric capacity Cx21, connecting resistance Rx22 is in parallel with electric capacity Cx22's, connecting resistance Rx23 and electric capacity Cx23 again in parallel after, connect the 4th pin of analog switch U5 again, 14th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R1, the 9th pin of operational amplifier U1 is connect by resistance R7,
The 6th of described operational amplifier U2, 7 pins are unsettled, the 3rd of described operational amplifier U2, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 1st pin of operational amplifier U2 passes through the series connection ground connection of resistance R14 and R15, the 8th of analog switch U5 the is connect by R14, 9 pins, 8th pin of operational amplifier U2 connects the 9th pin of operational amplifier U2 by resistance R12, connect the 3rd pin of multiplier U3, 9th pin of operational amplifier U2 is in parallel by resistance Rz11 and electric capacity Cz11's, connecting resistance Rz12 is in parallel with electric capacity Cz12's, connecting resistance Rz13 and electric capacity Cz13 again in parallel after, connect the 10th pin of analog switch U5 again, in parallel by resistance Rz21 and electric capacity Cz21, connecting resistance Rz22 is in parallel with electric capacity Cz22's, connecting resistance Rz23 and electric capacity Cz23 again in parallel after, connect the 12nd pin of analog switch U5 again, 14th pin of operational amplifier U2 connects the 13rd pin of operational amplifier U2 by resistance R11, the 9th pin of operational amplifier U2 is connect by resistance R13,
1st pin of described multiplier U3 connects the 8th pin of operational amplifier U1,3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 6th pin of operational amplifier U1 by resistance R9, and the 8th pin meets VCC;
1st pin of described multiplier U4 connects the 8th pin of operational amplifier U1,3rd pin connects the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 13rd pin of operational amplifier U2 by resistance R10, and the 8th pin meets VCC;
1st pin of described analog switch U5 meets VCC, the 16th pin ground connection, the 13rd, 14,15 pins are unsettled, the 3rd pin connects the 8th pin of operational amplifier U1, and the 6th pin connects the 7th pin of operational amplifier U1, and the 11st pin connects the 8th pin of operational amplifier U2.
The beneficial effects of the utility model are: the novel commutation circuit proposing a novel chaos system, and this is applied to engineering practice provides a kind of new approaches to increasing type that chaos system switches and this chaos system.
Accompanying drawing explanation
Fig. 1 a, Fig. 1 b and Fig. 1 c is the circuit connection structure schematic diagram of the utility model preferred embodiment.
Fig. 2 a is that the circuit of U1 and U3 connects figure, and Fig. 2 b and Fig. 2 c is fractional order integration circuit.
Fig. 3 a is the actual connection layout of circuit of U2, U4 and U5, and Fig. 3 b is fractional order integration circuit.
Embodiment
Below in conjunction with accompanying drawing and preferred embodiment, the utility model is further described in detail, see Fig. 1-Fig. 3.
The chen chaos switched system circuit that fractional-order is different, is characterized in that being, comprises the following steps:
(1) equation of chen chaos system i is:
The equation of (2) 0.9 rank chen chaos system ii is:
The equation of (3) 0.1 rank chen chaos system iii is:
(4) construct switching function q=f (x), wherein the expression formula iv of f (x) is:
(5) the chen chaos switched system v constructing a kind of fractional-order different by ii, iii and iv is:
(6) different according to fractional-order chen chaos switched system v constructing analog Circuits System, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form the fractional order inverting integrator of anti-phase adder and different order, multiplier U3 and multiplier U4 is utilized to realize multiplying, the selection utilizing analog switch U5 to realize analog signal exports, described operational amplifier U1 and operational amplifier U2 adopts LF347D, described multiplier U3 and multiplier U4 adopts AD633JN, described analog switch U5 adopts ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4 and analog switch U5, described operational amplifier U2 connects multiplier U3 and analog switch U5, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2, described analog switch U5 concatenation operation amplifier U1 and operational amplifier U2,
1st pin of described operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance R3, connected with the 6th pin of operational amplifier U1 by resistance R8, the 3rd of operational amplifier U1, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U1 is in parallel by resistance Ry11 and electric capacity Cy11's, connecting resistance Ry12 is in parallel with electric capacity Cy12's, connecting resistance Ry13 and electric capacity Cy13 again in parallel after, connect the 7th pin of analog switch U5 again, in parallel by resistance Ry21 and electric capacity Cy21, connecting resistance Ry22 is in parallel with electric capacity Cy22's, connecting resistance Ry23 and electric capacity Cy23 again in parallel after, connect the 5th pin of analog switch U5 again, 7th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R2, the 2nd pin of operational amplifier U1 is connect by resistance R5, connect the 3rd pin of multiplier U4, 8th pin of operational amplifier U1 connects the 9th pin of operational amplifier U1 by resistance R6, the 6th pin of operational amplifier U1 is connect by resistance R4, connect the 2nd pin of operational amplifier U2, connect the 1st pin of multiplier U3, connect the 1st pin of multiplier U4, 9th pin of operational amplifier U1 is in parallel by resistance Rx11 and electric capacity Cx11's, connecting resistance Rx12 is in parallel with electric capacity Cx12's, connecting resistance Rx13 and electric capacity Cx13 again in parallel after, connect the 2nd pin of analog switch U5 again, in parallel by resistance Rx21 and electric capacity Cx21, connecting resistance Rx22 is in parallel with electric capacity Cx22's, connecting resistance Rx23 and electric capacity Cx23 again in parallel after, connect the 4th pin of analog switch U5 again, 14th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R1, the 9th pin of operational amplifier U1 is connect by resistance R7,
The 6th of described operational amplifier U2, 7 pins are unsettled, the 3rd of described operational amplifier U2, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 1st pin of operational amplifier U2 passes through the series connection ground connection of resistance R14 and R15, the 8th of analog switch U5 the is connect by R14, 9 pins, 8th pin of operational amplifier U2 connects the 9th pin of operational amplifier U2 by resistance R12, connect the 3rd pin of multiplier U3, 9th pin of operational amplifier U2 is in parallel by resistance Rz11 and electric capacity Cz11's, connecting resistance Rz12 is in parallel with electric capacity Cz12's, connecting resistance Rz13 and electric capacity Cz13 again in parallel after, connect the 10th pin of analog switch U5 again, in parallel by resistance Rz21 and electric capacity Cz21, connecting resistance Rz22 is in parallel with electric capacity Cz22's, connecting resistance Rz23 and electric capacity Cz23 again in parallel after, connect the 12nd pin of analog switch U5 again, 14th pin of operational amplifier U2 connects the 13rd pin of operational amplifier U2 by resistance R11, the 9th pin of operational amplifier U2 is connect by resistance R13,
1st pin of described multiplier U3 connects the 8th pin of operational amplifier U1,3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 6th pin of operational amplifier U1 by resistance R9, and the 8th pin meets VCC;
1st pin of described multiplier U4 connects the 8th pin of operational amplifier U1,3rd pin connects the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 13rd pin of operational amplifier U2 by resistance R10, and the 8th pin meets VCC;
1st pin of described analog switch U5 meets VCC, the 16th pin ground connection, the 13rd, 14,15 pins are unsettled, the 3rd pin connects the 8th pin of operational amplifier U1, and the 6th pin connects the 7th pin of operational amplifier U1, and the 11st pin connects the 8th pin of operational amplifier U2.
Resistance R1=R7=R3=R8=R11=R13=10k Ω in circuit, R2=R6=2.86k Ω, R4=14.3k Ω, R5=3.57k Ω, R9=R10=1k Ω, R12=33.3k Ω, R14=100k Ω, R15=80k Ω, Rx11=Ry11=Rz11=62.84M Ω, Rx12=Ry12=Rz12=250k Ω, Rx13=Ry13=Rz13=2.5k Ω, Rx21=Ry21=Rz21=0.636M Ω, Rx22=Ry22=Rz22=0.3815M Ω, Rx23=Ry23=Rz23=0.5672M Ω, Cx11=Cy11=Cz11=1.2 μ F, Cx12=Cy12=Cz13=1.8 μ F, Cx13=Cy13=Cz13=1.1 μ F, Cx21=Cy21=Cz21=15.75 μ F, Cx22=Cy22=Cz22=0.1575 μ F, Cx23=Cy23=Cz23=633.5nF.
Claims (1)
1. the chen chaos switched system circuit that fractional-order is different, is characterized in that being: the different chen chaos switched system of a kind of fractional-order is:
x in formula, y, z is state variable, the chen chaos switched system constructing analog Circuits System different according to fractional-order, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form the fractional order inverting integrator of anti-phase adder and different order, multiplier U3 and multiplier U4 is utilized to realize multiplying, the selection utilizing analog switch U5 to realize analog signal exports, described operational amplifier U1 and operational amplifier U2 adopts LF347D, described multiplier U3 and multiplier U4 adopts AD633JN, described analog switch U5 adopts ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4 and analog switch U5, described operational amplifier U2 connects multiplier U3 and analog switch U5, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2, described analog switch U5 concatenation operation amplifier U1 and operational amplifier U2,
1st pin of described operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance R3, connected with the 6th pin of operational amplifier U1 by resistance R8, the 3rd of operational amplifier U1, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U1 is in parallel by resistance Ry11 and electric capacity Cy11's, connecting resistance Ry12 is in parallel with electric capacity Cy12's, connecting resistance Ry13 and electric capacity Cy13 again in parallel after, connect the 7th pin of analog switch U5 again, in parallel by resistance Ry21 and electric capacity Cy21, connecting resistance Ry22 is in parallel with electric capacity Cy22's, connecting resistance Ry23 and electric capacity Cy23 again in parallel after, connect the 5th pin of analog switch U5 again, 7th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R2, the 2nd pin of operational amplifier U1 is connect by resistance R5, connect the 3rd pin of multiplier U4, 8th pin of operational amplifier U1 connects the 9th pin of operational amplifier U1 by resistance R6, the 6th pin of operational amplifier U1 is connect by resistance R4, connect the 2nd pin of operational amplifier U2, connect the 1st pin of multiplier U3, connect the 1st pin of multiplier U4, 9th pin of operational amplifier U1 is in parallel by resistance Rx11 and electric capacity Cx11's, connecting resistance Rx12 is in parallel with electric capacity Cx12's, connecting resistance Rx13 and electric capacity Cx13 again in parallel after, connect the 2nd pin of analog switch U5 again, in parallel by resistance Rx21 and electric capacity Cx21, connecting resistance Rx22 is in parallel with electric capacity Cx22's, connecting resistance Rx23 and electric capacity Cx23 again in parallel after, connect the 4th pin of analog switch U5 again, 14th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R1, the 9th pin of operational amplifier U1 is connect by resistance R7,
The 6th of described operational amplifier U2, 7 pins are unsettled, the 3rd of described operational amplifier U2, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 1st pin of operational amplifier U2 passes through the series connection ground connection of resistance R14 and R15, the 8th of analog switch U5 the is connect by R14, 9 pins, 8th pin of operational amplifier U2 connects the 9th pin of operational amplifier U2 by resistance R12, connect the 3rd pin of multiplier U3, 9th pin of operational amplifier U2 is in parallel by resistance Rz11 and electric capacity Cz11's, connecting resistance Rz12 is in parallel with electric capacity Cz12's, connecting resistance Rz13 and electric capacity Cz13 again in parallel after, connect the 10th pin of analog switch U5 again, in parallel by resistance Rz21 and electric capacity Cz21, connecting resistance Rz22 is in parallel with electric capacity Cz22's, connecting resistance Rz23 and electric capacity Cz23 again in parallel after, connect the 12nd pin of analog switch U5 again, 14th pin of operational amplifier U2 connects the 13rd pin of operational amplifier U2 by resistance R11, the 9th pin of operational amplifier U2 is connect by resistance R13,
1st pin of described multiplier U3 connects the 8th pin of operational amplifier U1,3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 6th pin of operational amplifier U1 by resistance R9, and the 8th pin meets VCC;
1st pin of described multiplier U4 connects the 8th pin of operational amplifier U1,3rd pin connects the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 13rd pin of operational amplifier U2 by resistance R10, and the 8th pin meets VCC;
1st pin of described analog switch U5 meets VCC, the 16th pin ground connection, the 13rd, 14,15 pins are unsettled, the 3rd pin connects the 8th pin of operational amplifier U1, and the 6th pin connects the 7th pin of operational amplifier U1, and the 11st pin connects the 8th pin of operational amplifier U2.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105429746A (en) * | 2015-10-29 | 2016-03-23 | 山东农业大学 | Chaotic system automatic switching construction method and simulation circuit containing fractional order |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105429746A (en) * | 2015-10-29 | 2016-03-23 | 山东农业大学 | Chaotic system automatic switching construction method and simulation circuit containing fractional order |
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Granted publication date: 20150204 Termination date: 20160313 |
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