CN103825701B - Method for classical Qi chaotic switching system with different fractional orders and circuit - Google Patents

Abstract

The invention provides a method and a circuit for realizing a classical Qi chaotic switching system with different fractional orders. The method comprises the steps that an operational amplifier U1, an operational amplifier U2, a resistor and a capacitor are used for constituting a phase reversal summator and a fractional order phase reversal integrator with different orders; a multiplying unit U3, a multiplying unit U4 and a multiplying unit U6 are used for achieving multiplication, and an analog switch U5 is used for achieving selection output of analog signals; the model of the operational amplifier U1 and the model of the operational amplifier U2 are LF347D, the model of the multiplying unit U3, the model of the multiplying unit U4 and the model of the multiplying unit U6 are AD633JN, and the model of the analog switch U5 is ADG888; the operational amplifier U1 is connected with the multiplying unit U3, the multiplying unit U4, the multiplying unit U6 and the analog switch U5; the operational amplifier U2 is connected with the multiplying unit U3, the multiplying unit U6 and the analog switch U5; the multiplying unit U3 is connected with the operational amplifier U1, the multiplying unit U4 is connected with the operational amplifier U2, the analog switch U5 is connected with the operational amplifier U1 and the operational amplifier U2, and the multiplying unit U6 is connected with the operational amplifier U1. The novel switching method and circuit of a novel chaotic system are provided, and a new thought is supplied to adding the switching type of the chaotic system and enabling the chaotic system to be applied to engineering practice.

Description

A kind of method and circuit realizing the different classical Qi chaos switched system of fractional-order

Technical field

The present invention relates to a chaos system and circuit realiration, particularly a kind of method and circuit realizing the different classical Qi chaos switched system of fractional-order.

Background technology

At present, method and the main circuit of the switching chaos system that oneself has will comprise the switching between different linear term in chaos system or nonlinear terms, and based on the fractional order form of these 2 kinds of switch modes, also be not suggested about the changing method of the chaotic systems with fractional order of different order and circuit, the present invention proposes a kind of different classical Qi chaos switched system method of fractional-order and circuit, the present invention proposes New-type switching method and the circuit of a novel chaos system, this is applied to engineering practice to the type and this chaos system that increase chaos system switching and provides a kind of new approaches.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of method and the circuit that realize the different classical Qi chaos switched system of fractional-order, and the present invention adopts following technological means to realize goal of the invention:

1, realize a method for the different classical Qi chaos switched system of fractional-order, it is characterized in that being, comprise the following steps:

(1) equation of classical Qi chaos system i is:

$\left\{\begin{array}{ccc}\mathrm{dx}/\mathrm{dt}=\mathrm{\ρ}(y-x)+\mathrm{yz}& & \\ \mathrm{dy}/\mathrm{dt}=\mathrm{\αx}-y-\mathrm{xz}& i& \mathrm{\ρ}=35,\mathrm{\β}=8/3,\mathrm{\α}=80\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xy}-\mathrm{\βz}& & \end{array}\right.$

The equation of (2) 0.9 rank classical Qi chaos system ii is:

$\left\{\begin{array}{ccc}{d}^{0.9}x/{\mathrm{dt}}^{0.9}=\mathrm{\ρ}(y-x)+\mathrm{yz}& & \\ d^{0.9}y/{\mathrm{dt}}^{0.9}=\mathrm{\αx}-y-\mathrm{xz}& \mathrm{ii}& \mathrm{\ρ}=35,\mathrm{\β}=8/3,\mathrm{\α}=80\\ d^{0.9}z/{\mathrm{dt}}^{0.9}=\mathrm{xy}-\mathrm{\βz}& & \end{array}\right.$

The equation of (3) 0.1 rank classical Qi chaos system iii is:

$\left\{\begin{array}{ccc}{d}^{0.1}x/{\mathrm{dt}}^{0.1}=\mathrm{\ρ}(y-x)+\mathrm{yz}& & \\ d^{0.1}y/{\mathrm{dt}}^{0.1}=\mathrm{\αx}-y-\mathrm{xz}& \mathrm{iii}& \mathrm{\ρ}=35,\mathrm{\β}=8/3,\mathrm{\α}=80\\ d^{0.1}z/{\mathrm{dt}}^{0.1}=\mathrm{xy}-\mathrm{\βz}& & \end{array}\right.$

(4) construct switching function q=f (x), wherein the expression formula iv of f (x) is:

$q=f\left(x\right)=\left\{\begin{array}{cc}0.9& x>0\\ 0.1& x\≤0\end{array}\right.---\mathrm{iv}$

(5) the classical Qi chaos switched system v constructing a kind of fractional-order different by ii, iii and iv is:

$\begin{array}{cc}\left\{\begin{array}{c}{d}^{q}x/{\mathrm{dt}}^q=\mathrm{\ρ}(y-x)+\mathrm{yz}\\ d^{q}y/{\mathrm{dt}}^q=\mathrm{\αx}-y-\mathrm{xz}\\ d^{q}z/{\mathrm{dt}}^q=\mathrm{xy}-\mathrm{\βz}\end{array}\right.& \mathrm{\ρ}=35,\mathrm{\β}=8/3,\mathrm{\α}=80,q=f\left(x\right)=\left\{\begin{array}{cc}0.9& x>0\\ 0.1& x\≤0\end{array}\right.\end{array}---v$

(6) different according to fractional-order classical Qi chaos switched system v constructing analog Circuits System, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form the fractional order inverting integrator of anti-phase adder and different order, utilize multiplier U3, multiplier U4 and multiplier U6 realizes multiplying, the selection utilizing analog switch U5 to realize analog signal exports, described operational amplifier U1 and operational amplifier U2 adopts LF347D, described multiplier U3, multiplier U4 and multiplier U6 adopts AD633JN, described analog switch U5 adopts ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4, multiplier U6 and analog switch U5, described operational amplifier U2 connects multiplier U3, multiplier U6 and analog switch U5, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2, described analog switch U5 concatenation operation amplifier U1 and operational amplifier U2, described multiplier U6 concatenation operation amplifier U1,

1st pin of described operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance R3, connected with the 6th pin of operational amplifier U1 by resistance R8, the 3rd of operational amplifier U1, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U1 is in parallel by resistance Ry11 and electric capacity Cy11's, connecting resistance Ry12 is in parallel with electric capacity Cy12's, connecting resistance Ry13 and electric capacity Cy13 again in parallel after, connect the 7th pin of analog switch U5 again, in parallel by resistance Ry21 and electric capacity Cy21, connecting resistance Ry22 is in parallel with electric capacity Cy22's, connecting resistance Ry23 and electric capacity Cy23 again in parallel after, connect the 5th pin of analog switch U5 again, 7th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R2, the 6th pin of operational amplifier U1 is connect by resistance R4, connect the 3rd pin of multiplier U4, connect the 1st pin of multiplier U6, 8th pin of operational amplifier U1 connects the 2nd pin of operational amplifier U1 by resistance R5, the 9th pin of operational amplifier U1 is connect by resistance R6, connect the 2nd pin of operational amplifier U2, connect the 1st pin of multiplier U3, connect the 1st pin of multiplier U4, 9th pin of operational amplifier U1 is in parallel by resistance Rx11 and electric capacity Cx11's, connecting resistance Rx12 is in parallel with electric capacity Cx12's, connecting resistance Rx13 and electric capacity Cx13 again in parallel after, connect the 2nd pin of analog switch U5 again, in parallel by resistance Rx21 and electric capacity Cx21, connecting resistance Rx22 is in parallel with electric capacity Cx22's, connecting resistance Rx23 and electric capacity Cx23 again in parallel after, connect the 4th pin of analog switch U5 again, 14th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R1, the 9th pin of operational amplifier U1 is connect by resistance R7,

The 6th of described operational amplifier U2, 7 pins are unsettled, the 3rd of described operational amplifier U2, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 1st pin of operational amplifier U2 passes through the series connection ground connection of resistance R14 and R15, the 8th of analog switch U5 the is connect by R14, 9 pins, 8th pin of operational amplifier U2 connects the 9th pin of operational amplifier U2 by resistance R12, connect the 3rd pin of multiplier U3, connect the 3rd pin of multiplier U6, 9th pin of operational amplifier U2 is in parallel by resistance Rz11 and electric capacity Cz11's, connecting resistance Rz12 is in parallel with electric capacity Cz12's, connecting resistance Rz13 and electric capacity Cz13 again in parallel after, connect the 10th pin of analog switch U5 again, in parallel by resistance Rz21 and electric capacity Cz21, connecting resistance Rz22 is in parallel with electric capacity Cz22's, connecting resistance Rz23 and electric capacity Cz23 again in parallel after, connect the 12nd pin of analog switch U5 again, 14th pin of operational amplifier U2 connects the 13rd pin of operational amplifier U2 by resistance R11, the 9th pin of operational amplifier U2 is connect by resistance R13,

1st pin of described multiplier U3 connects the 8th pin of operational amplifier U1,3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 6th pin of operational amplifier U1 by resistance R9, and the 8th pin meets VCC;

1st pin of described multiplier U4 connects the 8th pin of operational amplifier U1,3rd pin connects the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 13rd pin of operational amplifier U2 by resistance R10, and the 8th pin meets VCC;

1st pin of described analog switch U5 meets VCC, the 16th pin ground connection, the 13rd, 14,15 pins are unsettled, the 3rd pin connects the 8th pin of operational amplifier U1, and the 6th pin connects the 7th pin of operational amplifier U1, and the 11st pin connects the 8th pin of operational amplifier U2;

1st pin of described multiplier U6 connects the 7th pin of operational amplifier U1,3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 13rd pin of operational amplifier U1 by resistance R16, and the 8th pin meets VCC.

2, a kind of circuit realizing the different classical Qi chaos switched system of fractional-order, it is characterized in that being, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form the fractional order inverting integrator of anti-phase adder and different order, utilize multiplier U3, multiplier U4 and multiplier U6 realizes multiplying, the selection utilizing analog switch U5 to realize analog signal exports, described operational amplifier U1 and operational amplifier U2 adopts LF347D, described multiplier U3, multiplier U4 and multiplier U6 adopts AD633JN, described analog switch U5 adopts ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4, multiplier U6 and analog switch U5, described operational amplifier U2 connects multiplier U3, multiplier U6 and analog switch U5, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2, described analog switch U5 concatenation operation amplifier U1 and operational amplifier U2, described multiplier U6 concatenation operation amplifier U1,

1st pin of described operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance R3, connected with the 6th pin of operational amplifier U1 by resistance R8, the 3rd of operational amplifier U1, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U1 is in parallel by resistance Ry11 and electric capacity Cy11's, connecting resistance Ry12 is in parallel with electric capacity Cy12's, connecting resistance Ry13 and electric capacity Cy13 again in parallel after, connect the 7th pin of analog switch U5 again, in parallel by resistance Ry21 and electric capacity Cy21, connecting resistance Ry22 is in parallel with electric capacity Cy22's, connecting resistance Ry23 and electric capacity Cy23 again in parallel after, connect the 5th pin of analog switch U5 again, 7th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R2, the 6th pin of operational amplifier U1 is connect by resistance R4, connect the 3rd pin of multiplier U4, connect the 1st pin of multiplier U6, 8th pin of operational amplifier U1 connects the 2nd pin of operational amplifier U1 by resistance R5, the 9th pin of operational amplifier U1 is connect by resistance R6, connect the 2nd pin of operational amplifier U2, connect the 1st pin of multiplier U3, connect the 1st pin of multiplier U4, 9th pin of operational amplifier U1 is in parallel by resistance Rx11 and electric capacity Cx11's, connecting resistance Rx12 is in parallel with electric capacity Cx12's, connecting resistance Rx13 and electric capacity Cx13 again in parallel after, connect the 2nd pin of analog switch U5 again, in parallel by resistance Rx21 and electric capacity Cx21, connecting resistance Rx22 is in parallel with electric capacity Cx22's, connecting resistance Rx23 and electric capacity Cx23 again in parallel after, connect the 4th pin of analog switch U5 again, 14th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R1, the 9th pin of operational amplifier U1 is connect by resistance R7,

The 6th of described operational amplifier U2, 7 pins are unsettled, the 3rd of described operational amplifier U2, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 1st pin of operational amplifier U2 passes through the series connection ground connection of resistance R14 and R15, the 8th of analog switch U5 the is connect by R14, 9 pins, 8th pin of operational amplifier U2 connects the 9th pin of operational amplifier U2 by resistance R12, connect the 3rd pin of multiplier U3, connect the 3rd pin of multiplier U6, 9th pin of operational amplifier U2 is in parallel by resistance Rz11 and electric capacity Cz11's, connecting resistance Rz12 is in parallel with electric capacity Cz12's, connecting resistance Rz13 and electric capacity Cz13 again in parallel after, connect the 10th pin of analog switch U5 again, in parallel by resistance Rz21 and electric capacity Cz21, connecting resistance Rz22 is in parallel with electric capacity Cz22's, connecting resistance Rz23 and electric capacity Cz23 again in parallel after, connect the 12nd pin of analog switch U5 again, 14th pin of operational amplifier U2 connects the 13rd pin of operational amplifier U2 by resistance R11, the 9th pin of operational amplifier U2 is connect by resistance R13,

1st pin of described multiplier U3 connects the 8th pin of operational amplifier U1,3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 6th pin of operational amplifier U1 by resistance R9, and the 8th pin meets VCC;

1st pin of described multiplier U4 connects the 8th pin of operational amplifier U1,3rd pin connects the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 13rd pin of operational amplifier U2 by resistance R10, and the 8th pin meets VCC;

1st pin of described analog switch U5 meets VCC, the 16th pin ground connection, the 13rd, 14,15 pins are unsettled, the 3rd pin connects the 8th pin of operational amplifier U1, and the 6th pin connects the 7th pin of operational amplifier U1, and the 11st pin connects the 8th pin of operational amplifier U2;

1st pin of described multiplier U6 connects the 7th pin of operational amplifier U1,3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 13rd pin of operational amplifier U1 by resistance R16, and the 8th pin meets VCC.

The invention has the beneficial effects as follows: the New-type switching method and the circuit that propose a novel chaos system, this is applied to engineering practice provides a kind of new approaches to increasing type that chaos system switches and this chaos system.

Accompanying drawing explanation

Fig. 1 is the circuit connection structure schematic diagram of the preferred embodiment of the present invention.

Fig. 2 and Fig. 3 is the actual connection layout of circuit of the present invention.

Embodiment

Below in conjunction with accompanying drawing and preferred embodiment, the present invention is further described in detail, see Fig. 1-Fig. 3.

1, realize a method for the different classical Qi chaos switched system of fractional-order, it is characterized in that being, comprise the following steps:

(1) equation of classical Qi chaos system i is:

$\left\{\begin{array}{ccc}\mathrm{dx}/\mathrm{dt}=\mathrm{\ρ}(y-x)+\mathrm{yz}& & \\ \mathrm{dy}/\mathrm{dt}=\mathrm{\αx}-y-\mathrm{xz}& i& \mathrm{\ρ}=35,\mathrm{\β}=8/3,\mathrm{\α}=80\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xy}-\mathrm{\βz}& & \end{array}\right.$

The equation of (2) 0.9 rank classical Qi chaos system ii is:

$\left\{\begin{array}{ccc}{d}^{0.9}x/{\mathrm{dt}}^{0.9}=\mathrm{\ρ}(y-x)+\mathrm{yz}& & \\ d^{0.9}y/{\mathrm{dt}}^{0.9}=\mathrm{\αx}-y-\mathrm{xz}& \mathrm{ii}& \mathrm{\ρ}=35,\mathrm{\β}=8/3,\mathrm{\α}=80\\ d^{0.9}z/{\mathrm{dt}}^{0.9}=\mathrm{xy}-\mathrm{\βz}& & \end{array}\right.$

The equation of (3) 0.1 rank classical Qi chaos system iii is:

$\left\{\begin{array}{ccc}{d}^{0.1}x/{\mathrm{dt}}^{0.1}=\mathrm{\ρ}(y-x)+\mathrm{yz}& & \\ d^{0.1}y/{\mathrm{dt}}^{0.1}=\mathrm{\αx}-y-\mathrm{xz}& \mathrm{iii}& \mathrm{\ρ}=35,\mathrm{\β}=8/3,\mathrm{\α}=80\\ d^{0.1}z/{\mathrm{dt}}^{0.1}=\mathrm{xy}-\mathrm{\βz}& & \end{array}\right.$

(4) construct switching function q=f (x), wherein the expression formula iv of f (x) is:

$q=f\left(x\right)=\left\{\begin{array}{cc}0.9& x>0\\ 0.1& x\≤0\end{array}\right.---\mathrm{iv}$

(5) the classical Qi chaos switched system v constructing a kind of fractional-order different by ii, iii and iv is:

$\begin{array}{cc}\left\{\begin{array}{c}{d}^{q}x/{\mathrm{dt}}^q=\mathrm{\ρ}(y-x)+\mathrm{yz}\\ d^{q}y/{\mathrm{dt}}^q=\mathrm{\αx}-y-\mathrm{xz}\\ d^{q}z/{\mathrm{dt}}^q=\mathrm{xy}-\mathrm{\βz}\end{array}\right.& \mathrm{\ρ}=35,\mathrm{\β}=8/3,\mathrm{\α}=80,q=f\left(x\right)=\left\{\begin{array}{cc}0.9& x>0\\ 0.1& x\≤0\end{array}\right.\end{array}---v$

(6) different according to fractional-order Qi chaos switched system v constructing analog Circuits System, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form the fractional order inverting integrator of anti-phase adder and different order, utilize multiplier U3, multiplier U4 and multiplier U6 realizes multiplying, the selection utilizing analog switch U5 to realize analog signal exports, described operational amplifier U1 and operational amplifier U2 adopts LF347D, described multiplier U3, multiplier U4 and multiplier U6 adopts AD633JN, described analog switch U5 adopts ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4, multiplier U6 and analog switch U5, described operational amplifier U2 connects multiplier U3, multiplier U6 and analog switch U5, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2, described analog switch U5 concatenation operation amplifier U1 and operational amplifier U2,

1st pin of described operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance R3, connected with the 6th pin of operational amplifier U1 by resistance R8, the 3rd of operational amplifier U1, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U1 is in parallel by resistance Ry11 and electric capacity Cy11's, connecting resistance Ry12 is in parallel with electric capacity Cy12's, connecting resistance Ry13 and electric capacity Cy13 again in parallel after, connect the 7th pin of analog switch U5 again, in parallel by resistance Ry21 and electric capacity Cy21, connecting resistance Ry22 is in parallel with electric capacity Cy22's, connecting resistance Ry23 and electric capacity Cy23 again in parallel after, connect the 5th pin of analog switch U5 again, 7th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R2, the 6th pin of operational amplifier U1 is connect by resistance R4, connect the 3rd pin of multiplier U4, connect the 1st pin of multiplier U6, 8th pin of operational amplifier U1 connects the 2nd pin of operational amplifier U1 by resistance R5, the 9th pin of operational amplifier U1 is connect by resistance R6, connect the 2nd pin of operational amplifier U2, connect the 1st pin of multiplier U3, connect the 1st pin of multiplier U4, 9th pin of operational amplifier U1 is in parallel by resistance Rx11 and electric capacity Cx11's, connecting resistance Rx12 is in parallel with electric capacity Cx12's, connecting resistance Rx13 and electric capacity Cx13 again in parallel after, connect the 2nd pin of analog switch U5 again, in parallel by resistance Rx21 and electric capacity Cx21, connecting resistance Rx22 is in parallel with electric capacity Cx22's, connecting resistance Rx23 and electric capacity Cx23 again in parallel after, connect the 4th pin of analog switch U5 again, 14th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R1, the 9th pin of operational amplifier U1 is connect by resistance R7,

The 6th of described operational amplifier U2, 7 pins are unsettled, the 3rd of described operational amplifier U2, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 1st pin of operational amplifier U2 passes through the series connection ground connection of resistance R14 and R15, the 8th of analog switch U5 the is connect by R14, 9 pins, 8th pin of operational amplifier U2 connects the 9th pin of operational amplifier U2 by resistance R12, connect the 3rd pin of multiplier U3, connect the 3rd pin of multiplier U6, 9th pin of operational amplifier U2 is in parallel by resistance Rz11 and electric capacity Cz11's, connecting resistance Rz12 is in parallel with electric capacity Cz12's, connecting resistance Rz13 and electric capacity Cz13 again in parallel after, connect the 10th pin of analog switch U5 again, in parallel by resistance Rz21 and electric capacity Cz21, connecting resistance Rz22 is in parallel with electric capacity Cz22's, connecting resistance Rz23 and electric capacity Cz23 again in parallel after, connect the 12nd pin of analog switch U5 again, 14th pin of operational amplifier U2 connects the 13rd pin of operational amplifier U2 by resistance R11, the 9th pin of operational amplifier U2 is connect by resistance R13,

1st pin of described multiplier U3 connects the 8th pin of operational amplifier U1,3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 6th pin of operational amplifier U1 by resistance R9, and the 8th pin meets VCC;

1st pin of described multiplier U4 connects the 8th pin of operational amplifier U1,3rd pin connects the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 13rd pin of operational amplifier U2 by resistance R10, and the 8th pin meets VCC;

1st pin of described analog switch U5 meets VCC, the 16th pin ground connection, the 13rd, 14,15 pins are unsettled, the 3rd pin connects the 8th pin of operational amplifier U1, and the 6th pin connects the 7th pin of operational amplifier U1, and the 11st pin connects the 8th pin of operational amplifier U2;

1st pin of described multiplier U6 connects the 7th pin of operational amplifier U1,3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 13rd pin of operational amplifier U1 by resistance R16, and the 8th pin meets VCC.

2, a kind of circuit realizing the different classical Qi chaos switched system of fractional-order, it is characterized in that being, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form the fractional order inverting integrator of anti-phase adder and different order, utilize multiplier U3, multiplier U4 and multiplier U6 realizes multiplying, the selection utilizing analog switch U5 to realize analog signal exports, described operational amplifier U1 and operational amplifier U2 adopts LF347D, described multiplier U3, multiplier U4 and multiplier U6 adopts AD633JN, described analog switch U5 adopts ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4, multiplier U6 and analog switch U5, described operational amplifier U2 connects multiplier U3, multiplier U6 and analog switch U5, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2, described analog switch U5 concatenation operation amplifier U1 and operational amplifier U2,

1st pin of described operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance R3, connected with the 6th pin of operational amplifier U1 by resistance R8, the 3rd of operational amplifier U1, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U1 is in parallel by resistance Ry11 and electric capacity Cy11's, connecting resistance Ry12 is in parallel with electric capacity Cy12's, connecting resistance Ry13 and electric capacity Cy13 again in parallel after, connect the 7th pin of analog switch U5 again, in parallel by resistance Ry21 and electric capacity Cy21, connecting resistance Ry22 is in parallel with electric capacity Cy22's, connecting resistance Ry23 and electric capacity Cy23 again in parallel after, connect the 5th pin of analog switch U5 again, 7th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R2, the 6th pin of operational amplifier U1 is connect by resistance R4, connect the 3rd pin of multiplier U4, connect the 1st pin of multiplier U6, 8th pin of operational amplifier U1 connects the 2nd pin of operational amplifier U1 by resistance R5, the 9th pin of operational amplifier U1 is connect by resistance R6, connect the 2nd pin of operational amplifier U2, connect the 1st pin of multiplier U3, connect the 1st pin of multiplier U4, 9th pin of operational amplifier U1 is in parallel by resistance Rx11 and electric capacity Cx11's, connecting resistance Rx12 is in parallel with electric capacity Cx12's, connecting resistance Rx13 and electric capacity Cx13 again in parallel after, connect the 2nd pin of analog switch U5 again, in parallel by resistance Rx21 and electric capacity Cx21, connecting resistance Rx22 is in parallel with electric capacity Cx22's, connecting resistance Rx23 and electric capacity Cx23 again in parallel after, connect the 4th pin of analog switch U5 again, 14th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R1, the 9th pin of operational amplifier U1 is connect by resistance R7,

The 6th of described operational amplifier U2, 7 pins are unsettled, the 3rd of described operational amplifier U2, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 1st pin of operational amplifier U2 passes through the series connection ground connection of resistance R14 and R15, the 8th of analog switch U5 the is connect by R14, 9 pins, 8th pin of operational amplifier U2 connects the 9th pin of operational amplifier U2 by resistance R12, connect the 3rd pin of multiplier U3, connect the 3rd pin of multiplier U6, 9th pin of operational amplifier U2 is in parallel by resistance Rz11 and electric capacity Cz11's, connecting resistance Rz12 is in parallel with electric capacity Cz12's, connecting resistance Rz13 and electric capacity Cz13 again in parallel after, connect the 10th pin of analog switch U5 again, in parallel by resistance Rz21 and electric capacity Cz21, connecting resistance Rz22 is in parallel with electric capacity Cz22's, connecting resistance Rz23 and electric capacity Cz23 again in parallel after, connect the 12nd pin of analog switch U5 again, 14th pin of operational amplifier U2 connects the 13rd pin of operational amplifier U2 by resistance R11, the 9th pin of operational amplifier U2 is connect by resistance R13,

1st pin of described multiplier U3 connects the 8th pin of operational amplifier U1,3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 6th pin of operational amplifier U1 by resistance R9, and the 8th pin meets VCC;

1st pin of described multiplier U4 connects the 8th pin of operational amplifier U1,3rd pin connects the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 13rd pin of operational amplifier U2 by resistance R10, and the 8th pin meets VCC;

1st pin of described analog switch U5 meets VCC, the 16th pin ground connection, the 13rd, 14,15 pins are unsettled, the 3rd pin connects the 8th pin of operational amplifier U1, and the 6th pin connects the 7th pin of operational amplifier U1, and the 11st pin connects the 8th pin of operational amplifier U2;

1st pin of described multiplier U6 connects the 7th pin of operational amplifier U1,3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 13rd pin of operational amplifier U1 by resistance R16, and the 8th pin meets VCC.

Resistance R1=R3=R7=R8=R11=R13=10k Ω in circuit, R9=R10=R16=1k Ω, R2=R6=2.86k Ω, R4=100k Ω, R5=1.25k Ω, R12=37.5k Ω, R14=100k Ω, R15=80k Ω, Rx11=Ry11=Rz11=62.84M Ω, Rx12=Ry12=Rz12=250k Ω, Rx13=Ry13=Rz13=2.5k Ω, Rx21=Ry21=Rz21=0.636M Ω, Rx22=Ry22=Rz22=0.3815M Ω, Rx23=Ry23=Rz23=0.5672M Ω, Cx11=Cy11=Cz11=1.2 μ F, Cx12=Cy12=Cz13=1.8 μ F, Cx13=Cy13=Cz13=1.1 μ F, Cx21=Cy21=Cz21=15.75 μ F, Cx22=Cy22=Cz22=0.1575 μ F, Cx23=Cy23=Cz23=633.5nF.

Certainly, above-mentioned explanation is not limitation of the present invention, and the present invention is also not limited only to above-mentioned citing, and the change that those skilled in the art make in essential scope of the present invention, remodeling, interpolation or replacement, also belong to protection scope of the present invention.

Claims (2)

1. realize a method for the different classical Qi chaos switched system of fractional-order, it is characterized in that being, comprise the following steps:

(1) equation of classical Qi chaos system i is:

$\begin{array}{ccc}\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=\mathrm{\ρ}(y-x)+\mathrm{yz}\\ \mathrm{dy}/\mathrm{dt}=\mathrm{\αx}-y-\mathrm{xz}\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xy}-\mathrm{\βz}\end{array}\right.& i& \mathrm{\ρ}=35,\mathrm{\β}=8/3,\mathrm{\α}=80\end{array}$

The equation of (2) 0.9 rank classical Qi chaos system ii is:

$\begin{array}{ccc}\left\{\begin{array}{c}{d}^{0.9}x/{\mathrm{dt}}^{0.9}=\mathrm{\ρ}(y-x)+\mathrm{yz}\\ d^{0.9}y/{\mathrm{dt}}^{0.9}=\mathrm{\αx}-y-\mathrm{xz}\\ d^{0.9}z/{\mathrm{dt}}^{0.9}=\mathrm{xy}-\mathrm{\βz}\end{array}\right.& \mathrm{ii}& \mathrm{\ρ}=35,\mathrm{\β}=8/3,\mathrm{\α}=80\end{array}$

The equation of (3) 0.1 rank classical Qi chaos system iii is:

$\begin{array}{ccc}\left\{\begin{array}{c}{d}^{0.1}x/{\mathrm{dt}}^{0.1}=\mathrm{\ρ}(y-x)+\mathrm{yz}\\ d^{0.1}y/{\mathrm{dt}}^{0.1}=\mathrm{\αx}-y-\mathrm{xz}\\ d^{0.1}z/{\mathrm{dt}}^{0.1}=\mathrm{xy}-\mathrm{\βz}\end{array}\right.& \mathrm{ii}& \mathrm{\ρ}=35,\mathrm{\β}=8/3,\mathrm{\α}=80\end{array}$

(4) construct switching function q=f (x), wherein the expression formula iv of f (x) is:

$q=f\left(x\right)=\left\{\begin{array}{ccc}0.9& x>0& \\ & & \mathrm{iv}\\ 0.1& x\≤0& \end{array}\right.$

(5) the classical Qi chaos switched system v constructing a kind of fractional-order different by ii, iii and iv is:

$\begin{array}{ccc}\left\{\begin{array}{c}{d}^{q}x/{\mathrm{dt}}^q=\mathrm{\ρ}(y-x)+\mathrm{yz}\\ d^{q}y+{\mathrm{dt}}^q=\mathrm{\αx}-y-\mathrm{xz}\\ d^{q}z/{\mathrm{dt}}^q=\mathrm{xy}-\mathrm{\βz}\end{array}\right.& \mathrm{\ρ}=35,\mathrm{\β}=8/3,\mathrm{\α}=80,q=f\left(x\right)=\left\{\begin{array}{cc}0.9& x>0\\ 0.1& x\≤0\end{array}\right.& v\end{array}$

(6) different according to fractional-order classical Qi chaos switched system v constructing analog Circuits System, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form the fractional order inverting integrator of anti-phase adder and different order, utilize multiplier U3, multiplier U4 and multiplier U6 realizes multiplying, the selection utilizing analog switch U5 to realize analog signal exports, described operational amplifier U1 and operational amplifier U2 adopts LF347D, described multiplier U3, multiplier U4 and multiplier U6 adopts AD633JN, described analog switch U5 adopts ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4, multiplier U6 and analog switch U5, described operational amplifier U2 connects multiplier U3, multiplier U6 and analog switch U5, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2, described analog switch U5 concatenation operation amplifier U1 and operational amplifier U2, described multiplier U6 concatenation operation amplifier U1,

1st pin of described operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance R3, connected with the 6th pin of operational amplifier U1 by resistance R8, the 3rd of operational amplifier U1, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U1 is in parallel by resistance Ry11 and electric capacity Cy11's, connecting resistance Ry12 is in parallel with electric capacity Cy12's, connecting resistance Ry13 and electric capacity Cy13 again in parallel after, connect the 7th pin of analog switch U5 again, in parallel by resistance Ry21 and electric capacity Cy21, connecting resistance Ry22 is in parallel with electric capacity Cy22's, connecting resistance Ry23 and electric capacity Cy23 again in parallel after, connect the 5th pin of analog switch U5 again, 7th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R2, the 6th pin of operational amplifier U1 is connect by resistance R4, connect the 3rd pin of multiplier U4, connect the 1st pin of multiplier U6, 8th pin of operational amplifier U1 connects the 2nd pin of operational amplifier U1 by resistance R5, the 9th pin of operational amplifier U1 is connect by resistance R6, connect the 2nd pin of operational amplifier U2, connect the 1st pin of multiplier U3, connect the 1st pin of multiplier U4, 9th pin of operational amplifier U1 is in parallel by resistance Rx11 and electric capacity Cx11's, connecting resistance Rx12 is in parallel with electric capacity Cx12's, connecting resistance Rx13 and electric capacity Cx13 again in parallel after, connect the 2nd pin of analog switch U5 again, in parallel by resistance Rx21 and electric capacity Cx21, connecting resistance Rx22 is in parallel with electric capacity Cx22's, connecting resistance Rx23 and electric capacity Cx23 again in parallel after, connect the 4th pin of analog switch U5 again, 14th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R1, the 9th pin of operational amplifier U1 is connect by resistance R7,

The 6th of described operational amplifier U2, 7 pins are unsettled, the 3rd of described operational amplifier U2, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 1st pin of operational amplifier U2 passes through the series connection ground connection of resistance R14 and R15, the 8th of analog switch U5 the is connect by R14, 9 pins, 8th pin of operational amplifier U2 connects the 9th pin of operational amplifier U2 by resistance R12, connect the 3rd pin of multiplier U3, connect the 3rd pin of multiplier U6, 9th pin of operational amplifier U2 is in parallel by resistance Rz11 and electric capacity Cz11's, connecting resistance Rz12 is in parallel with electric capacity Cz12's, connecting resistance Rz13 and electric capacity Cz13 again in parallel after, connect the 10th pin of analog switch U5 again, in parallel by resistance Rz21 and electric capacity Cz21, connecting resistance Rz22 is in parallel with electric capacity Cz22's, connecting resistance Rz23 and electric capacity Cz23 again in parallel after, connect the 12nd pin of analog switch U5 again, 14th pin of operational amplifier U2 connects the 13rd pin of operational amplifier U2 by resistance R11, the 9th pin of operational amplifier U2 is connect by resistance R13,

1st pin of described multiplier U3 connects the 8th pin of operational amplifier U1,3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 6th pin of operational amplifier U1 by resistance R9, and the 8th pin meets VCC;

1st pin of described multiplier U4 connects the 8th pin of operational amplifier U1,3rd pin connects the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 13rd pin of operational amplifier U2 by resistance R10, and the 8th pin meets VCC;

1st pin of described analog switch U5 meets VCC, the 16th pin ground connection, the 13rd, 14,15 pins are unsettled, the 3rd pin connects the 8th pin of operational amplifier U1, and the 6th pin connects the 7th pin of operational amplifier U1, and the 11st pin connects the 8th pin of operational amplifier U2;

1st pin of described multiplier U6 connects the 7th pin of operational amplifier U1,3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 13rd pin of operational amplifier U1 by resistance R16, and the 8th pin meets VCC.

2. one kind realizes the circuit of the different classical Qi chaos switched system of fractional-order, it is characterized in that being, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form the fractional order inverting integrator of anti-phase adder and different order, utilize multiplier U3, multiplier U4 and multiplier U6 realizes multiplying, the selection utilizing analog switch U5 to realize analog signal exports, described operational amplifier U1 and operational amplifier U2 adopts LF347D, described multiplier U3, multiplier U4 and multiplier U6 adopts AD633JN, described analog switch U5 adopts ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4, multiplier U6 and analog switch U5, described operational amplifier U2 connects multiplier U3, multiplier U6 and analog switch U5, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2, described analog switch U5 concatenation operation amplifier U1 and operational amplifier U2,

1st pin of described operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance R3, connected with the 6th pin of operational amplifier U1 by resistance R8, the 3rd of operational amplifier U1, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U1 is in parallel by resistance Ry11 and electric capacity Cy11's, connecting resistance Ry12 is in parallel with electric capacity Cy12's, connecting resistance Ry13 and electric capacity Cy13 again in parallel after, connect the 7th pin of analog switch U5 again, in parallel by resistance Ry21 and electric capacity Cy21, connecting resistance Ry22 is in parallel with electric capacity Cy22's, connecting resistance Ry23 and electric capacity Cy23 again in parallel after, connect the 5th pin of analog switch U5 again, 7th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R2, the 6th pin of operational amplifier U1 is connect by resistance R4, connect the 3rd pin of multiplier U4, connect the 1st pin of multiplier U6, 8th pin of operational amplifier U1 connects the 2nd pin of operational amplifier U1 by resistance R5, the 9th pin of operational amplifier U1 is connect by resistance R6, connect the 2nd pin of operational amplifier U2, connect the 1st pin of multiplier U3, connect the 1st pin of multiplier U4, 9th pin of operational amplifier U1 is in parallel by resistance Rx11 and electric capacity Cx11's, connecting resistance Rx12 is in parallel with electric capacity Cx12's, connecting resistance Rx13 and electric capacity Cx13 again in parallel after, connect the 2nd pin of analog switch U5 again, in parallel by resistance Rx21 and electric capacity Cx21, connecting resistance Rx22 is in parallel with electric capacity Cx22's, connecting resistance Rx23 and electric capacity Cx23 again in parallel after, connect the 4th pin of analog switch U5 again, 14th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R1, the 9th pin of operational amplifier U1 is connect by resistance R7,

The 6th of described operational amplifier U2, 7 pins are unsettled, the 3rd of described operational amplifier U2, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 1st pin of operational amplifier U2 passes through the series connection ground connection of resistance R14 and R15, the 8th of analog switch U5 the is connect by R14, 9 pins, 8th pin of operational amplifier U2 connects the 9th pin of operational amplifier U2 by resistance R12, connect the 3rd pin of multiplier U3, connect the 3rd pin of multiplier U6, 9th pin of operational amplifier U2 is in parallel by resistance Rz11 and electric capacity Cz11's, connecting resistance Rz12 is in parallel with electric capacity Cz12's, connecting resistance Rz13 and electric capacity Cz13 again in parallel after, connect the 10th pin of analog switch U5 again, in parallel by resistance Rz21 and electric capacity Cz21, connecting resistance Rz22 is in parallel with electric capacity Cz22's, connecting resistance Rz23 and electric capacity Cz23 again in parallel after, connect the 12nd pin of analog switch U5 again, 14th pin of operational amplifier U2 connects the 13rd pin of operational amplifier U2 by resistance R11, the 9th pin of operational amplifier U2 is connect by resistance R13,

1st pin of described multiplier U3 connects the 8th pin of operational amplifier U1,3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 6th pin of operational amplifier U1 by resistance R9, and the 8th pin meets VCC;

1st pin of described multiplier U4 connects the 8th pin of operational amplifier U1,3rd pin connects the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 13rd pin of operational amplifier U2 by resistance R10, and the 8th pin meets VCC;

1st pin of described analog switch U5 meets VCC, the 16th pin ground connection, the 13rd, 14,15 pins are unsettled, the 3rd pin connects the 8th pin of operational amplifier U1, and the 6th pin connects the 7th pin of operational amplifier U1, and the 11st pin connects the 8th pin of operational amplifier U2;

1st pin of described multiplier U6 connects the 7th pin of operational amplifier U1,3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 13rd pin of operational amplifier U1 by resistance R16, and the 8th pin meets VCC.