CN103916232B - Switching method and circuit of Lu chaotic system with different fractional orders and y<2> - Google Patents

Abstract

The invention provides a switching method and circuit of Lu chaotic system with different fractional orders and y<2>. An operational amplifier U1, an operational amplifier U2, a resistor and a capacitor constitute an inverter summator and different-order fractional order inverted integrator, a multiplying unit U3 and a multiplying unit U4 are adopted to achieve multiplying, and an analog switch U5 is adopted to achieve selective output of analog signals, wherein LF347Ds serve as the operational amplifier U1 and the operational amplifier U2, AD633JNs serve as the multiplying unit U3 and the multiplying unit U4, an ADG888 serves as the analog switch U5, the operational amplifier U1 is connected with the multiplying unit U3, the multiplying unit U4 and the analog switch U5, the operational amplifier U2 is connected with the multiplying unit U3 and the analog switch U5, the multiplying unit U3 is connected with the operational amplifier U1, the multiplying unit U4 is connected with the operational amplifier U2, and the analog switch U5 is connected with the operational amplifier U1 and the operational amplifier U2. The novel switching method and circuit of the novel chaotic system provide a new idea for increasing of chaotic system switching types and the application of the chaotic system to engineering practice.

Description

What a kind of fractional-order was different contains y 2l ü chaos switched system method and circuit

Technical field

The present invention relates to a chaos system and circuit realiration, what particularly a kind of fractional-order was different contains y ²'s chaos switched system method and circuit.

Background technology

At present, method and the main circuit of the switching chaos system that oneself has will comprise the switching between different linear term in chaos system or nonlinear terms, and based on the fractional order form of these 2 kinds of switch modes, also be not suggested about the changing method of the chaotic systems with fractional order of different order and circuit, the present invention proposes a kind of fractional-order different containing y ²'s chaos switched system method and circuit, the present invention proposes New-type switching method and the circuit of a novel chaos system, and this is applied to engineering practice provides a kind of new approaches to increasing type that chaos system switches and this chaos system.

Summary of the invention

The technical problem to be solved in the present invention be to provide a kind of fractional-order different containing y ²'s chaos switched system method and circuit, the present invention adopts following technological means to realize goal of the invention:

What 1, a kind of fractional-order was different contains y ²'s chaos switched system method, is characterized in that being, comprises the following steps:

(1) containing y ²'s the equation of chaos system i is:

$\left\{\begin{array}{ccc}\mathrm{dx}/\mathrm{dt}=a(y-x)& & \\ \mathrm{dy}/\mathrm{dt}=\mathrm{cy}-\mathrm{cz}& i& a=36,b=3,c=22\\ \mathrm{dz}/\mathrm{dt}=y^2-\mathrm{bz}& & \end{array}\right.$

(2) 0.9 rank are containing y ²'s the equation of chaos system ii is:

$\left\{\begin{array}{ccc}{d}^{0.9}x/{\mathrm{dt}}^{0.9}=a(y-x)& & \\ d^{0.9}y/{\mathrm{dt}}^{0.9}=\mathrm{cy}-\mathrm{xz}& \mathrm{ii}& d=36,b=3,c=22\\ d^{0.9}z/{\mathrm{dt}}^{0.9}=y^2-\mathrm{bz}& & \end{array}\right.$

(3) 0.1 rank are containing y ²'s the equation of chaos system iii is:

$\left\{\begin{array}{ccc}{d}^{0.1}x/{\mathrm{dt}}^{0.1}=a(y-x)& & \\ d^{0.1}y/{\mathrm{dt}}^{0.1}=\mathrm{cy}-\mathrm{xz}& \mathrm{iii}& a=36,b=3,c=22\\ d^{0.1}z/{\mathrm{dt}}^{0.1}=y^2-\mathrm{bz}& & \end{array}\right.$

(4) construct switching function q=f (x), wherein the expression formula iv of f (x) is:

$q=f\left(x\right)=\left\{\begin{array}{cc}\begin{array}{cc}0.9& x>0\\ 0.1& x\&le;0\end{array}& \mathrm{iv}\end{array}\right.$

(5) by ii, iii and iv construct a kind of fractional-order different containing y ²'s chaos switched system v is:

$\left\{\begin{array}{cc}{d}^{q}x/{\mathrm{dt}}^q=a(y-x)& \\ d^{q}y/{\mathrm{dt}}^q=\mathrm{cy}-\mathrm{xz}& a=36,b=3,c=22,q=f\left(x\right)=\left\{\begin{array}{cc}\begin{array}{cc}0.9& x>0\\ 0.1& x\&le;0\end{array}& v\end{array}\right.\\ d^{q}z/{\mathrm{dt}}^q=y^2-\mathrm{bz}& \end{array}\right.$

(6) according to fractional-order different containing y ²'s chaos switched system v constructing analog Circuits System, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form the fractional order inverting integrator of anti-phase adder and different order, multiplier U3 and multiplier U4 is utilized to realize multiplying, the selection utilizing analog switch U5 to realize analog signal exports, described operational amplifier U1 and operational amplifier U2 adopts LF347D, described multiplier U3 and multiplier U4 adopts AD633JN, described analog switch U5 adopts ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4 and analog switch U5, described operational amplifier U2 connects multiplier U3 and analog switch U5, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2, described analog switch U5 concatenation operation amplifier U1 and operational amplifier U2,

1st pin of described operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance R3, connected with the 6th pin of operational amplifier U1 by resistance R7, the 3rd of operational amplifier U1, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U1 is in parallel by resistance Ry11 and electric capacity Cy11's, connecting resistance Ry12 is in parallel with electric capacity Cy12's, connecting resistance Ry13 and electric capacity Cy13 again in parallel after, connect the 7th pin of analog switch U5 again, in parallel by resistance Ry21 and electric capacity Cy21, connecting resistance Ry22 is in parallel with electric capacity Cy22's, connecting resistance Ry23 and electric capacity Cy23 again in parallel after, connect the 5th pin of analog switch U5 again, 7th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R2, the 2nd pin of operational amplifier U1 is connect by resistance R4, connect the 1st of multiplier U4 the, 3 pins, 8th pin of operational amplifier U1 connects the 9th pin of operational amplifier U1 by resistance R5, connect the 2nd pin of operational amplifier U2, connect the 1st pin of multiplier U3, 9th pin of operational amplifier U1 is in parallel by resistance Rx11 and electric capacity Cx11's, connecting resistance Rx12 is in parallel with electric capacity Cx12's, connecting resistance Rx13 and electric capacity Cx13 again in parallel after, connect the 2nd pin of analog switch U5 again, in parallel by resistance Rx21 and electric capacity Cx21, connecting resistance Rx22 is in parallel with electric capacity Cx22's, connecting resistance Rx23 and electric capacity Cx23 again in parallel after, connect the 4th pin of analog switch U5 again, 14th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R1, the 9th pin of operational amplifier U1 is connect by resistance R6,

The 6th of described operational amplifier U2, 7 pins are unsettled, the 3rd of described operational amplifier U2, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 1st pin of operational amplifier U2 passes through the series connection ground connection of resistance R13 and R14, the 8th of analog switch U5 the is connect by R13, 9 pins, 8th pin of operational amplifier U2 connects the 9th pin of operational amplifier U2 by resistance R11, connect the 3rd pin of multiplier U3, 9th pin of operational amplifier U2 is in parallel by resistance Rz11 and electric capacity Cz11's, connecting resistance Rz12 is in parallel with electric capacity Cz12's, connecting resistance Rz13 and electric capacity Cz13 again in parallel after, connect the 10th pin of analog switch U5 again, in parallel by resistance Rz21 and electric capacity Cz21, connecting resistance Rz22 is in parallel with electric capacity Cz22's, connecting resistance Rz23 and electric capacity Cz23 again in parallel after, connect the 12nd pin of analog switch U5 again, 14th pin of operational amplifier U2 connects the 13rd pin of operational amplifier U2 by resistance R10, the 9th pin of operational amplifier U2 is connect by resistance R12,

1st pin of described multiplier U3 connects the 8th pin of operational amplifier U1,3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 6th pin of operational amplifier U1 by resistance R8, and the 8th pin meets VCC;

Described multiplier U4 the 1st, 3 pins connect the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, the 5th pin meets VEE, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance R9, and the 8th pin meets VCC;

1st pin of described analog switch U5 meets VCC, the 16th pin ground connection, the 13rd, 14,15 pins are unsettled, the 3rd pin connects the 8th pin of operational amplifier U1, and the 6th pin connects the 7th pin of operational amplifier U1, and the 11st pin connects the 8th pin of operational amplifier U2.

What 2, a kind of fractional-order was different contains y ²'s chaos switched system circuit, it is characterized in that being, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form the fractional order inverting integrator of anti-phase adder and different order, multiplier U3 and multiplier U4 is utilized to realize multiplying, the selection utilizing analog switch U5 to realize analog signal exports, described operational amplifier U1 and operational amplifier U2 adopts LF347D, described multiplier U3 and multiplier U4 adopts AD633JN, described analog switch U5 adopts ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4 and analog switch U5, described operational amplifier U2 connects multiplier U3 and analog switch U5, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2, described analog switch U5 concatenation operation amplifier U1 and operational amplifier U2,

1st pin of described operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance R3, connected with the 6th pin of operational amplifier U1 by resistance R7, the 3rd of operational amplifier U1, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U1 is in parallel by resistance Ry11 and electric capacity Cy11's, connecting resistance Ry12 is in parallel with electric capacity Cy12's, connecting resistance Ry13 and electric capacity Cy13 again in parallel after, connect the 7th pin of analog switch U5 again, in parallel by resistance Ry21 and electric capacity Cy21, connecting resistance Ry22 is in parallel with electric capacity Cy22's, connecting resistance Ry23 and electric capacity Cy23 again in parallel after, connect the 5th pin of analog switch U5 again, 7th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R2, the 2nd pin of operational amplifier U1 is connect by resistance R4, connect the 1st of multiplier U4 the, 3 pins, 8th pin of operational amplifier U1 connects the 9th pin of operational amplifier U1 by resistance R5, connect the 2nd pin of operational amplifier U2, connect the 1st pin of multiplier U3, 9th pin of operational amplifier U1 is in parallel by resistance Rx11 and electric capacity Cx11's, connecting resistance Rx12 is in parallel with electric capacity Cx12's, connecting resistance Rx13 and electric capacity Cx13 again in parallel after, connect the 2nd pin of analog switch U5 again, in parallel by resistance Rx21 and electric capacity Cx21, connecting resistance Rx22 is in parallel with electric capacity Cx22's, connecting resistance Rx23 and electric capacity Cx23 again in parallel after, connect the 4th pin of analog switch U5 again, 14th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R1, the 9th pin of operational amplifier U1 is connect by resistance R6,

The 6th of described operational amplifier U2, 7 pins are unsettled, the 3rd of described operational amplifier U2, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 1st pin of operational amplifier U2 passes through the series connection ground connection of resistance R13 and R14, the 8th of analog switch U5 the is connect by R13, 9 pins, 8th pin of operational amplifier U2 connects the 9th pin of operational amplifier U2 by resistance R11, connect the 3rd pin of multiplier U3, 9th pin of operational amplifier U2 is in parallel by resistance Rz11 and electric capacity Cz11's, connecting resistance Rz12 is in parallel with electric capacity Cz12's, connecting resistance Rz13 and electric capacity Cz13 again in parallel after, connect the 10th pin of analog switch U5 again, in parallel by resistance Rz21 and electric capacity Cz21, connecting resistance Rz22 is in parallel with electric capacity Cz22's, connecting resistance Rz23 and electric capacity Cz23 again in parallel after, connect the 12nd pin of analog switch U5 again, 14th pin of operational amplifier U2 connects the 13rd pin of operational amplifier U2 by resistance R10, the 9th pin of operational amplifier U2 is connect by resistance R12,

1st pin of described multiplier U3 connects the 8th pin of operational amplifier U1,3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 6th pin of operational amplifier U1 by resistance R8, and the 8th pin meets VCC;

Described multiplier U4 the 1st, 3 pins connect the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, the 5th pin meets VEE, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance R9, and the 8th pin meets VCC;

1st pin of described analog switch U5 meets VCC, the 16th pin ground connection, the 13rd, 14,15 pins are unsettled, the 3rd pin connects the 8th pin of operational amplifier U1, and the 6th pin connects the 7th pin of operational amplifier U1, and the 11st pin connects the 8th pin of operational amplifier U2.

The invention has the beneficial effects as follows: the New-type switching method and the circuit that propose a novel chaos system, this is applied to engineering practice provides a kind of new approaches to increasing type that chaos system switches and this chaos system.

Accompanying drawing explanation

Fig. 1 is the circuit connection structure schematic diagram of the preferred embodiment of the present invention.

Fig. 2 and Fig. 3 is the actual connection layout of circuit of the present invention.

Embodiment

Below in conjunction with accompanying drawing and preferred embodiment, the present invention is further described in detail, see Fig. 1-Fig. 3.

What 1, a kind of fractional-order was different contains y ²'s chaos switched system method, is characterized in that being, comprises the following steps:

(1) containing y ²'s the equation of chaos system i is:

$\left\{\begin{array}{ccc}\mathrm{dx}/\mathrm{dt}=a(y-x)& & \\ \mathrm{dy}/\mathrm{dt}=\mathrm{cy}-\mathrm{cz}& i& a=36,b=3,c=22\\ \mathrm{dz}/\mathrm{dt}=y^2-\mathrm{bz}& & \end{array}\right.$

(2) 0.9 rank are containing y ²'s the equation of chaos system ii is:

$\left\{\begin{array}{ccc}{d}^{0.9}x/{\mathrm{dt}}^{0.9}=a(y-x)& & \\ d^{0.9}y/{\mathrm{dt}}^{0.9}=\mathrm{cy}-\mathrm{xz}& \mathrm{ii}& d=36,b=3,c=22\\ d^{0.9}z/{\mathrm{dt}}^{0.9}=y^2-\mathrm{bz}& & \end{array}\right.$

(3) 0.1 rank are containing y ²'s the equation of chaos system iii is:

$\left\{\begin{array}{ccc}{d}^{0.1}x/{\mathrm{dt}}^{0.1}=a(y-x)& & \\ d^{0.1}y/{\mathrm{dt}}^{0.1}=\mathrm{cy}-\mathrm{xz}& \mathrm{iii}& a=36,b=3,c=22\\ d^{0.1}z/{\mathrm{dt}}^{0.1}=y^2-\mathrm{bz}& & \end{array}\right.$

(4) construct switching function q=f (x), wherein the expression formula iv of f (x) is:

$q=f\left(x\right)=\left\{\begin{array}{cc}\begin{array}{cc}0.9& x>0\\ 0.1& x\&le;0\end{array}& \mathrm{iv}\end{array}\right.$

(5) by ii, iii and iv construct a kind of fractional-order different containing y ²'s chaos switched system v is:

$\left\{\begin{array}{cc}{d}^{q}x/{\mathrm{dt}}^q=a(y-x)& \\ d^{q}y/{\mathrm{dt}}^q=\mathrm{cy}-\mathrm{xz}& a=36,b=3,c=22,q=f\left(x\right)=\left\{\begin{array}{cc}\begin{array}{cc}0.9& x>0\\ 0.1& x\&le;0\end{array}& v\end{array}\right.\\ d^{q}z/{\mathrm{dt}}^q=y^2-\mathrm{bz}& \end{array}\right.$

(6) according to fractional-order different containing y ²'s chaos switched system v constructing analog Circuits System, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form the fractional order inverting integrator of anti-phase adder and different order, multiplier U3 and multiplier U4 is utilized to realize multiplying, the selection utilizing analog switch U5 to realize analog signal exports, described operational amplifier U1 and operational amplifier U2 adopts LF347D, described multiplier U3 and multiplier U4 adopts AD633JN, described analog switch U5 adopts ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4 and analog switch U5, described operational amplifier U2 connects multiplier U3 and analog switch U5, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2, described analog switch U5 concatenation operation amplifier U1 and operational amplifier U2,

1st pin of described operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance R3, connected with the 6th pin of operational amplifier U1 by resistance R7, the 3rd of operational amplifier U1, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U1 is in parallel by resistance Ry11 and electric capacity Cy11's, connecting resistance Ry12 is in parallel with electric capacity Cy12's, connecting resistance Ry13 and electric capacity Cy13 again in parallel after, connect the 7th pin of analog switch U5 again, in parallel by resistance Ry21 and electric capacity Cy21, connecting resistance Ry22 is in parallel with electric capacity Cy22's, connecting resistance Ry23 and electric capacity Cy23 again in parallel after, connect the 5th pin of analog switch U5 again, 7th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R2, the 2nd pin of operational amplifier U1 is connect by resistance R4, connect the 1st of multiplier U4 the, 3 pins, 8th pin of operational amplifier U1 connects the 9th pin of operational amplifier U1 by resistance R5, connect the 2nd pin of operational amplifier U2, connect the 1st pin of multiplier U3, 9th pin of operational amplifier U1 is in parallel by resistance Rx11 and electric capacity Cx11's, connecting resistance Rx12 is in parallel with electric capacity Cx12's, connecting resistance Rx13 and electric capacity Cx13 again in parallel after, connect the 2nd pin of analog switch U5 again, in parallel by resistance Rx21 and electric capacity Cx21, connecting resistance Rx22 is in parallel with electric capacity Cx22's, connecting resistance Rx23 and electric capacity Cx23 again in parallel after, connect the 4th pin of analog switch U5 again, 14th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R1, the 9th pin of operational amplifier U1 is connect by resistance R6,

The 6th of described operational amplifier U2, 7 pins are unsettled, the 3rd of described operational amplifier U2, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 1st pin of operational amplifier U2 passes through the series connection ground connection of resistance R13 and R14, the 8th of analog switch U5 the is connect by R13, 9 pins, 8th pin of operational amplifier U2 connects the 9th pin of operational amplifier U2 by resistance R11, connect the 3rd pin of multiplier U3, 9th pin of operational amplifier U2 is in parallel by resistance Rz11 and electric capacity Cz11's, connecting resistance Rz12 is in parallel with electric capacity Cz12's, connecting resistance Rz13 and electric capacity Cz13 again in parallel after, connect the 10th pin of analog switch U5 again, in parallel by resistance Rz21 and electric capacity Cz21, connecting resistance Rz22 is in parallel with electric capacity Cz22's, connecting resistance Rz23 and electric capacity Cz23 again in parallel after, connect the 12nd pin of analog switch U5 again, 14th pin of operational amplifier U2 connects the 13rd pin of operational amplifier U2 by resistance R10, the 9th pin of operational amplifier U2 is connect by resistance R12,

1st pin of described multiplier U3 connects the 8th pin of operational amplifier U1,3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 6th pin of operational amplifier U1 by resistance R8, and the 8th pin meets VCC;

Described multiplier U4 the 1st, 3 pins connect the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, the 5th pin meets VEE, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance R9, and the 8th pin meets VCC;

1st pin of described analog switch U5 meets VCC, the 16th pin ground connection, the 13rd, 14,15 pins are unsettled, the 3rd pin connects the 8th pin of operational amplifier U1, and the 6th pin connects the 7th pin of operational amplifier U1, and the 11st pin connects the 8th pin of operational amplifier U2.

What 2, a kind of fractional-order was different contains y ²'s chaos switched system circuit, it is characterized in that being, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form the fractional order inverting integrator of anti-phase adder and different order, multiplier U3 and multiplier U4 is utilized to realize multiplying, the selection utilizing analog switch U5 to realize analog signal exports, described operational amplifier U1 and operational amplifier U2 adopts LF347D, described multiplier U3 and multiplier U4 adopts AD633JN, described analog switch U5 adopts ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4 and analog switch U5, described operational amplifier U2 connects multiplier U3 and analog switch U5, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2, described analog switch U5 concatenation operation amplifier U1 and operational amplifier U2,

1st pin of described operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance R3, connected with the 6th pin of operational amplifier U1 by resistance R7, the 3rd of operational amplifier U1, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U1 is in parallel by resistance Ry11 and electric capacity Cy11's, connecting resistance Ry12 is in parallel with electric capacity Cy12's, connecting resistance Ry13 and electric capacity Cy13 again in parallel after, connect the 7th pin of analog switch U5 again, in parallel by resistance Ry21 and electric capacity Cy21, connecting resistance Ry22 is in parallel with electric capacity Cy22's, connecting resistance Ry23 and electric capacity Cy23 again in parallel after, connect the 5th pin of analog switch U5 again, 7th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R2, the 2nd pin of operational amplifier U1 is connect by resistance R4, connect the 1st of multiplier U4 the, 3 pins, 8th pin of operational amplifier U1 connects the 9th pin of operational amplifier U1 by resistance R5, connect the 2nd pin of operational amplifier U2, connect the 1st pin of multiplier U3, 9th pin of operational amplifier U1 is in parallel by resistance Rx11 and electric capacity Cx11's, connecting resistance Rx12 is in parallel with electric capacity Cx12's, connecting resistance Rx13 and electric capacity Cx13 again in parallel after, connect the 2nd pin of analog switch U5 again, in parallel by resistance Rx21 and electric capacity Cx21, connecting resistance Rx22 is in parallel with electric capacity Cx22's, connecting resistance Rx23 and electric capacity Cx23 again in parallel after, connect the 4th pin of analog switch U5 again, 14th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R1, the 9th pin of operational amplifier U1 is connect by resistance R6,

The 6th of described operational amplifier U2, 7 pins are unsettled, the 3rd of described operational amplifier U2, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 1st pin of operational amplifier U2 passes through the series connection ground connection of resistance R13 and R14, the 8th of analog switch U5 the is connect by R13, 9 pins, 8th pin of operational amplifier U2 connects the 9th pin of operational amplifier U2 by resistance R11, connect the 3rd pin of multiplier U3, 9th pin of operational amplifier U2 is in parallel by resistance Rz11 and electric capacity Cz11's, connecting resistance Rz12 is in parallel with electric capacity Cz12's, connecting resistance Rz13 and electric capacity Cz13 again in parallel after, connect the 10th pin of analog switch U5 again, in parallel by resistance Rz21 and electric capacity Cz21, connecting resistance Rz22 is in parallel with electric capacity Cz22's, connecting resistance Rz23 and electric capacity Cz23 again in parallel after, connect the 12nd pin of analog switch U5 again, 14th pin of operational amplifier U2 connects the 13rd pin of operational amplifier U2 by resistance R10, the 9th pin of operational amplifier U2 is connect by resistance R12,

1st pin of described multiplier U3 connects the 8th pin of operational amplifier U1,3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 6th pin of operational amplifier U1 by resistance R8, and the 8th pin meets VCC;

Described multiplier U4 the 1st, 3 pins connect the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, the 5th pin meets VEE, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance R9, and the 8th pin meets VCC;

1st pin of described analog switch U5 meets VCC, the 16th pin ground connection, the 13rd, 14,15 pins are unsettled, the 3rd pin connects the 8th pin of operational amplifier U1, and the 6th pin connects the 7th pin of operational amplifier U1, and the 11st pin connects the 8th pin of operational amplifier U2.

Resistance R1=R3=R6=R7=R10=R12=10k Ω in circuit, R8=R9=1k Ω, R4=4.5k Ω, R2=R5=2.7k Ω, R11=33.3k Ω, R13=100k Ω, R14=80k Ω, Rx11=Ry11=Rz11=62.84M Ω, Rx12=Ry12=Rz12=250k Ω, Rx13=Ry13=Rz13=2.5k Ω, Rx21=Ry21=Rz21=0.636M Ω, Rx22=Ry22=Rz22=0.3815M Ω, Rx23=Ry23=Rz23=0.5672M Ω, Cx11=Cy11=Cz11=1.2 μ F, Cx12=Cy12=Cz13=1.8 μ F, Cx13=Cy13=Cz13=1.1 μ F, Cx21=Cy21=Cz21=15.75 μ F, Cx22=Cy22=Cz22=0.1575 μ F, Cx23=Cy23=Cz23=633.5nF.

Certainly, above-mentioned explanation is not limitation of the present invention, and the present invention is also not limited only to above-mentioned citing, and the change that those skilled in the art make in essential scope of the present invention, remodeling, interpolation or replacement, also belong to protection scope of the present invention.

Claims (2)

1. a fractional-order different containing y ²l ü chaos switched system method, it is characterized in that being, comprise the following steps:

(1) containing y ²the equation of L ü chaos system i be:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{cy}-\mathrm{xz}\\ \mathrm{dz}/\mathrm{dt}=y^2-\mathrm{bz}\end{array}\right.---i$ a＝36,b＝3,c＝22

(2) 0.9 rank are containing y ²the equation of L ü chaos system ii be:

$\left\{\begin{array}{c}{d}^{0.9}x/{\mathrm{dt}}^{0.9}=a(y-x)\\ d^{0.9}y/{\mathrm{dt}}^{0.9}=\mathrm{cy}-\mathrm{xz}\\ d^{0.9}z/{\mathrm{dt}}^{0.9}=y^2-\mathrm{bz}\end{array}\right.---\mathrm{ii}$ a＝36,b＝3,c＝22

(3) 0.1 rank are containing y ²the equation of L ü chaos system iii be:

$\left\{\begin{array}{c}{d}^{0.1}x/{\mathrm{dt}}^{0.1}=a(y-x)\\ d^{0.1}y/{\mathrm{dt}}^{0.1}=\mathrm{cy}-\mathrm{xz}\\ d^{0.1}z/{\mathrm{dt}}^{0.1}=y^2-\mathrm{bz}\end{array}\right.---\mathrm{iii}$ a＝36,b＝3,c＝22

(4) construct switching function q=f (x), wherein the expression formula iv of f (x) is:

$q=f\left(x\right)=\left\{\begin{array}{cc}0.9& x>0\\ 0.1& x\&le;0\end{array}\right.---\mathrm{iv}$

(5) by ii, iii and iv construct a kind of fractional-order different containing y ²l ü chaos switched system v be:

$\left\{\begin{array}{c}{d}^{q}x/{\mathrm{dt}}^q=a(y-x)\\ d^{q}y/{\mathrm{dt}}^q=\mathrm{cy}-\mathrm{xz}\\ d^{q}z/{\mathrm{dt}}^q=y^2-\mathrm{bz}\end{array}\right.$ a＝36,b＝3,c＝22, $q=f\left(x\right)=\left\{\begin{array}{cc}0.9& x>0\\ 0.1& x\&le;0\end{array}\right.---v$

(6) according to fractional-order different containing y ²l ü chaos switched system v constructing analog Circuits System, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form the fractional order inverting integrator of anti-phase adder and different order, multiplier U3 and multiplier U4 is utilized to realize multiplying, the selection utilizing analog switch U5 to realize analog signal exports, described operational amplifier U1 and operational amplifier U2 adopts LF347D, described multiplier U3 and multiplier U4 adopts AD633JN, described analog switch U5 adopts ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4 and analog switch U5, described operational amplifier U2 connects multiplier U3 and analog switch U5, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2, described analog switch U5 concatenation operation amplifier U1 and operational amplifier U2,

1st pin of described operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance R3, connected with the 6th pin of operational amplifier U1 by resistance R7, the 3rd of operational amplifier U1, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U1 is in parallel by resistance Ry11 and electric capacity Cy11's, connecting resistance Ry12 is in parallel with electric capacity Cy12's, connecting resistance Ry13 and electric capacity Cy13 again in parallel after, connect the 7th pin of analog switch U5 again, in parallel by resistance Ry21 and electric capacity Cy21, connecting resistance Ry22 is in parallel with electric capacity Cy22's, connecting resistance Ry23 and electric capacity Cy23 again in parallel after, connect the 5th pin of analog switch U5 again, 7th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R2, the 2nd pin of operational amplifier U1 is connect by resistance R4, connect the 1st of multiplier U4 the, 3 pins, 8th pin of operational amplifier U1 connects the 9th pin of operational amplifier U1 by resistance R5, connect the 2nd pin of operational amplifier U2, connect the 1st pin of multiplier U3, 9th pin of operational amplifier U1 is in parallel by resistance Rx11 and electric capacity Cx11's, connecting resistance Rx12 is in parallel with electric capacity Cx12's, connecting resistance Rx13 and electric capacity Cx13 again in parallel after, connect the 2nd pin of analog switch U5 again, in parallel by resistance Rx21 and electric capacity Cx21, connecting resistance Rx22 is in parallel with electric capacity Cx22's, connecting resistance Rx23 and electric capacity Cx23 again in parallel after, connect the 4th pin of analog switch U5 again, 14th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R1, the 9th pin of operational amplifier U1 is connect by resistance R6,

The 6th of described operational amplifier U2, 7 pins are unsettled, the 3rd of described operational amplifier U2, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 1st pin of operational amplifier U2 passes through the series connection ground connection of resistance R13 and R14, the 8th of analog switch U5 the is connect by R13, 9 pins, 8th pin of operational amplifier U2 connects the 9th pin of operational amplifier U2 by resistance R11, connect the 3rd pin of multiplier U3, 9th pin of operational amplifier U2 is in parallel by resistance Rz11 and electric capacity Cz11's, connecting resistance Rz12 is in parallel with electric capacity Cz12's, connecting resistance Rz13 and electric capacity Cz13 again in parallel after, connect the 10th pin of analog switch U5 again, in parallel by resistance Rz21 and electric capacity Cz21, connecting resistance Rz22 is in parallel with electric capacity Cz22's, connecting resistance Rz23 and electric capacity Cz23 again in parallel after, connect the 12nd pin of analog switch U5 again, 14th pin of operational amplifier U2 connects the 13rd pin of operational amplifier U2 by resistance R10, the 9th pin of operational amplifier U2 is connect by resistance R12,

1st pin of described multiplier U3 connects the 8th pin of operational amplifier U1,3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 6th pin of operational amplifier U1 by resistance R8, and the 8th pin meets VCC;

Described multiplier U4 the 1st, 3 pins connect the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, the 5th pin meets VEE, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance R9, and the 8th pin meets VCC;

1st pin of described analog switch U5 meets VCC, the 16th pin ground connection, the 13rd, 14,15 pins are unsettled, the 3rd pin connects the 8th pin of operational amplifier U1, and the 6th pin connects the 7th pin of operational amplifier U1, and the 11st pin connects the 8th pin of operational amplifier U2.

2. a fractional-order different containing y ²l ü chaos switched system circuit, it is characterized in that being, fractional-order different containing y ²l ü chaos switched system equation be:

$\left\{\begin{array}{c}{d}^{q}x/{\mathrm{dt}}^q=a(y-x)\\ d^{q}y/{\mathrm{dt}}^q=\mathrm{cy}-\mathrm{xz}\\ d^{q}z/{\mathrm{dt}}^q=y^2-\mathrm{bz}\end{array}\right.$ a＝36,b＝3,c＝22, $q=f\left(x\right)=\left\{\begin{array}{cc}0.9& x>0\\ 0.1& x\&le;0\end{array}\right.---v$

According to system equation v constructing analog circuit, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form the fractional order inverting integrator of anti-phase adder and different order, multiplier U3 and multiplier U4 is utilized to realize multiplying, the selection utilizing analog switch U5 to realize analog signal exports, described operational amplifier U1 and operational amplifier U2 adopts LF347D, described multiplier U3 and multiplier U4 adopts AD633JN, described analog switch U5 adopts ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4 and analog switch U5, described operational amplifier U2 connects multiplier U3 and analog switch U5, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2, described analog switch U5 concatenation operation amplifier U1 and operational amplifier U2,

1st pin of described operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance R3, connected with the 6th pin of operational amplifier U1 by resistance R7, the 3rd of operational amplifier U1, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U1 is in parallel by resistance Ry11 and electric capacity Cy11's, connecting resistance Ry12 is in parallel with electric capacity Cy12's, connecting resistance Ry13 and electric capacity Cy13 again in parallel after, connect the 7th pin of analog switch U5 again, in parallel by resistance Ry21 and electric capacity Cy21, connecting resistance Ry22 is in parallel with electric capacity Cy22's, connecting resistance Ry23 and electric capacity Cy23 again in parallel after, connect the 5th pin of analog switch U5 again, 7th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R2, the 2nd pin of operational amplifier U1 is connect by resistance R4, connect the 1st of multiplier U4 the, 3 pins, 8th pin of operational amplifier U1 connects the 9th pin of operational amplifier U1 by resistance R5, connect the 2nd pin of operational amplifier U2, connect the 1st pin of multiplier U3, 9th pin of operational amplifier U1 is in parallel by resistance Rx11 and electric capacity Cx11's, connecting resistance Rx12 is in parallel with electric capacity Cx12's, connecting resistance Rx13 and electric capacity Cx13 again in parallel after, connect the 2nd pin of analog switch U5 again, in parallel by resistance Rx21 and electric capacity Cx21, connecting resistance Rx22 is in parallel with electric capacity Cx22's, connecting resistance Rx23 and electric capacity Cx23 again in parallel after, connect the 4th pin of analog switch U5 again, 14th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R1, the 9th pin of operational amplifier U1 is connect by resistance R6,

The 6th of described operational amplifier U2, 7 pins are unsettled, the 3rd of described operational amplifier U2, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 1st pin of operational amplifier U2 passes through the series connection ground connection of resistance R13 and R14, the 8th of analog switch U5 the is connect by R13, 9 pins, 8th pin of operational amplifier U2 connects the 9th pin of operational amplifier U2 by resistance R11, connect the 3rd pin of multiplier U3, 9th pin of operational amplifier U2 is in parallel by resistance Rz11 and electric capacity Cz11's, connecting resistance Rz12 is in parallel with electric capacity Cz12's, connecting resistance Rz13 and electric capacity Cz13 again in parallel after, connect the 10th pin of analog switch U5 again, in parallel by resistance Rz21 and electric capacity Cz21, connecting resistance Rz22 is in parallel with electric capacity Cz22's, connecting resistance Rz23 and electric capacity Cz23 again in parallel after, connect the 12nd pin of analog switch U5 again, 14th pin of operational amplifier U2 connects the 13rd pin of operational amplifier U2 by resistance R10, the 9th pin of operational amplifier U2 is connect by resistance R12,

1st pin of described multiplier U3 connects the 8th pin of operational amplifier U1,3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, 7th pin connects the 6th pin of operational amplifier U1 by resistance R8, and the 8th pin meets VCC;

Described multiplier U4 the 1st, 3 pins connect the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, the 5th pin meets VEE, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance R9, and the 8th pin meets VCC;

1st pin of described analog switch U5 meets VCC, the 16th pin ground connection, the 13rd, 14,15 pins are unsettled, the 3rd pin connects the 8th pin of operational amplifier U1, and the 6th pin connects the 7th pin of operational amplifier U1, and the 11st pin connects the 8th pin of operational amplifier U2.