CN204102905U - A kind of RF-LDMOS drain terminal field plate structure - Google Patents
A kind of RF-LDMOS drain terminal field plate structure Download PDFInfo
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- CN204102905U CN204102905U CN201420453674.2U CN201420453674U CN204102905U CN 204102905 U CN204102905 U CN 204102905U CN 201420453674 U CN201420453674 U CN 201420453674U CN 204102905 U CN204102905 U CN 204102905U
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- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 54
- 239000002184 metal Substances 0.000 claims abstract description 43
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 41
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 229910004298 SiO 2 Inorganic materials 0.000 claims abstract description 25
- 230000004888 barrier function Effects 0.000 claims abstract description 22
- 230000000694 effects Effects 0.000 abstract description 10
- 238000000151 deposition Methods 0.000 description 19
- 230000008021 deposition Effects 0.000 description 17
- 230000005684 electric field Effects 0.000 description 12
- 238000000034 method Methods 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000009826 distribution Methods 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 8
- 238000002347 injection Methods 0.000 description 7
- 239000007924 injection Substances 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- ALKWEXBKAHPJAQ-NAKRPEOUSA-N Asn-Leu-Asp-Asp Chemical compound NC(=O)C[C@H](N)C(=O)N[C@@H](CC(C)C)C(=O)N[C@@H](CC(O)=O)C(=O)N[C@@H](CC(O)=O)C(O)=O ALKWEXBKAHPJAQ-NAKRPEOUSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- FGRBYDKOBBBPOI-UHFFFAOYSA-N 10,10-dioxo-2-[4-(N-phenylanilino)phenyl]thioxanthen-9-one Chemical compound O=C1c2ccccc2S(=O)(=O)c2ccc(cc12)-c1ccc(cc1)N(c1ccccc1)c1ccccc1 FGRBYDKOBBBPOI-UHFFFAOYSA-N 0.000 description 1
- 102100037981 Dickkopf-like protein 1 Human genes 0.000 description 1
- 101000951345 Homo sapiens Dickkopf-like protein 1 Proteins 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The utility model discloses a kind of RF-LDMOS drain terminal field plate structure, comprise electrode layer (1), substrate (2), epitaxial loayer (3), source-substrate articulamentum (4), drift region (5), fixed potential district (7), source electrode (8), raceway groove (9), drain electrode (15), insulating barrier (10), grid (20), gate metal silicide (21), source-channel bonding pad (22), also comprise SiO
2layer (23), amorphous silicon (12) and metal silicide (17); Amorphous silicon (12) comprises horizontal expansion structure and longitudinal extension structure, and longitudinal extension structure contacts with drift region (5), and horizontal expansion vibrational power flow is at SiO
2on layer (23); Metal silicide (17) is arranged on amorphous silicon (12).The utility model can improve the puncture voltage of device, reduces hot carrier's effect simultaneously, reduces the drift of quiescent current, significantly reduces Cds electric capacity.
Description
Technical field
The present invention relates to RF-LDMOS (radio frequency Laterally Diffused Metal Oxide Semiconductor) field, particularly relate to a kind of RF-LDMOS drain terminal field plate structure and preparation method thereof.
Background technology
The efficiency of RF ldmos transistor, depends primarily on conducting resistance and the output capacitance of transistor.In addition, the video bandwidth of transistor, also with the output capacitance of transistor, has very large relation.Low output capacitance, can obtain high video bandwidth.As shown in Figure 1, the output capacitance of transistor, depends primarily on the width of drift region (NLDD) 5 and drain electrode 15.The width of drift region (NLDD) is determined by puncture voltage, for 28V RF LDMOS device, usually requires that the width of NLDD is 3um.The width of drain electrode 15 is determined by CT34 and metal silicide 30, and metal silicide 30 needs to cover CT completely, and leaves certain surplus, and drain electrode 15 also needs complete covering metal silicide, and leaves certain surplus, otherwise can cause large electric leakage.Just because of this, the width of drain electrode 15 is usually wider, seriously like this adds output capacitance.
Summary of the invention
Instant invention overcomes the deficiencies in the prior art, a kind of RF-LDMOS drain terminal field plate structure and preparation method thereof is provided.Amorphous silicon comprises and comprises horizontal expansion structure and longitudinal extension structure, and horizontal expansion structure serves the effect of drain electrode field plate, and the formation of drain terminal is before deposition of the amorphous silicon, and autoregistration is formed.Deposited layer of metal silicide above amorphous silicon, reduce the conducting resistance of through hole and amorphous silicon.
The technical solution used in the present invention is:
A kind of RF-LDMOS drain terminal field plate structure, comprise electrode layer, substrate, epitaxial loayer, source-substrate articulamentum, drift region, fixed potential district, source electrode, raceway groove, drain electrode, insulating barrier, grid, gate metal silicide, source-channel bonding pad, it is characterized in that, also comprise SiO
2layer, amorphous silicon and metal silicide;
Substrate is arranged on electrode layer, epitaxial loayer and source-substrate articulamentum are arranged on substrate, drain electrode is arranged on epitaxial loayer, fixed potential district and raceway groove are arranged on source-substrate articulamentum, source electrode is arranged in fixed potential district, drift region is arranged on epitaxial loayer, and is connected with raceway groove, and raceway groove both sides connect source electrode and drift region respectively; Source-substrate articulamentum connects source electrode and substrate;
Source-channel bonding pad is arranged in fixed potential district, and insulating barrier covers on drift region, raceway groove and source electrode, and grid is arranged on the insulating layer, and gate metal silicide is arranged on grid, and amorphous silicon is arranged on drift region, is provided with SiO between grid and amorphous silicon
2layer;
Amorphous silicon is generally L-type, and comprise horizontal expansion structure and longitudinal extension structure, longitudinal extension structure contacts with drift region, and horizontal expansion vibrational power flow on the insulating layer;
Metal silicide is arranged on amorphous silicon, and metal silicide is the port be connected with external circuit, and it is connected with drain electrode by amorphous silicon, i.e. metal silicide, amorphous silicon, drain electrode electrical connection.Insulating barrier and insulating barrier all insulate, and extend into amorphous silicon; Amorphous silicon comprises horizontal expansion structure and longitudinal extension structure, and this horizontal expansion structure serves the effect of drain electrode field plate.Drain electrode utilized autoregistration to be formed before deposition of amorphous silicon.Above amorphous silicon, depositing metal silicide is the conducting resistance in order to reduce between external circuit to drain electrode.
The resistivity of substrate is 0.005-0.05 Ω cm, and the resistivity of epitaxial loayer is 10-100 Ω cm, and the thickness of epitaxial loayer is relevant with puncture voltage.
The doping content of source electrode and drain electrode is 10
19/ cm
3above.
Source-channel bonding pad is metal or metal silicide, be used for connecting source electrode and fixed potential district, thus give raceway groove current potential determined, namely source electrode, source-channel bonding pad and fixed potential district 7 are electrically connected, fixed potential district is connected with raceway groove, to raceway groove current potential determined simultaneously.
Horizontal expansion structure, forms drain electrode field plate, horizontal expansion structure and SiO
2the length of layer contact-making surface is greater than SiO
2layer and thickness of insulating layer sum.The electric field strength of drain edge can be increased like this, make the Electric Field Distribution of drift region more even, the puncture voltage of device can be improved like this, reduce hot carrier's effect simultaneously, reduce the drift of quiescent current.
Forming leakage field plate is the feature that this structure necessarily requires, the electric field strength of drain edge can be increased like this, make the Electric Field Distribution of drift region more even, the puncture voltage of device can be improved like this, reduce hot carrier's effect simultaneously, reduce the drift of quiescent current.
SiO
2the contact-making surface of layer and insulating barrier and amorphous silicon is inclined-plane.In that case, by choosing etching liquid, can ensure insulating barrier and SiO
2the etching of layer is not vertical, but has certain slope.Form such structure, better can optimize the Electric Field Distribution of drift region, the performance of device can better be promoted.
The manufacture method of aforesaid a kind of RF-LDMOS drain terminal field plate structure, with reference to following steps:
S01, the mode being formed drain electrode by self-aligned manner is: etching insulating layer and SiO
2layer forms window, then carries out N-type injection, due to etching insulating layer and SiO
2the barrier effect of layer, only just has ion and enters in body in window region, thus forms drain electrode.By the drain electrode that self-aligned manner is formed, the benefit brought be drain electrode area can do very good, only by the wide decision of the line of shortest length of technique.But if in follow-up technical process, comprise a lot of high-temperature technologies, the donor ion of injection, can spread in silicon, this increases the width in heavily doped N-type district, thus increases the electric capacity of Cds.In addition, in former technique, also have a lot of ion implantation, the P type comprised when forming raceway groove injects.These high-temperature technologies, before all changing, the dopant profiles of ion implantation, affects device performance.Therefore, step S02 operation has been carried out;
S02, after drain electrode is formed, at edge layer and SiO
2end away from the grid deposition last layer amorphous silicon of layer.The benefit of deposition of amorphous silicon is, the temperature of deposition of amorphous silicon is very low, is generally less than 500 degree.The donor ion of such injection silicon can not spread, and can significantly reduce Cds electric capacity.And if deposit spathic silicon, General Requirements temperature is greater than 700 degree, and such donor ion can spread, and causes the increase of Cds electric capacity.Adopt the method for deposition of amorphous silicon, this situation can be avoided.
S03, on amorphous silicon, deposition layer of metal silicide, can reduce the square resistance of CT and polysilicon like this.
S04, the metal silicide of step S03 completes CT and metal connecting line.
Compared with prior art, beneficial effect of the present invention has: the present invention includes SiO
2layer, amorphous silicon and metal silicide; Amorphous silicon, comprise its horizontal expansion structure, define a drain electrode field plate, the electric field strength of drain edge can be increased, make the Electric Field Distribution of drift region more even, the puncture voltage of device can be improved like this, reduce hot carrier's effect simultaneously, reduce the drift of quiescent current, the bottom of amorphous silicon is less with the contact area of drain terminal, and the Area comparison at top is large.Can ensure have enough areas to make the through hole be connected with external circuitry at amorphous silicon top like this.
Drain electrode is formed by self aligned mode, and drain electrode is only by the wide decision of the line of shortest length of technique, and after drain electrode is formed, at deposition last layer amorphous silicon, the benefit of deposition of amorphous silicon is, the temperature of deposition of amorphous silicon is very low, and temperature is generally less than 500 degree.The donor ion of such injection silicon can not spread, and can significantly reduce Cds electric capacity like this.
Accompanying drawing explanation
Fig. 1 is the structural representation of prior art drain terminal field plate structure;
Fig. 2 is the structural representation of a kind of RF-LDMOS drain terminal of the present invention field plate structure;
Fig. 3 is that the present invention states SiO
2the contact-making surface of layer and insulating barrier and amorphous silicon is the example structure schematic diagram on inclined-plane.
Embodiment
Below in conjunction with accompanying drawing, the present invention is further described.
As shown in Figure 2, a kind of RF-LDMOS drain terminal field plate structure, comprise electrode layer 1, substrate 2, epitaxial loayer 3, source-substrate articulamentum 4, drift region 5, fixed potential district 7, source electrode 8, raceway groove 9, drain electrode 15, insulating barrier 10, grid 20, gate metal silicide 21, source-channel bonding pad 22, it is characterized in that, also comprise SiO
2layer 23, amorphous silicon 12 and metal silicide 17;
Substrate 2 is arranged on electrode layer 1, epitaxial loayer 3 and source-substrate articulamentum 4 arrange on the substrate 2, drain electrode 15 is arranged on epitaxial loayer 3, fixed potential district 7 and raceway groove 9 are arranged on source-substrate articulamentum 4, source electrode 8 is arranged in fixed potential district 7, drift region 5 is arranged on epitaxial loayer 3, and is connected with raceway groove 9, and raceway groove 9 both sides connect source electrode 8 and drift region 5 respectively; Source-substrate articulamentum 4 connects source electrode 8 and substrate 2;
Source-channel bonding pad 22 is arranged in fixed potential district 7, insulating barrier 10 covers on drift region 5, raceway groove 9 and source electrode 8, grid 20 is arranged on insulating barrier 10, gate metal silicide 21 is arranged on grid 20, amorphous silicon 12 is arranged on drift region 5, is provided with SiO between grid 20 and amorphous silicon 12
2layer 23;
Amorphous silicon 12 is L-type, and comprise horizontal expansion structure and longitudinal extension structure, longitudinal extension structure contacts with drift region 5, and horizontal expansion vibrational power flow is at SiO
2on layer 23;
Metal silicide 17 is arranged on amorphous silicon 12.Metal silicide 17 is the ports be connected with external circuit, and it is connected with drain electrode 15 by amorphous silicon 12.Amorphous silicon 12 comprises horizontal expansion structure and longitudinal extension structure, and horizontal expansion structure (a part in Fig. 3) serves the effect of drain electrode field plate.Drain electrode 15 utilized autoregistration to be formed before deposition of amorphous silicon 12.Above amorphous silicon 12, depositing metal silicide 17 is the conducting resistance in order to reduce between external circuit to drain electrode 15.
For N-type LDMOS, can derive according to principle corresponding to N-type LDMOS and description for P type LDMOS.The resistivity of substrate 2 is 0.005-0.05 Ω cm, and the resistivity of epitaxial loayer 3 is 10-100 Ω cm, and the thickness of epitaxial loayer is relevant with puncture voltage.
Source electrode 8 and drain electrode 15 be that heavily doped N-type forms, and are used for the source of doing and leakage, doping content be 10
19/ cm
3above.
Drift region 5 is drift regions of one section of N-type doping, is used for improving the puncture voltage of LDMOS device.7 are made up of the heavy doping of P type, and being used to provides a fixing current potential to P-type raceway groove.Raceway groove 9 is P-Body, is used to the raceway groove forming LDMOS, regulates its doping content can change the threshold voltage of LDMOS, also can prevent the Punch-Through of raceway groove in addition.Source-substrate articulamentum 4 is normally made up of the heavy doping of P type, it is used to connection source and highly doped substrate, the metal that the contact in such source just can be against by highly doped substrate back is drawn, and which reduces the stray inductance of source, improves the radiofrequency characteristics of device.If do not have source-substrate articulamentum 4, source is drawn by 13 metal connecting lines.10 is insulating barriers, prevent 10 directly and silicon substrate be connected together (mistake is described herein, prevent? link together with silicon substrate), be normally made up of silicon dioxide.Grid 20 is normally made up of polysilicon, and gate metal silicide 21 is the layer of metal silicides above grid, to lower the square resistance of grid.
Source-channel bonding pad 22 is metal or metal silicide, be used for connecting source electrode 8 and fixed potential district 7, thus give raceway groove current potential determined, namely source electrode 8, source-channel bonding pad 22 and fixed potential district 7 are electrically connected, fixed potential district 7 is connected with raceway groove 9, to raceway groove 9 one current potentials determined simultaneously.Horizontal expansion structure, forms drain electrode field plate, horizontal expansion structure and SiO
2the length a of layer 23 contact-making surface is greater than SiO
2layer 23 and insulating barrier 10 thickness sum b.The electric field strength of drain edge can be increased like this, make the Electric Field Distribution of drift region more even, the puncture voltage of device can be improved like this, reduce hot carrier's effect simultaneously, reduce the drift of quiescent current.
Forming leakage field plate is the feature that this structure necessarily requires, the electric field strength of drain edge can be increased like this, make the Electric Field Distribution of drift region more even, the puncture voltage of device can be improved like this, reduce hot carrier's effect simultaneously, reduce the drift of quiescent current.
As shown in Figure 3, SiO
2layer 23 and insulating barrier 10 are inclined-plane with the contact-making surface of amorphous silicon 12.In that case, by choosing etching liquid, can ensure insulating barrier 10 and SiO
2the etching of layer 23 is not vertical, but has certain slope.Form such structure, better can optimize the Electric Field Distribution of drift region, the performance of device can better be promoted.
The manufacture method of aforesaid a kind of RF-LDMOS drain terminal field plate structure, comprises the following steps:
S01, insulating barrier 10 and SiO
2layer is opened for 23 quarter, then carries out N-type injection, forms drain electrode 15; Such drain electrode 15 is formed by self aligned mode, and it is very good that the area doing the benefit drain electrode 15 that can bring like this can do, only by the wide decision of the line of shortest length of technique.But if in follow-up technical process, comprise a lot of high-temperature technologies, the donor ion of injection, can spread in silicon, this increases the width in heavily doped N-type district, thus increases the electric capacity of Cds.In addition, in former technique, also there is a lot of ion implantation, comprise the formation of 9 P-Body.These high-temperature technologies, all can to the distribution changing ion implantation in the past in the past, performance during impact.
For this reason, following solution is adopted:
S02, after drain electrode 15 is formed, at edge layer 10 and SiO
2end away from the grid 20 deposition last layer amorphous silicon 12 of layer 23.The benefit of deposition of amorphous silicon is, the temperature of deposition of amorphous silicon is very low, and temperature is generally less than 500 degree.The donor ion of such injection silicon can not spread, and can significantly reduce Cds electric capacity like this.If deposit spathic silicon, General Requirements temperature is greater than 700 degree, and such donor ion can spread, and causes the increase of Cds electric capacity.Adopt the method for deposition of amorphous silicon, this situation can be avoided.
S03, on amorphous silicon 12, deposition layer of metal silicide; Face is at deposition layer of metal silicide on the polysilicon, can reduce the square resistance of CT and polysilicon.
S04, the metal silicide of step S03 completes CT and metal connecting line.
Below be only the preferred embodiment of the present invention; be noted that for those skilled in the art; under the premise without departing from the principles of the invention, can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (6)
1. a RF-LDMOS drain terminal field plate structure, comprise electrode layer (1), substrate (2), epitaxial loayer (3), source-substrate articulamentum (4), drift region (5), fixed potential district (7), source electrode (8), raceway groove (9), drain electrode (15), insulating barrier (10), grid (20), gate metal silicide (21), source-channel bonding pad (22), it is characterized in that, also comprise SiO
2layer (23), amorphous silicon (12) and metal silicide (17);
Substrate (2) is arranged on electrode layer (1), described epitaxial loayer (3) and source-substrate articulamentum (4) are arranged on substrate (2), described drain electrode (15) is arranged on epitaxial loayer (3), fixed potential district (7) and raceway groove (9) are arranged on source-substrate articulamentum (4), source electrode (8) is arranged in fixed potential district (7), described drift region (5) arranges on epitaxial loayer (3), and be connected with described raceway groove (9), raceway groove (9) both sides connect source electrode (8) and drift region (5) respectively; Described source-substrate articulamentum (4) connects source electrode (8) and substrate (2);
Source-channel bonding pad (22) is arranged in fixed potential district (7), insulating barrier (10) covers on drift region (5), raceway groove (9) and source electrode (8), grid (20) is arranged on insulating barrier (10), gate metal silicide (21) is arranged on described grid (20), amorphous silicon (12) is arranged on drift region (5), is provided with SiO between described grid (20) and described amorphous silicon (12)
2layer (23); Described source-channel bonding pad (22) connects source electrode (8) and fixed potential district (7), and fixed potential district (7) are connected with raceway groove (9);
Described amorphous silicon (12) comprises horizontal expansion structure and longitudinal extension structure, and described longitudinal extension structure contacts with drift region (5), and described horizontal expansion vibrational power flow is at described SiO
2on layer (23);
Described metal silicide (17) is arranged on described amorphous silicon (12), and described metal silicide (17) is connected with drain electrode (15) by amorphous silicon (12).
2. a kind of RF-LDMOS drain terminal field plate structure according to claim 1, is characterized in that, the resistivity of described substrate (2) is 0.005-0.05 Ω cm, and the resistivity of described epitaxial loayer (3) is 10-100 Ω cm.
3. a kind of RF-LDMOS drain terminal field plate structure according to claim 1, is characterized in that, the doping content of source electrode (8) and drain electrode (15) is 10
19/ cm
3above.
4. a kind of RF-LDMOS drain terminal field plate structure according to claim 1, it is characterized in that, source-channel bonding pad (22) are metal or metal silicide, are used for connecting source electrode (8) and fixed potential district (7).
5. a kind of RF-LDMOS drain terminal field plate structure according to claim 1, is characterized in that, described horizontal expansion structure, forms drain electrode field plate, described horizontal expansion structure and SiO
2the length (a) of layer (23) contact-making surface is greater than SiO
2layer (23) and insulating barrier (10) thickness sum (b).
6. a kind of RF-LDMOS drain terminal field plate structure according to claim 1, is characterized in that, described SiO
2layer (23) and insulating barrier (10) are inclined-plane with the contact-making surface of described amorphous silicon (12).
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| CN201420453674.2U CN204102905U (en) | 2014-08-13 | 2014-08-13 | A kind of RF-LDMOS drain terminal field plate structure |
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| CN201420453674.2U CN204102905U (en) | 2014-08-13 | 2014-08-13 | A kind of RF-LDMOS drain terminal field plate structure |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104183632A (en) * | 2014-08-13 | 2014-12-03 | 昆山华太电子技术有限公司 | RF-LDMOS (radio frequency laterally diffused metal oxide semiconductor) self-alignment drain terminal field plate structure and fabrication method thereof |
| CN107710410A (en) * | 2015-05-21 | 2018-02-16 | 酷星技术股份有限公司 | The enhancing of DMOS and cmos semiconductor device integrates |
| WO2019024906A1 (en) * | 2017-08-04 | 2019-02-07 | 无锡华润上华科技有限公司 | Ldmos component, manufacturing method therefor, and electronic device |
-
2014
- 2014-08-13 CN CN201420453674.2U patent/CN204102905U/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104183632A (en) * | 2014-08-13 | 2014-12-03 | 昆山华太电子技术有限公司 | RF-LDMOS (radio frequency laterally diffused metal oxide semiconductor) self-alignment drain terminal field plate structure and fabrication method thereof |
| CN104183632B (en) * | 2014-08-13 | 2017-08-29 | 昆山华太电子技术有限公司 | The self aligned drain terminal field plate structures of RF LDMOS and preparation method |
| CN107710410A (en) * | 2015-05-21 | 2018-02-16 | 酷星技术股份有限公司 | The enhancing of DMOS and cmos semiconductor device integrates |
| WO2019024906A1 (en) * | 2017-08-04 | 2019-02-07 | 无锡华润上华科技有限公司 | Ldmos component, manufacturing method therefor, and electronic device |
| US11158737B2 (en) | 2017-08-04 | 2021-10-26 | Csmc Technologies Fab2 Co., Ltd. | LDMOS component, manufacturing method therefor, and electronic device |
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