CN204011395U - A kind of QFN encapsulating structure of two-sided semiconductor device - Google Patents
A kind of QFN encapsulating structure of two-sided semiconductor device Download PDFInfo
- Publication number
- CN204011395U CN204011395U CN201420367174.7U CN201420367174U CN204011395U CN 204011395 U CN204011395 U CN 204011395U CN 201420367174 U CN201420367174 U CN 201420367174U CN 204011395 U CN204011395 U CN 204011395U
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- China
- Prior art keywords
- chip
- sipes
- framework
- conducting resinl
- semiconductor device
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- Expired - Fee Related
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 239000011521 glass Substances 0.000 claims abstract description 7
- 238000003032 molecular docking Methods 0.000 claims abstract description 4
- 238000002161 passivation Methods 0.000 claims abstract description 4
- 230000001052 transient effect Effects 0.000 abstract description 3
- 238000005538 encapsulation Methods 0.000 description 12
- 238000000034 method Methods 0.000 description 7
- 238000007599 discharging Methods 0.000 description 6
- 238000002360 preparation method Methods 0.000 description 6
- 239000007787 solid Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000012856 packing Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 239000000047 product Substances 0.000 description 4
- 238000012797 qualification Methods 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000000428 dust Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 210000003205 muscle Anatomy 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 230000002457 bidirectional effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000009770 conventional sintering Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model discloses a kind of QFN encapsulating structure of two-sided semiconductor device, comprise chip and the framework docking with it, described chip is provided with sipes at the lateral edges of the contact-making surface of itself and framework, in sipes surface coverage, has glass passivation layer; Described framework has the overflow launder of certain width in its position corresponding with the inner edge of chip sipes; Chip and framework are bonding by conducting resinl, and excessive conducting resinl is placed in overflow launder.The utility model arranges sipes structure on chip, and overflow groove structure is set on framework, and conducting resinl can flow into overflow launder when flash, the short circuit problem while effectively having prevented conducting resinl flash; It is the 2815A of KYOCERA that conducting resinl of the present utility model is selected model, when two-sided semiconductor device is power device, also can meet particular job state needs of transient high-current.
Description
Technical field
The utility model belongs to semiconductor device design and manufacture field, specifically a kind of QFN encapsulating structure of two-sided semiconductor device.
Background technology
Along with design of electronic circuits is tending towards highly integrated, the encapsulation volume of device is required also to improve thereupon, the two-sided semiconductor device of paster type encapsulation such as traditional button-shaped encapsulation, SMA/SMB/SMC cannot meet the Butut needs of high side circuitry Design PCB version gradually, and more flat, more small-sized packing forms demand is urgent.
Surrounding is current the most suitable wafer-level package form without pin Flat type packaged (QFN), but this encapsulation technology is mainly used in integrated antenna package at present, for the such power device of solid discharging tube inapplicable.Its main cause is with reference to Fig. 1, two-sided semiconductor device when conducting resinl flash can with chip contact short circuit, thereby cause component failure; In addition, if this device is power device, the operating state that need to bear transient high-current, QFN can only be used conducting resinl to carry out bonding die, and conventional conducting resinl cannot meet this performance need.
Utility model content
The application is according to the technical threshold in background technology, based on the existing encapsulation technology of QFN and appointed condition, designed, designed a kind of QFN encapsulating structure of two-sided semiconductor device.
Technical scheme is:
A QFN encapsulating structure for two-sided semiconductor device, comprises chip and the framework docking with it, and described chip is provided with sipes at the lateral edges of the contact-making surface of itself and framework, in sipes surface coverage, has glass passivation layer; Described framework has the overflow launder of certain width in its position corresponding with the inner edge of chip sipes; Chip and framework are bonding by conducting resinl, and excessive conducting resinl is placed in overflow launder.
As preferred embodiment, the section of described sipes is arc, and its width is 90～110 μ m, is highly 30～50 μ m; The width of described overflow launder is 150～200 μ m, groove depth 50～60 μ m, and in it, surrounding edge length is less than the long 100 μ m of surrounding edge in chip sipes.
Preferably, described conducting resinl model is the 2815A of KYOCERA.
This encapsulating structure also comprises the first pin and the second pin, and as the arrangement of a kind of the first pin and the second pin, the first pin is connected with chip by wire respectively with the second pin.
As the arrangement of another kind of the first pin and the second pin, the first pin is connected with chip by wire, and the second pin is arranged on framework, by conducting resinl, is connected with chip.
The beneficial effects of the utility model:
The utility model arranges sipes structure on chip, and overflow groove structure is set on framework, and conducting resinl can flow into overflow launder when flash, the short circuit problem while effectively having prevented conducting resinl flash;
It is the 2815A of KYOCERA that conducting resinl of the present utility model is selected model, when two-sided semiconductor device is power device, also can meet particular job state needs of transient high-current.
Accompanying drawing explanation
Fig. 1 is the QFN encapsulating structure schematic diagram of conventional two-sided semiconductor device.
Fig. 2 is the sipes structure side view of the utility model chip.
Fig. 3 is the sipes structure vertical view of the utility model chip.
Fig. 4 is the overflow groove structure end view of the utility model framework.
Fig. 5 is the overflow groove structure vertical view of the utility model framework.
Fig. 6 is QFN encapsulating structure schematic diagram of the present utility model (the first pin arrangement mode).
Fig. 7 is QFN encapsulating structure schematic diagram of the present utility model (the second pin arrangement mode).
Description of reference numerals:
1-chip; 2-sipes; 3-framework; 4-overflow launder; 5-Ji island; 6-the first pin; 7-the second pin.
Embodiment
Below in conjunction with accompanying drawing, the QFN encapsulating structure of a kind of two-sided semiconductor device of the utility model is described further, but protection range of the present utility model is not limited to this:
In conjunction with Fig. 2-Fig. 5, a kind of QFN encapsulating structure of two-sided semiconductor device, comprise chip 1 and with its framework docking by base island 53, described chip 1 is provided with sipes 2 at the lateral edges of the contact-making surface of itself and framework 3, in sipes 2 surface coverage, has glass passivation layer; Described framework 3 has the overflow launder 4 of certain width in its position corresponding with the inner edge of the sipes 2 of chip 1; Chip 1 and framework 3 are bonding by conducting resinl, and excessive conducting resinl is placed in overflow launder 4.
The section of sipes 2 is arc, and its width is 90～110 μ m, is highly 30～50 μ m; The width of overflow launder 4 is 150～200 μ m, groove depth 50～60 μ m, and in it, surrounding edge length is less than the long 100 μ m of the interior surrounding edge of sipes 2 of chip 1.
Conducting resinl model is the 2815A of KYOCERA.
In conjunction with Fig. 6, the QFN encapsulating structure of two-sided semiconductor device of the present utility model also comprises that the first pin 6 and the second pin 7, the first pins 6 are connected with chip 1 by wire respectively with the second pin 7.
In conjunction with Fig. 7, the second arrangement of the utility model the first pin 6 and the second pin 7, the first pin 6 is connected with chip 1 by wire, and the second pin 7 is arranged on framework 3, by conducting resinl, is connected with chip 1.
Below in conjunction with specific embodiment, the QFN method for packing of a kind of two-sided semiconductor device of the utility model is described, but protection range of the present utility model is not limited to this:
Embodiment 1:
The QFN encapsulation of solid discharging tube:
The preparation of a, chip:
1, technological process to phosphorus diffusion finishes routinely;
2, one side etching sipes domain, another side applies photoresist exposure protection, does not do to corrode;
3, wet etching sipes, its width is 90 μ m, is highly 30 μ m;
4, in sipes surface-coated glass dust (370 type), carry out conventional glassivation operation;
5, chip metallization, forms electrode;
The preparation of b, framework: prepared framework has the overflow launder of certain width at the inner edge correspondence position of itself and chip sipes; The width of overflow launder is 150 μ m, groove depth 50 μ m, and in it, surrounding edge length is less than the long 100 μ m of surrounding edge in chip sipes;
C, the selection 2815A of conducting resinl KYOCERA carry out bonding die;
D, technological process is carried out key pressure, plastic packaging, is cut muscle, test, braid and packing routinely.
Embodiment 2:
The QFN encapsulation of solid discharging tube:
The preparation of a, chip:
1, technological process to phosphorus diffusion finishes routinely;
2, one side etching sipes domain, another side applies photoresist exposure protection, does not do to corrode;
3, wet etching sipes, its width is 110 μ m, is highly 50 μ m;
4, in sipes surface-coated glass dust (370 type), carry out conventional glassivation operation;
5, chip metallization, forms electrode;
The preparation of b, framework: prepared framework has the overflow launder of certain width at the inner edge correspondence position of itself and chip sipes; The width of overflow launder is 200 μ m, groove depth 60 μ m, and in it, surrounding edge length is less than the long 100 μ m of surrounding edge in chip sipes;
C, the selection 2815A of conducting resinl KYOCERA carry out bonding die;
D, technological process is carried out key pressure, plastic packaging, is cut muscle, test, braid and packing routinely.
Embodiment 3:
The QFN encapsulation of bidirectional trigger diode:
The preparation of a, chip:
1, technological process to phosphorus diffusion finishes routinely;
2, one side etching sipes domain, another side applies photoresist exposure protection, does not do to corrode;
3, wet etching sipes, its width is 100 μ m, is highly 40 μ m;
4, in sipes surface-coated glass dust (370 type), carry out conventional glassivation operation;
5, chip metallization, forms electrode;
The preparation of b, framework: prepared framework has the overflow launder of certain width at the inner edge correspondence position of itself and chip sipes; The width of overflow launder is 175 μ m, groove depth 55 μ m, and in it, surrounding edge length is less than the long 100 μ m of surrounding edge in chip sipes;
C, the selection 2815A of conducting resinl KYOCERA carry out bonding die;
D, technological process is carried out key pressure, plastic packaging, is cut muscle, test, braid and packing routinely.
For checking the utility model conforming product rate greatly improves, now take three contrast schemes (1, planar chip+without overflow launder framework+solid discharging tube; 2, band sipes isolating chip+without overflow launder framework+solid discharging tube; 3, planar chip+have overflow launder framework+bidirectional trigger diode) in conjunction with the scheme of three embodiment, carry out experimental verification.Each contrast scheme and embodiment scheme are all carried out the small lot batch manufacture of 50 numbers, and statistics qualification rate is as following table:
| Sample batch | Qualification rate | Technical scheme |
| 1 | 0％ | Contrast scheme 1 |
| 2 | 16％ | Contrast scheme 2 |
| 3 | 12％ | Contrast scheme 3 |
| 4 | 94％ | Embodiment 1 |
| 5 | 89％ | Embodiment 2 |
| 6 | 92％ | Embodiment 3 |
The utility model embodiment gained qualification rate is very nearly the same with conventional paster encapsulation qualification rate, realized the production in enormous quantities feasibility that QFN encapsulates two-sided semiconductor device." accurate QFN encapsulates two-sided semiconductor device " on contrast market, actual its is that thinner normal sintering formula paster encapsulates, and product thickness cannot be less than 1mm, and needs independent mold developing and production test equipment, and investment of production is huge.This programme is standard QFN encapsulation, can compatible existing various QFN sealed in unit, go into operation without increasing investment, and product thickness can be down to 0.7～0.8mm, and break through conventional sintering formula and encapsulated the unsurpassable 1mm limit of two-sided semiconductor device.
The utility model scheme has realized chip-scale (CSP) the QFN encapsulation of two-sided semiconductor device.Wafer-level package will become the development trend of integrated circuit from now on; in the wiring board of a large amount of use wafer-level package integrated circuits; the product of the utility model scheme (the QFN encapsulation of solid discharging tube) will can be this type circuit provides high-power overvoltage protection, breaks away from due to high-power protection device being installed simultaneously and needs to increase the drawback of pcb board installing space.
Specific embodiment described herein is only that utility model spirit is illustrated.The utility model person of ordinary skill in the field can make various modifications or supplements or adopt similar mode to substitute described specific embodiment, but can't depart from spirit of the present utility model or surmount the defined scope of appended claims.
Claims (5)
1. a QFN encapsulating structure for two-sided semiconductor device, comprises chip and the framework docking with it, it is characterized in that described chip is provided with sipes at the lateral edges of the contact-making surface of itself and framework, has glass passivation layer in sipes surface coverage; Described framework has the overflow launder of certain width in its position corresponding with the inner edge of chip sipes; Chip and framework are bonding by conducting resinl, and excessive conducting resinl is placed in overflow launder.
2. the QFN encapsulating structure of a kind of two-sided semiconductor device according to claim 1, the section that it is characterized in that described sipes is arc, its width is 90～110 μ m, is highly 30～50 μ m; The width of described overflow launder is 150～200 μ m, groove depth 50～60 μ m, and in it, surrounding edge length is less than the long 100 μ m of surrounding edge in chip sipes.
3. the QFN encapsulating structure of a kind of two-sided semiconductor device according to claim 1, is characterized in that described conducting resinl model is the 2815A of KYOCERA.
4. according to the QFN encapsulating structure of any the two-sided semiconductor device described in claim 1-3, it is characterized in that it also comprises the first pin and the second pin, the first pin is connected with chip by wire respectively with the second pin.
5. according to the QFN encapsulating structure of any the two-sided semiconductor device described in claim 1-3, it is characterized in that it also comprises the first pin and the second pin, the first pin is connected with chip by wire, and the second pin is arranged on framework, by conducting resinl, is connected with chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420367174.7U CN204011395U (en) | 2014-07-03 | 2014-07-03 | A kind of QFN encapsulating structure of two-sided semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420367174.7U CN204011395U (en) | 2014-07-03 | 2014-07-03 | A kind of QFN encapsulating structure of two-sided semiconductor device |
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| Publication Number | Publication Date |
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| CN204011395U true CN204011395U (en) | 2014-12-10 |
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| CN201420367174.7U Expired - Fee Related CN204011395U (en) | 2014-07-03 | 2014-07-03 | A kind of QFN encapsulating structure of two-sided semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104064533A (en) * | 2014-07-03 | 2014-09-24 | 江苏东光微电子股份有限公司 | QFN packaging structure and method for double-face semiconductor device |
-
2014
- 2014-07-03 CN CN201420367174.7U patent/CN204011395U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104064533A (en) * | 2014-07-03 | 2014-09-24 | 江苏东光微电子股份有限公司 | QFN packaging structure and method for double-face semiconductor device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: JIANGSU DONGCHEN ELCTRONICS TECHNOLOGY CO., LTD. Free format text: FORMER NAME: YIXING DONGCHEN ELECTRONIC TECHNOLOGY CO., LTD. |
|
| CP01 | Change in the name or title of a patent holder |
Address after: 214205 Yixing New Street Lily Industrial Park, Jiangsu, Wuxi Patentee after: JIANGSU DONGCHEN ELECTRONICS TECHNOLOGY Co.,Ltd. Address before: 214205 Yixing New Street Lily Industrial Park, Jiangsu, Wuxi Patentee before: YIXING DONGCHEN ELECTRONIC TECHNOLOGY Co.,Ltd. |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20141210 |