CN203930815U - A kind of high speed signal generation systems based on solid state hard disc - Google Patents

Abstract

The utility model relates to a kind of high speed signal generation systems based on solid state hard disc.In the implementation of signal generating system storage data, EEPROM capacity is little, and FLASH is bad piece of manageability not, and mechanical hard disk speed is slow.The utility model includes FPGA, PATA-SATA bridge sheet and four SSD in parallel; FPGA includes both-end RAM, RAM controller, memory controller and UART transceiver; On FPGA, be provided with the parallel input interface of LVDS that receives external data, and expand the PATA interface that has 4 forwarding datas, each PATA interface access PATA-SATA bridge sheet accesses respectively four SSD in parallel again.The utility model utilizes multiple solid state hard discs signal generation rate that improves in parallel, and memory capacity is large, signal rate occurs high, owing to having adopted FPGA and PATA-SATA bridge sheet, do not need to use the third party IPcore of SATA, save cost, external interface diversification of forms.

Description

A kind of high speed signal generation systems based on solid state hard disc

Technical field

the utility model relates to a kind of signal generating system, is specifically related to a kind of high speed signal generation systems based on solid state hard disc.

Background technology

Signal generating system can externally provide emulated data or true image data as signal source, is used as the data source of equipment under test, to detect the handling property of equipment under test.First signal generating system is wanted to store data, and implementation has EEPROM, FLASH, mechanical hard disk, solid state hard disc etc.In these several implementations, the speed of EEPROM is slow, and capacity is little; FLASH capacity is little, not bad piece of manageability; Mechanical hard disk speed is slow; Although the speed of solid state hard disc compares comparatively fast, externally provide high-speed data in order to meet, use a hard disk can not meet interface rate requirement.

Summary of the invention

The purpose of this utility model is to provide a kind of high speed signal generation systems based on solid state hard disc, and parallel signal more at a high speed can be externally provided.

The technical scheme that the utility model adopts is:

A high speed signal generation systems based on solid state hard disc, is characterized in that:

Include FPGA, PATA-SATA bridge sheet and four SSD in parallel;

FPGA includes both-end RAM, RAM controller, memory controller and UART transceiver;

On FPGA, be provided with the parallel input interface of LVDS of reception external data and the parallel input interface of LVDS of transmission internal data, and expand the PATA interface that has 4 forwarding datas, each PATA interface access PATA-SATA bridge sheet accesses respectively four SSD in parallel again.

FPGA is connected to FIFO or the RAM for buffer memory SSD read-write interval data, and the space size of buffer memory mates with the interval of SSD2 UDMA transmission.

The utlity model has following advantage:

The high speed signal generation systems based on solid state hard disc that the utility model is related, with FPGA and the realization of multiple solid state hard disc, memory capacity is large, generation signal rate is high, owing to having adopted FPGA and PATA-SATA bridge sheet, provide multiple SATA interfaces simultaneously, do not need to use the third party IPcore of SATA, save cost, external interface diversification of forms.Use FIFO to solve the problem of the UDMA Transmission Time Interval of PATA interface as buffer memory in inside, thereby ensure the continuity of external interface, utilize the high-speed parallel output interface of FPGA to carry out transmitted signal simultaneously, reduce design complexity.

Brief description of the drawings

Fig. 1 is that system hardware is realized block diagram.

Fig. 2 is FPGA Software for Design internal module block diagram.

Fig. 3 writes 4 hard disks Data Division to realize block diagram.

Fig. 4 is that the pooled data of 4 hard disks is converted to raw data format output.

Fig. 5 is UDMA transmission DREQ signal waveform.

Fig. 6 is register configuration under READ DMA pattern.

Fig. 7 is register configuration under READ DMA EXT pattern.

Fig. 8 is PATA-SATA bridge sheet schematic diagram, and two ends are connected respectively to FPGA and SATA connector.

Fig. 9-11 are 3 kinds of data output interfaces of correspondence system respectively: parallel LVDS, TLK2711, ECL.

Wherein, parallel LVDS is directly connected to the LVDS interface of FPGA, TLK2711 interface utilizes the GPIO of FPGA to change by TLK2711 chip, ECL interface utilizes the parallel serial conversion module of FPGA inside that parallel data is converted to the output of LVDS interface, realizes the conversion of LVDS level to ECL level in outside by level transferring chip simultaneously.

Embodiment

Below in conjunction with embodiment, the utility model is described in detail.

A kind of high speed signal generation systems based on solid state hard disc that the utility model relates to, as shown in Figure 1, includes FPGA, PATA-SATA bridge sheet and four SSD in parallel.FPGA includes both-end RAM, RAM controller, memory controller and UART transceiver, on FPGA, be provided with the parallel input interface of LVDS that receives external data and the parallel input interface of LVDS that sends internal data, and expand the PATA interface that has 4 forwarding datas, each PATA interface access PATA-SATA bridge sheet accesses respectively four SSD in parallel again.FPGA is connected to FIFO or the RAM for buffer memory SSD read-write interval data, and the space size of buffer memory mates with the interval of SSD2 UDMA transmission.Under data acquisition scheme, system walks abreast input interface from outside access data by LVDS, controls forwarding by FPGA, then gives outside PATA-SATA bridge sheet by PATA interface, and data are write SSD after the conversion of PATA-SATA bridge sheet.Data transmission modes is contrary with above process, and data read out after FPGA conversion and send by LVDS parallel output interface from SSD.In order to realize data acquisition and the transmission of relative high speed, the utility model adopts the structure of 4 SSD parallel connections, and like this, the speed of external interface can reach 4 times of hard-disk interface, can improve system bandwidth.Figure 2 shows that FPGA internal software design module frame chart.

Owing to having used PATA-SATA bridge sheet, PATA interface has limited the transfer rate of SATA interface, in order to improve the transmission rate of data, on FPGA, expand 4 PATA interfaces, be unit the data that receive according to a word (16bit), store into respectively on each SSD, be that first 16bit deposits on SSD1, second 16bit deposits on SSD2, the 3rd 16bit deposits SSD3 above, and the 4th 16bit deposits SSD4 above, and the 5th 16bit deposits on SSD1, the 6th 16bit deposits SSD2 above, by that analogy.In the time that reception external data speed is higher, the memory rate of single SSD only has 1/4 of external data receiving velocity like this, makes the speed of writing SSD can reach the outside requirement that receives data.Figure 3 shows that Data Division is write to 4 SSD realizes block diagram, produces the enable signal of writing of 4 hard-disk interface FIFO, initial setting up fifo_wen_temp<=4'b0001 in code in DATA_FIFO_CONTROL by displacement; In the time starting to transmit data, fifo_wen_temp is assigned to fifo_wen, realize displacement fifo_wen_temp<={fifo_wen_temp[2:0 in transmitting procedure simultaneously], fifo_wen_temp[3] };

Equally, in the time that system outwards sends data as signal source, simultaneously from 4 SSD reading out datas, remake and be similar to parallel-serial conversion and outwards send, the speed of so external transmission data is exactly 4 times of the single SSD of reading speed, can improve the speed of external transmission data in the situation that SSD reading rate is limited.In Fig. 4, write fifo end data width 64bit, read fifo end data width 16bit, realized parallel-serial conversion function with fifo, completed data are reverted to raw data format.

Because system storage is all real-time Transmission with sending data, and the read and write of SSD is all spaced, be to have the response time between each UDMA transmission, during this period of time, SSD can not receive or send data, at this time in order to ensure system storage and to send the continuity of data, must come with FIFO or RAM data cachedly, the space size of buffer memory will mate with the interval that SSD2 UDMA transmits.

UDMA transmission is by asking (enabling DREQ signal) from equipment by initiating UDMA, then response of host request starts UDMA transmission, in host configuration from equipment, (describe unclear and coherent, please audit amendment) to the time of initiating UDMA request from equipment be not to be subject to host computer control, by reality test send out this time with from device-dependent, the response time of different solid state hard discs is inconsistent, the response time of certain model solid state hard disc shown in Fig. 3 is approximately 20us, can calculate the capacity of FIFO according to this time, take external transfer rate as example as 100MB/s, the required FIFO capacity=100MB/s*25us/4=625B of each hard-disk interface module.The interface rate of each hard disk must be greater than 25MB/s simultaneously, shown in Fig. 5, a UDMA duration is approximately 1000us, the interface rate of hard disk is greater than (100 * 1000/ (1000-25)) MB/s, visible when one timing of hard-disk interface speed, improve the UDMA duration and can improve external transfer rate.By the transmission mode of configuration UDMA, can change the UDMA duration one time.

The UDMA access of hard disk has 2 kinds of patterns, has read as example, has two kinds of READ DMA and READ DMA EXT, the difference of 2 kinds of patterns is the in different size of reference address space, and the length of each UDMA transmission is different, the register value difference configuring under two kinds of patterns, as shown in Figure 6 and Figure 7.

Fig. 9-11 are 3 kinds of data output interfaces of correspondence system respectively: parallel LVDS, TLK2711, ECL.Wherein, parallel LVDS is directly connected to the LVDS interface of FPGA, TLK2711 interface utilizes the GPIO of FPGA to change by TLK2711 chip, ECL interface utilizes the parallel serial conversion module of FPGA inside that parallel data is converted to the output of LVDS interface, realizes the conversion of LVDS level to ECL level in outside by level transferring chip simultaneously.

It is cited that content of the present utility model is not limited to embodiment, and the conversion of any equivalence that those of ordinary skill in the art take technical solutions of the utility model by reading the utility model instructions, is claim of the present utility model and contains.

Claims (2)

1. the high speed signal generation systems based on solid state hard disc, is characterized in that:

Include FPGA, PATA-SATA bridge sheet and four SSD in parallel;

FPGA includes both-end RAM, RAM controller, memory controller and UART transceiver;

On FPGA, be provided with the parallel input interface of LVDS of reception external data and the parallel input interface of LVDS of transmission internal data, and expand the PATA interface that has 4 forwarding datas, each PATA interface access PATA-SATA bridge sheet accesses respectively four SSD in parallel again.

2. a kind of high speed signal generation systems based on solid state hard disc according to claim 1, is characterized in that:

FPGA is connected to FIFO or the RAM for buffer memory SSD read-write interval data, and the space size of buffer memory mates with the interval of SSD2 UDMA transmission.