CN203883038U - Led封装结构 - Google Patents

Led封装结构 Download PDF

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Publication number
CN203883038U
CN203883038U CN201320891378.6U CN201320891378U CN203883038U CN 203883038 U CN203883038 U CN 203883038U CN 201320891378 U CN201320891378 U CN 201320891378U CN 203883038 U CN203883038 U CN 203883038U
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Prior art keywords
led
encapsulating structure
substrate
chip
led chip
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Expired - Fee Related
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CN201320891378.6U
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English (en)
Inventor
吴叶青
张月强
张奕聪
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FUJIAN LIGHTNING OPTOELECTRONIC Co Ltd
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LIGHTNING OPTOECTRONIC TECHNOLOGY (SHENZHEN) CO LTD
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Priority to CN201320891378.6U priority Critical patent/CN203883038U/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item

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Abstract

本申请公开了一种LED封装结构，包括：设置有围墙结构的LED支架，所述围墙结构的内侧构成所述LED支架的贴片区；至少一个贴设于所述LED支架贴片区的LED芯片；以及设置于所述围墙结构内且覆盖于所述LED芯片表面的荧光膜。本申请的LED封装结构，通过设置荧光膜，在提高LED器件光效的同时实现LED器件的微型化，且降低了制造成本。

Description

LED封装结构
技术领域
本申请涉及LED封装技术领域，尤其涉及一种LED封装结构。
背景技术
发光二极管（Light Emitting Diode，简称LED）是一种可直接把电转化为可见光的固态的半导体器件，与同类产品相比，其因功耗低、寿命长、光效高、无辐射、体积小且响应时间短等优点而逐渐成为主流的光源器件。
随着LED封装技术的不断创新以及国内外节能减排政策的执行，LED光源应用在照明领域的比例日益增大。目前业界通常采用的LED封装结构是采用固晶焊线工艺将LED芯片固定于LED基板上，并在LED芯片表面涂覆荧光胶，以最终形成LED器件。
发明人在具体实施过程中，发现现有技术的LED封装结构至少存在如下技术问题：
1、这种LED封装结构的光利用率较低，光效较差，影响LED的整体性能；
2、由于电子产品不断朝向轻薄、短小、高效等特性发展，现有LED器件受封装结构所限，无法进一步实现微型化，限制了LED的推广应用；
3、由于现有LED封装工艺较复杂，导致LED器件制造成本居高不下。
发明内容
本申请提供一种LED封装结构，可有效提高光效，实现微型化，并降低制造成本。
本申请提供一种LED封装结构，包括：
设置有围墙结构的LED支架，所述围墙结构的内侧构成所述LED支架的贴片区；
至少一个贴设于所述LED支架贴片区的LED芯片；以及
设置于所述围墙结构内且覆盖于所述LED芯片表面的荧光膜。
进一步地，所述荧光膜真空压制于所述LED芯片表面。
进一步地，所述LED支架包括基板，所述基板的朝向所述围墙结构一侧设置有电路层，所述LED芯片贴设于所述电路层上。
进一步地，所述LED芯片通过金线或铝线与所述电路层电连接。
进一步地，所述基板为陶瓷基板、铝基板或铜基板。
进一步地，所述LED支架包括绝缘基座及嵌设于所述绝缘基座底部的基板，所述基板的上表面外露于所述围墙结构内并构成所述贴片区。
进一步地，所述绝缘基座采用热固性材料，或者所述绝缘基座为陶瓷基座。
进一步地，所述基板为镀银或镀金的高导热铜板，或者为镀银或镀金的合金铜板。
进一步地，所述LED芯片通过金线或铝线与所述基板的引脚相连。
本申请的有益效果是：
通过提供一种LED封装结构，真空压制荧光膜，在有效提高光效的同时降低LED封装结构的厚度，实现LED器件的微型化; 由于本申请的LED封装结构简化了制造流程，减少了制造材料，进而降低了制造成本。
附图说明
图1为本申请LED封装结构第一种实施例的结构示意图。
图2为本申请LED封装结构第二种实施例的结构示意图。
具体实施方式
下面通过具体实施方式结合附图对本申请作进一步详细说明。
如图1、图2所示，本申请提供一种LED封装结构，包括设置有围墙结构11的LED支架10、至少一个贴设于所述LED支架10上的LED芯片20，以及设置于所述LED芯片20上且覆盖于所述LED芯片20表面的荧光膜30。所述围墙结构11的内侧构成所述LED支架10的贴片区，所述LED芯片20贴设于所述LED支架10的贴片区。
本申请中，所述荧光膜30为荧光粉与硅胶充分混合均匀后制成的薄膜材料。封装时，先将所述LED芯片20贴设于所述LED支架10的贴片区，然后放置所述荧光膜30，并对所述荧光膜30与所述LED芯片20之间的空间进行抽真空，使所述荧光膜30与所述LED芯片20紧密贴合，最后使用真空压片机将所述荧光膜30压制固定于所述围墙结构11内。
于所述LED芯片20表面真空压制所述荧光膜30，使得所述荧光膜30与所述LED芯片20表面无间隙，在充分保护LED芯片的同时，提高光利用率；同时，用所述荧光膜30替代传统的荧光胶，利用所述荧光膜30薄的特性，有效降低所述LED封装结构的整体厚度，形成微型LED器件，大大提高LED的推广应用；而且，本申请的LED封装结构充分简化了制造流程，减少了制造材料，进而降低了LED器件的整体制造成本。
请参考图１所示的第一种实施例，所述LED支架10包括基板12，所述围墙结构11采用注塑等工艺压注成型于所述基板12上。所述基板12的朝向所述围墙结构11一侧设置有电路层121，所述LED芯片20直接贴设于所述电路层121上。
本实施例中，所述基板12可根据实际设计需求设置为陶瓷基板、铝基板或铜基板，所述LED芯片20通过金属线40与所述基板12上的电路层121电连接。所述金属线40具体可设置为金线或铝线。
请参考图2所示的第二种实施例，本实施例中，所述LED支架10包括基板12及绝缘基座13，所述基板12嵌设于所述绝缘基座13底部，其上表面外露于所述围墙结构11内以构成所述贴片区。
本申请中，所述绝缘基座13采用热固性材料，其与所述围墙结构11优选设置为一体注塑成型。所述热固性材料具体可为玻璃纤维、聚邻苯二甲酰胺（Polyphthalamide，简称PPA）、环氧树脂、硅胶或硅树脂。作为又一种实施方式，所述绝缘基座13也可设置为陶瓷基座。
所述基板12优选设置为金属基板。所述金属基板具体可为镀银或镀金的高导热铜板，或者为镀银或镀金的合金铜板。
所述LED芯片20容置于所述围墙结构11内，其采用焊接等工艺固定于所述基板12的上表面，本申请中，所述LED芯片20通过金属线40与所述基板的引脚相连。所述金属线40具体可设置为金线或铝线。
以上内容是结合具体的实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换。

Claims (9)

1.一种LED封装结构，其特征在于，包括： 
设置有围墙结构的LED支架，所述围墙结构的内侧构成所述LED支架的贴片区；至少一个贴设于所述LED支架贴片区的LED芯片；以及 
设置于所述围墙结构内且覆盖于所述LED芯片表面的荧光膜, 
所述荧光膜为荧光粉与硅胶充分混合均匀后制成的薄膜材料。 
2.如权利要求1所述的LED封装结构，其特征在于，所述荧光膜真空压制于所述LED芯片表面。 
3.如权利要求1或2所述的LED封装结构，其特征在于，所述LED支架包括基板，所述基板的朝向所述围墙结构一侧设置有电路层，所述LED芯片贴设于所述电路层上。 
4.如权利要求3所述的LED封装结构，其特征在于，所述LED芯片通过金线或铝线与所述电路层电连接。 
5.如权利要求3所述的LED封装结构，其特征在于，所述基板为陶瓷基板、铝基板或铜基板。 
6.如权利要求1或2所述的LED封装结构，其特征在于，所述LED支架包括绝缘基座及嵌设于所述绝缘基座底部的基板，所述基板的上表面外露于所述围墙结构内并构成所述贴片区。 
7.如权利要求6所述的LED封装结构，其特征在于，所述绝缘基座采用热固性材料，或者所述绝缘基座为陶瓷基座。 
8.如权利要求6所述的LED封装结构，其特征在于，所述基板为镀银或镀金的高导热铜板，或者为镀银或镀金的合金铜板。 
9.如权利要求6所述的LED封装结构，其特征在于，所述LED芯片通过金线或铝线与所述基板的引脚相连。 
CN201320891378.6U 2013-12-31 2013-12-31 Led封装结构 Expired - Fee Related CN203883038U (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108666307A (zh) * 2017-03-28 2018-10-16 江苏博睿光电有限公司 一种csp光源及其制备方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108666307A (zh) * 2017-03-28 2018-10-16 江苏博睿光电有限公司 一种csp光源及其制备方法
CN108666307B (zh) * 2017-03-28 2020-07-28 江苏博睿光电有限公司 一种csp光源及其制备方法

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Address after: The Town Lake Anxi County of Quanzhou City, Fujian province 362411 Photoelectric Industrial Park

Patentee after: FUJIAN LIGHTNING OPTOELECTRONIC CO., LTD.

Address before: Baoan District Shiyan street Shenzhen city Guangdong province 518000 South Road community should be one stone Wentao Science Park building B

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Granted publication date: 20141015

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