CN203772423U - Readout circuit adopting background suppression structure provided with memory function - Google Patents
Readout circuit adopting background suppression structure provided with memory function Download PDFInfo
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- CN203772423U CN203772423U CN201420028379.2U CN201420028379U CN203772423U CN 203772423 U CN203772423 U CN 203772423U CN 201420028379 U CN201420028379 U CN 201420028379U CN 203772423 U CN203772423 U CN 203772423U
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Abstract
The utility model discloses a readout circuit adopting a background suppression structure provided with a memory function. The circuit adopts a background suppression circuit module provided with the memory function. During the use, the steps are as follows: firstly, copying and memorizing mean current of background electric current of four picture elements which are arrayed in a two-line and two-row manner; secondly, taking the mean current as the background electric current of the four picture elements, and deducting the mean current from photoelectric current; thirdly, integrating through an SBDI preposed input stage circuit module adopting a high-gain shared negative feedback operational amplifier to obtain a voltage signal, and sampling the signal onto a sampling capacitor through a sampling holding circuit module; and finally, outputting an analog signal through a unit gain output stage module. The readout circuit realizes the memory of the background electric current of different picture elements, and deducts the background electric current before the signal processing, so that the integral time is effectively prolonged, the contrast degree is increased, and the signal-to-noise ratio of the output signal is increased.
Description
Technical field
This patent relates to infrared focal plane readout integrated circuit, specifically refer to a kind of have that memory function background suppresses structure read integrated circuit (Readout Integrated Circuit-ROIC), it is for very long wave infrared focal plane array (Infrared Focus Plane Array-IRFPA), each pixel background current of detector accurately can be copied to memory, and reduce from photocurrent, only efficient light marking current is carried out to integration amplification, sampling maintenance and signal output.
Background technology
Very long wave infrared focus plane is the core devices in advanced infrared system.Infrared focal plane array is generally comprised of two parts: infrared detector array and sensing circuit array.Infrared eye on focal plane, after receiving the infrared radiation of incident, produces a partial charge relevant with incident infrared radiation property on the incoming position of infrared radiation, is transferred to corresponding sensing circuit unit.Sensing circuit will carry out integration amplification to these electric signal, sampling keeps, then cushion and multiplex system by output, finally send to surveillance and form image.
Because very long wave infrared eye energy gap is narrow, in growth course, be very easy to be subject to the various factors such as material, growth technique, laboratory environment.Limited by existing process conditions, present stage himself equivalent resistance of very long wave detector smaller, be generally less than 10K Ω; Therefore, the input resistance of sensing circuit input stage must be very little.Meanwhile, in order to prevent excessive leakage current, detector must operate at accurately under " zero partially " state.In addition, very long wave detector dark current is larger, and is operated under high background condition, sensing circuit integrating capacitor is very easy to saturated, is difficult to obtain desirable signal to noise ratio (snr).The defect of very long wave detector self performance, has limited to a great extent the performance of very long wave infrared focus plane, and sensing circuit design has been proposed to very high requirement.
Owing to having used negative feedback amplifier, generally adopt the structures such as BDI, CTIA, BGMI as the preposition input stage of very long wave infrared focal plane read-out circuit.Under regular situation, adopt one-stage amplifier or five pipe differential amplifiers, although its low-temperature working is functional, because gain is lower, photocurrent injection efficiency is very low, detector job insecurity, and noise is larger, is difficult to practical requirement.In addition, it is to use simple voltage-current conversion method that existing background suppresses circuit a kind of, and its precision is low, and it is all after the ascending pipe as for the preposition input stage of BDI, is subject to the impact of metal-oxide-semiconductor channel-length modulation, and the background current of generation is unstable; The background that another kind has memory function suppresses circuit due to its complex structure, and area occupied is large, is difficult to realize in unit.Meanwhile, sensing circuit cellar area is limited, and must use larger integrating capacitor and sampling capacitance, and the two is difficult to trade off.
Summary of the invention
The object of this patent is to provide a kind of sensing circuit that memory function background suppresses structure that has.This circuit is applicable to very long wave infrared focal plane array, its by background current automatic average corresponding to each pixel of detector, copy, remember, adopt 2 * 2 to share the preposition input stage module of SBDI as input stage, solve existing background inhibition precision low, cannot complete separately and copy memory each pixel, signals collecting difficulty is large, the problem that collection signal signal to noise ratio (S/N ratio) is lower.
This circuit suppresses circuit module, the preposition input stage module of SBDI, sampling hold circuit module, current mirror circuit module, unity gain output level module and sequential control circuit module composition by background; It is characterized in that:
Described background suppresses its structure of circuit module and comprises simple mirror image circuit, 3 memories electric capacity, electrostatic storage tube and 4 metal-oxide-semiconductor gauge tap, and it is that NMOS pipe and a pair of breadth length ratio of 2: 1 and 1: 1 is that the PMOS pipe of 5: 1 and 1: 1 forms that wherein said simple mirror image circuit has a pair of breadth length ratio; Described 3 memory electric capacity are 500fF, 50fF and tri-NW electric capacity of 500fF, their formation ring-types that joins end to end, two 500fF memory electric capacity termination power VDD that are connected; Described electrostatic storage tube adopts the PMOS pipe that breadth length ratio is 4: 3, and its source S end is connected with the output terminal of simple mirror image circuit, and drain D end opens the light and is connected with control, and grid G end joins with the end that is connected of 50fF with a 500fF; 4 described metal-oxide-semiconductor gauge tap are two pairs is managed and a switch that PMOS virtual tube forms by a NMOS, wherein NMOS pipe φ
1with PMOS virtual tube
the gauge tap one end forming connects the grid G end of electrostatic storage tube, and the other end connects the drain D end of electrostatic storage tube, and NMOS manages φ
2with PMOS virtual tube
the gauge tap one end forming connects the end that joins of second 500fF and 50fF memory electric capacity, and the other end connects the drain D end of electrostatic storage tube;
The preposition input stage module of described SBDI adopts the direct injection circuit structure of shared buffer, the metal-oxide-semiconductor being used separately by eight shared metal-oxide-semiconductors of Mg0～Mg7 and 12 each pixels of Mg8～Mg19 forms the negative feedback amplifier of SBDI input stage module, and the integrating capacitor in the direct injection circuit of described shared buffer adopts NW electric capacity;
The four NMOS pipe that described current mirror circuit module is respectively 3: 3,12: 3,3: 3,12: 3 by breadth length ratio forms;
Described unity gain output level module adopts the five pipe differential operational amplifiers that increased by two control tubes;
Its annexation is: by the preposition input stage module of SBDI, gather detector current signal, suppress circuit module and be connected, and through passage II, feed back to the input end of the preposition input stage module of SBDI through the current mirror circuit module of interface channel I and background; Follow-up connection sampling hold circuit module, two modules of unity gain output level module, sample, keep, amplify processing to signal.Sequential control circuit module is directly connected with the preposition input stage module of SBDI, sampling hold circuit module, unity gain output level module, by control bus, directly controls this three modules, and by these three modules, indirectly controls background and suppress circuit module.
Its principle of work is: circuit provides control signal by sequential control circuit module, the work of each functional module of control circuit, during work, first by detector as under the full background without useful signal, closing passage II, open channel I, is read 2 * 2 total background currents of pixel by the preposition input stage module of SBDI, and by current mirror circuit module, complete equalization and operate, the background with memory function suppresses circuit module and accurately copies memory background current; Then by detector as in normal environment for use, open channel II, closing passage I, before the preposition input stage module of SBDI is carried out integration to detector photocurrent in advance by the background current composition subduction in detector photocurrent; The amplification integration, the sampling that finally by the preposition input stage module of SBDI, sampling hold circuit module and unity gain output level module, are completed useful signal circuit keep and output.
The advantage of this patent is:
(1) adopt 2 * 2 pixel shared structures, well realized the compromise of area, precision and performance in SBDI unit, for equiva lent impedance own is low, and the very long wave focal plane arrays (FPA) being operated under high background provides a kind of sensing circuit solution route.Within the scope of the marking current of 0.1uA-1uA, output area is 3V, and frequency of operation reaches 2.5MHz.Negative feedback amplifier adopts shares telescoping structure, makes the injection efficiency of photocurrent be greater than 99%, and the linearity of output signal is better than 99%, and detector maintains accurately " zero partially " state.
(2) background suppress circuit module copy accurately, on average, the background current of four pixels of memory.C
m0, C
m1and C
m2remember electric capacity due to the effect of clamping down on of two tie point A, B for three, so antijamming capability is stronger, electric current jitter error is less.In addition, the background current before preposition input stage is processed photocurrent in subduction Primary photocurrent, has effectively extended integral time, has increased contrast, has improved the signal to noise ratio (S/N ratio) of output signal.For very long wave infrared focal plane detector is applied technical support is provided under high background environment.
Accompanying drawing explanation
Fig. 1 is whole each circuit function module and the workflow diagram of reading integrated circuit.
Fig. 2 is the preposition input stage modular structure of the SBDI figure that reads integrated circuit.Wherein S1～S4 is detector gating switch, and T1～T4 is ascending pipe gating switch, and ST is the integration sampling gauge tap that copies memory and useful signal of background current, and these switches all adopt passgate structures.
Fig. 3 shares telescopic OPAMP structural drawing.Wherein AS0～AS4 is the gating switch of amplifier, when preposition input stage is without when work, can close this five switches, can effectively reduce chip power-consumption.
Fig. 4 is sampling hold circuit module and unity gain output level module circuit structure diagram.Integrating capacitor is reset to high level, and sampling capacitance is reset to low level.SIIN is marking current passage.
Fig. 5 is that current mirror circuit module and background suppress circuit modular structure figure.Gauge tap in passage I and passage II adopts transmission gate, and memory capacitor charging gauge tap increases PMOS virtual tube.Gauge tap VSUP controls whether use background inhibition structure, widens the range of application that this reads integrated circuit.
Fig. 6 is the differential amplifier that unity gain output level module is used.PLUS is gating switch, and VBIA is amplifier bias voltage control end.
Embodiment
(1) the preposition input stage of sensing circuit adopts 2 * 2 SBDI structures that pixel is shared, comprises operational amplifier, ascending pipe, integrating capacitor and sampling capacitance.Wherein integrating capacitor size is 1pF～9pF, and sampling capacitance is 0.1pF.The breadth length ratio of ascending pipe M1～M4 is 6: 1.5.
(2) negative feedback amplifier adopts shares telescoping structure, makes the setting of the setting coincidence detector bias voltage 1.8V of its common port.The breadth length ratio of Mg0～Mg16 is 2: 1,4: 0.54,4: 1.5,4: 1.5,6: 1.5,6: 1.5,6: 1.5,6: 1.5,4: 1.5,4: 1.5,4: 0.54,4: 1.5,4: 1.5,4: 0.54,4: 1.5,4: 1.5,4: 0.54.
(3) in Fig. 5, the breadth length ratio of current mirror circuit module M1～M4 is: 3: 3,12: 3,3: 3,12: 3.The bias voltage of Vb determines by the overdrive voltage of M1 and M3, and this example is 1.1V.
(4) background suppresses circuit module reference current I
rEFbackground current by actual working environment determines, adopts 5uA in this example.Wherein to have a pair of breadth length ratio be that NMOS pipe and a pair of breadth length ratio of 2: 1 and 1: 1 is that the PMOS pipe of 5: 1 and 1: 1 forms to simple mirror image circuit, and by 2: 1 and 5: 1 twice mirror image, theory is contracted to I by electric current
rEF/ 10, the actual Iback of obtaining is about 0.8uA.Memory electric capacity adopts 500fF, 50fF and tri-NW electric capacity of 500fF; Gauge tap adopts transmission gate or increases virtual tube.
(5) adopt unity gain output level module as the output buffering of sensing circuit, reduced the load capacitance of front stage circuits, strengthened the driving force of circuit.Concrete size can be set voluntarily according to the driving force of actual requirement and power consumption.
In sum, use that this patent adopts share the preposition input stage module of SBDI of telescopic OPAMP, the background with memory function suppress circuit module, sampling hold circuit module and the application design proposal of unity gain output level module in very long wave infrared focal plane array rationally, practical, efficient, for reading of very long wave infrared detector focal plane array signal provides a kind of solution effectively.
Claims (1)
1. have the integrated circuit of reading that memory function background suppresses structure, it suppresses circuit module, the preposition input stage module of SBDI, sampling hold circuit module, current mirror circuit module, unity gain output level module and sequential control circuit module composition by background; Its module is characterised in that:
Described background suppresses its structure of circuit module and comprises simple mirror image circuit, 3 memories electric capacity, electrostatic storage tube and 4 metal-oxide-semiconductor gauge tap, and it is that NMOS pipe and a pair of breadth length ratio of 2: 1 and 1: 1 is that the PMOS pipe of 5: 1 and 1: 1 forms that wherein said simple mirror image circuit has a pair of breadth length ratio; Described 3 memory electric capacity are 500fF, 50fF and tri-NW electric capacity of 500fF, their formation ring-types that joins end to end, two 500fF memory electric capacity termination power VDD that are connected; Described electrostatic storage tube adopts the PMOS pipe that breadth length ratio is 4: 3, and its source S end is connected with the output terminal of simple mirror image circuit, and drain D end opens the light and is connected with control, and grid G end joins with the end that is connected of 50fF with a 500fF; 4 described metal-oxide-semiconductor gauge tap are two pairs is managed and a switch that PMOS virtual tube forms by a NMOS, wherein NMOS pipe φ
1with PMOS virtual tube
the gauge tap one end forming connects the grid G end of electrostatic storage tube, and the other end connects the drain D end of electrostatic storage tube, and NMOS manages φ
2with PMOS virtual tube
the gauge tap one end forming connects the end that joins of second 500fF and 50fF memory electric capacity, and the other end connects the drain D end of electrostatic storage tube;
The preposition input stage module of described SBDI adopts the direct injection circuit structure of shared buffer, the metal-oxide-semiconductor being used separately by eight shared metal-oxide-semiconductors of Mg0～Mg7 and 12 each pixels of Mg8～Mg19 forms the negative feedback amplifier of SBDI input stage module, and the integrating capacitor in the direct injection circuit of described shared buffer adopts NW electric capacity;
The annexation of reading integrated circuit is: by the preposition input stage module of SBDI, gather detector current signal, current mirror circuit module through interface channel I is connected with background inhibition circuit module, and through passage II, feeds back to the input end of the preposition input stage module of SBDI; Follow-up connection sampling hold circuit module, two modules of unity gain output level module, sample, keep, amplify processing to signal.Sequential control circuit module is directly connected with the preposition input stage module of SBDI, sampling hold circuit module, unity gain output level module, by control bus, directly controls this three modules, and by these three modules, indirectly controls background and suppress circuit module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420028379.2U CN203772423U (en) | 2013-04-26 | 2014-01-17 | Readout circuit adopting background suppression structure provided with memory function |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310150721.6 | 2013-04-26 | ||
| CN 201310150721 CN103247636A (en) | 2013-04-26 | 2013-04-26 | Readout integrated circuit adopting background suppression structure provided with memory function |
| CN201420028379.2U CN203772423U (en) | 2013-04-26 | 2014-01-17 | Readout circuit adopting background suppression structure provided with memory function |
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| CN203772423U true CN203772423U (en) | 2014-08-13 |
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| CN 201310150721 Pending CN103247636A (en) | 2013-04-26 | 2013-04-26 | Readout integrated circuit adopting background suppression structure provided with memory function |
| CN201410020965.7A Active CN103852174B (en) | 2013-04-26 | 2014-01-17 | There is the reading integrated circuit of memory function background suppression structure |
| CN201420028379.2U Expired - Fee Related CN203772423U (en) | 2013-04-26 | 2014-01-17 | Readout circuit adopting background suppression structure provided with memory function |
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| CN201410020965.7A Active CN103852174B (en) | 2013-04-26 | 2014-01-17 | There is the reading integrated circuit of memory function background suppression structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103852174A (en) * | 2013-04-26 | 2014-06-11 | 中国科学院上海技术物理研究所 | Readout integrated circuit of background suppression structure with memory function |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104864966A (en) * | 2015-04-03 | 2015-08-26 | 燕山大学 | Microscopic thermal imaging method |
| CN105222900B (en) * | 2015-09-15 | 2018-09-28 | 工业和信息化部电子第五研究所 | Infrared focal plane array reading circuit |
| CN111277251B (en) * | 2020-02-20 | 2023-03-14 | 西北工业大学 | Self-triggering power supply control low-power consumption front end reading circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6373050B1 (en) * | 1998-10-07 | 2002-04-16 | California Institute Of Technology | Focal plane infrared readout circuit with automatic background suppression |
| US20020063198A1 (en) * | 2000-10-26 | 2002-05-30 | Krymski Alexander I. | Frame shutter for CMOS APS |
| JP4307322B2 (en) * | 2004-05-18 | 2009-08-05 | キヤノン株式会社 | Radiation imaging apparatus and radiation imaging system |
| CN2754070Y (en) * | 2004-10-22 | 2006-01-25 | 重庆大学 | Background current inhibition reading-out circuit for infrared focal plane array |
| CN101582978B (en) * | 2009-06-18 | 2011-02-09 | 东南大学 | Background suppression method for infrared reading circuit and circuit thereof |
| CN101634593B (en) * | 2009-08-14 | 2010-10-27 | 东南大学 | Stage background inhibiting infrared focal plane unit circuit |
| CN101650223A (en) * | 2009-09-10 | 2010-02-17 | 天津大学 | Digitized photoelectric detector sensing circuit |
| CN103247636A (en) * | 2013-04-26 | 2013-08-14 | 中国科学院上海技术物理研究所 | Readout integrated circuit adopting background suppression structure provided with memory function |
-
2013
- 2013-04-26 CN CN 201310150721 patent/CN103247636A/en active Pending
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2014
- 2014-01-17 CN CN201410020965.7A patent/CN103852174B/en active Active
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103852174A (en) * | 2013-04-26 | 2014-06-11 | 中国科学院上海技术物理研究所 | Readout integrated circuit of background suppression structure with memory function |
| CN103852174B (en) * | 2013-04-26 | 2016-08-17 | 中国科学院上海技术物理研究所 | There is the reading integrated circuit of memory function background suppression structure |
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| Publication number | Publication date |
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| CN103852174A (en) | 2014-06-11 |
| CN103852174B (en) | 2016-08-17 |
| CN103247636A (en) | 2013-08-14 |
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Granted publication date: 20140813 Termination date: 20170117 |
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