CN103852174A - Readout integrated circuit of background suppression structure with memory function - Google Patents

Abstract

The invention discloses a readout integrated circuit of a background suppression structure with the memory function. According to the circuit, due to the fact that a background suppression circuit module with the memory function is adopted, firstly, the average current of background currents of four pixels arranged in a 2*2 mode is copied and memorized, then the current serves as the background currents of the four pixels to be removed out of a light current, then, the current is integrated by an SBDI pre-posed input stage circuit module of a high-gain shared-type negative feedback operational amplifier to obtain a voltage signal, the signal is sampled to a sampling capacitor through a sample hold circuit module, and an analog signal is output through a unit gain output stage module. Different pixel background currents can be memorized through the circuit, the background currents are reduced before signal processing, the integrating time is effectively prolonged, the contrast ratio is increased, and the signal to noise ratio of the output signal is increased.

Description

There is the integrated circuit of reading that memory function background suppresses structure

Technical field

The present invention relates to infrared focal plane readout integrated circuit, specifically refer to a kind of have that memory function background suppresses structure read integrated circuit (Readout Integrated Circuit-ROIC), it is for very long wave infrared focal plane array (Infrared Focus Plane Array-IRFPA), each detector pixel background current accurately can be copied to memory, and reduce from photocurrent, only efficient light marking current is carried out to integration amplification, sampling maintenance and signal output.

Background technology

Very long wave infrared focus plane is the core devices in advanced infrared system.Infrared focal plane array is generally made up of two parts: infrared detector array and sensing circuit array.Infrared eye on focal plane is receiving after the infrared radiation of incident, produces a partial charge relevant with incident infrared radiation property on the incoming position of infrared radiation, is transferred to corresponding sensing circuit unit.Sensing circuit will carry out integration amplification to these electric signal, sampling keeps, then cushion and multiplex system by output, finally send to surveillance and form image.

Because very long wave infrared eye energy gap is narrow, in growth course, be very easy to be subject to the various factors such as material, growth technique, laboratory environment.Limited by existing process conditions, present stage himself equivalent resistance of very long wave detector smaller, be generally less than 10K Ω; Therefore, the input resistance of sensing circuit input stage must be very little.Meanwhile, in order to prevent excessive leakage current, detector must operate at accurately under " zero is inclined to one side " state.In addition, very long wave detector dark current is larger, and is operated under high background condition, sensing circuit integrating capacitor is very easy to saturated, is difficult to obtain desirable signal to noise ratio (snr).The defect of very long wave detector self performance, has limited to a great extent the performance of very long wave infrared focus plane, and sensing circuit design has been proposed to very high requirement.

Owing to having used negative feedback amplifier, generally adopt the preposition input stage of the structures such as BDI, CTIA, BGMI as very long wave infrared focal plane read-out circuit.Under regular situation, adopt one-stage amplifier or five pipe differential amplifiers, although its low-temperature working is functional, because gain is lower, photocurrent injection efficiency is very low, detector job insecurity, and noise is larger, is difficult to practical requirement.In addition, it is to use simple voltage-current conversion method that existing background suppresses circuit one, and its precision is low, and it is all after the ascending pipe as for the preposition input stage of BDI, is subject to the impact of metal-oxide-semiconductor channel-length modulation, and the background current of generation is unstable; The background that another kind has memory function suppresses circuit due to its complex structure, and area occupied is large, is difficult to realize in unit.Meanwhile, sensing circuit cellar area is limited, and must use larger integrating capacitor and sampling capacitance, and the two is difficult to trade off.

Summary of the invention

The object of this invention is to provide a kind of integrated circuit of reading that memory function background suppresses structure that has.This circuit is applicable to very long wave infrared focal plane array, its by background current automatic average corresponding each pixel of detector, copy, remember, adopt 2 × 2 to share the preposition input stage module of SBDI as input stage, solve existing background inhibition precision low, cannot complete separately and copy memory each pixel, signals collecting difficulty is large, the problem that collection signal signal to noise ratio (S/N ratio) is lower.

The object of the invention is to realize by following technological approaches:

The invention discloses a kind of integrated circuit of reading that memory function background suppresses structure that has, adopt HHNEC0.35um1P4M standard CMOS process, at EDA(Electronic Design Automatic electric design automation) build circuit in design platform, main realize to the background of detector signal suppress, amplify integration, sampling keeps and output.This circuit comprises following functions module: background suppresses circuit module, the preposition input stage module of SBDI, sampling hold circuit module, current mirror circuit module, unity gain output-stage circuit module and sequential control circuit module, wherein:

(1) the preposition input stage module of SBDI adopts the direct injection circuit structure of shared buffer (Shared Buffered Direct Injection-SBDI), as shown in Figure 2, wherein negative feedback computing adopts and shares telescoping structure, as shown in Figure 3, the metal-oxide-semiconductor that it is used separately by eight shared metal-oxide-semiconductors of Mg0～Mg7 and 12 each pixels of Mg8～Mg19 forms the negative feedback amplifier of SBDI input stage module; This amplifier open-loop gain A is greater than 80dB, and now the injection efficiency of photocurrent reaches 99%; Integrating capacitor in the direct injection circuit of described shared buffer adopts NW electric capacity; Meanwhile, design operational amplifier makes the setting of its common port input coincidence detector bias voltage.This circuit module is responsible for detector photo-signal to read, in order to complete the follow-up integration sampling that copies memory and efficient light signal to background current; And make detector maintain accurate little reverse-biased state.

(2) sampling hold circuit module is directly controlled by transmission gate, as shown in Figure 4, integrated signal is transferred to sampling capacitance by integrating capacitor.Its principle of work is as follows: after integrating capacitor C1, C2 are reset to high level, start integration; Meanwhile, before SEL closure, sampling capacitance C3 is reset to low level 0V.After integration completes, closed SEL switch, transfers to sampling capacitance C3 by the integral charge on C1, C2 and gets on, and its sample voltage value is:

$U_{\mathrm{samp}}=\frac{U_{\mathrm{int}}(C_1+C_2)}{C_1+C_2+C_3+C^{\′}}---\left(1\right)$

Wherein, U _intfor the integral voltage on integrating capacitor C1 and C2, U _sampfor the employing voltage on sampling capacitance C3, C' is the stray capacitance of M2 tube grid and plain conductor.Electric charge has shifted rear SEL and has opened, and now signal has been transferred to sampling capacitance C3.Integrating capacitor can again reset and start the integration of next frame; Meanwhile, the voltage signal on sequential control circuit module controls down-sampling electric capacity starts to read, and wherein Change of integral time signal INCT opens than integrating capacitor reset signal RST1 and closes 1us in advance.

(3) the NMOS pipe that in Fig. 5, current mirror circuit module is respectively 3:3,12:3,3:3,12:3 by M1, M2, M3 and tetra-breadth length ratios of M4 forms, and 2 × 2 total background currents of pixel that SBDI is read average operation.

(4) background that has a memory function suppresses circuit module its structure and comprises simple mirror image circuit, 3 memories electric capacity, electrostatic storage tube and 4 metal-oxide-semiconductor gauge tap, and wherein to have a pair of breadth length ratio be that the PMOS pipe that NMOS pipe and a pair of breadth length ratio of 2:1 and 1:1 is 5:1 and 1:1 forms to simple mirror image circuit; Described memory electric capacity adopts 500fF, 50fF and tri-NW electric capacity of 500fF, their formation ring-types that joins end to end, two 500fF memory electric capacity termination power VDD that are connected; Described electrostatic storage tube adopts the PMOS pipe that breadth length ratio is 4:3, and its source S end is connected with the output terminal of simple mirror image circuit, and drain D end opens the light and is connected with control, and grid G end joins with the end that is connected of 50fF with a 500fF; 4 described metal-oxide-semiconductor gauge tap are two pairs is managed and a switch that PMOS virtual tube forms by a NMOS, wherein NMOS pipe φ ₁with PMOS virtual tube

the gauge tap one end forming connects the grid G end of electrostatic storage tube, and the other end connects the drain D end of electrostatic storage tube, and NMOS manages φ ₂with PMOS virtual tube the gauge tap one end forming connects the end that joins of second 500fF and 50fF memory electric capacity, and the other end connects the drain D end of electrostatic storage tube; Its principle of work is as follows: current source is used to provide with reference to background current, and simple mirror image circuit copies reference current, generates a background current roughly; Memory electric capacity completes integration and the memory to accurate background electric current.First simple mirror image circuit is to reference current I _rEFcopy, generate a background current roughly.Then closing passage II, open channel I and memory capacitor charging gauge tap φ ₁and φ ₂, the accurate mirror image circuit of M1～M4 composition forces Iback to equal 2 × 2 pixel average background electric currents, and to C _m0, C _m1and C _m2three memory electric capacity charge, until circuit state complete stability is so far remembered electric capacity and completed accurate memory to producing the required Mmem grid voltage of accurate background electric current.Last open channel II, closing passage I and memory capacitor charging gauge tap φ ₁and φ ₂, before the preposition input stage of SBDI is carried out integration to detector photocurrent, in advance the background current composition in detector photocurrent is reduced.

(5) adopt unity gain amplifier component unit gain output level module in Fig. 5, reduce front stage circuits load request, the driving force of intensifier circuit, read-out speed and the output voltage swing of raising circuit, the differential amplifier detailed construction that unity gain output level module adopts is as shown in Figure 6.

The annexation of reading integrated circuit is: gather detector current signal by the preposition input stage module of SBDI, suppress circuit module through the current mirror circuit module of interface channel I with background and be connected, and feed back to the input end of the preposition input stage module of SBDI through passage II; Follow-up connection sampling hold circuit module, two modules of unity gain output level module, sample, keep, amplify processing to signal.Sequential control circuit module is directly connected with the preposition input stage module of SBDI, sampling hold circuit module, unity gain output level module, directly controls this three modules by control bus, and indirectly controls background by these three modules and suppress circuit module.

The workflow of whole circuit is as shown in Figure 1: circuit provides control signal by sequential control circuit module, the work of the each functional module of control circuit, when work, first by detector as under the full background without useful signal, closing passage II, open channel I, is read 2 × 2 total background currents of pixel by the preposition input stage module of SBDI, and complete equalization by current mirror circuit module and operate, the background with memory function suppresses circuit module and accurately copies memory background current; Then by detector as in normal environment for use, open channel II, closing passage I, before the preposition input stage module of SBDI is carried out integration to detector photocurrent in advance by the background current composition subduction in detector photocurrent; The amplification integration, the sampling that are finally completed useful signal circuit by the preposition input stage module of SBDI, sampling hold circuit module and unity gain output level module keep and output.

The invention has the advantages that:

(1) adopt 2 × 2 pixel shared structures, well realized the compromise of area, precision and performance in SBDI unit, for equiva lent impedance own is low, and the very long wave focal plane arrays (FPA) being operated under high background provides a kind of sensing circuit solution route.Within the scope of the marking current of 0.1uA-1uA, output area is 3V, and frequency of operation reaches 2.5MHz.Negative feedback amplifier adopts shares telescoping structure, makes the injection efficiency of photocurrent be greater than 99%, and the linearity of output signal is better than 99%, and detector maintains accurately " zero is inclined to one side " state.

(2) background suppress circuit module copy accurately, on average, memory four pixels background current.C _m0, C _m1and C _m2remember the clamp down on effect of electric capacity due to two tie point A, B for three, therefore antijamming capability is stronger, and electric current jitter error is less.In addition, the background current before preposition input stage is processed photocurrent in subduction Primary photocurrent, has effectively extended integral time, has increased contrast, has improved the signal to noise ratio (S/N ratio) of output signal.For very long wave infrared focal plane detector is applied technical support is provided under high background environment.

Accompanying drawing explanation

Fig. 1 is whole each circuit function module and the workflow diagram of reading integrated circuit.

Fig. 2 is the preposition input stage modular structure of the SBDI figure that reads integrated circuit.Wherein S1～S4 is detector gating switch, and T1～T4 is ascending pipe gating switch, and ST is the integration sampling gauge tap that copies memory and useful signal of background current, and these switches all adopt passgate structures.

Fig. 3 shares telescopic OPAMP structural drawing.Wherein AS0～AS4 is the gating switch of amplifier, when preposition input stage is without when work, can close this five switches, can effectively reduce chip power-consumption.

Fig. 4 is sampling hold circuit module and unity gain output level module circuit structure diagram.Integrating capacitor is reset to high level, and sampling capacitance is reset to low level.SIIN is marking current passage.

Fig. 5 is that current mirror circuit module and background suppress circuit modular structure figure.Gauge tap in passage I and passage II adopts transmission gate, and memory capacitor charging gauge tap increases PMOS virtual tube.Whether gauge tap VSUP controls and uses background to suppress structure, the range of application of widening this and reading integrated circuit.

Fig. 6 is the differential amplifier that unity gain output level module is used.PLUS is gating switch, and VBIA is amplifier bias voltage control end.

Embodiment

(1) the preposition input stage of sensing circuit adopts 2 × 2 SBDI structures that pixel is shared, comprises operational amplifier, ascending pipe, integrating capacitor and sampling capacitance.Wherein integrating capacitor size is 1pF～9pF, and sampling capacitance is 0.1pF.The breadth length ratio of ascending pipe M1～M4 is 6:1.5.

(2) negative feedback amplifier adopts shares telescoping structure, makes the setting of the setting coincidence detector bias voltage 1.8V of its common port.The breadth length ratio of Mg0～Mg16 is 2:1,4:0.54,4:1.5,4:1.5,6:1.5,6:1.5,6:1.5,6:1.5,4:1.5,4:1.5,4:0.54,4:1.5,4:1.5,4:0.54,4:1.5,4:1.5,4:0.54.

(3) in Fig. 5, the breadth length ratio of current mirror circuit module M1～M4 is: 3:3,12:3,3:3,12:3.The bias voltage of Vb determines by the overdrive voltage of M1 and M3, and this example is 1.1V.

(4) background suppresses circuit module reference current I _rEFbackground current by actual working environment determines, adopts 5uA in this example.Wherein to have a pair of breadth length ratio be that the PMOS pipe that NMOS pipe and a pair of breadth length ratio of 2:1 and 1:1 is 5:1 and 1:1 forms to simple mirror image circuit, and by 2:1 and twice mirror image of 5:1, electric current is contracted to I by theory _rEF/ 10, the actual Iback of obtaining is about 0.8uA.Memory electric capacity adopts 500fF, 50fF and tri-NW electric capacity of 500fF; Gauge tap adopts transmission gate or increases virtual tube.

(5) adopt the output buffering of unity gain output level module as sensing circuit, reduced the load capacitance of front stage circuits, strengthened the driving force of circuit.Concrete size can be set voluntarily according to the driving force of actual requirement and power consumption.

In sum, use that this invention adopts share the preposition input stage module of SBDI of telescopic OPAMP, the background with memory function suppress circuit module, sampling hold circuit module and the application design proposal of unity gain output level module in very long wave infrared focal plane array rationally, practical, efficient, for reading of very long wave infrared detector focal plane array signal provides one solution effectively.

Claims (1)

1. have the integrated circuit of reading that memory function background suppresses structure, it suppresses circuit module, the preposition input stage module of SBDI, sampling hold circuit module, current mirror circuit module, unity gain output level module and sequential control circuit module composition by background; Its module is characterised in that:

Described background suppresses its structure of circuit module and comprises simple mirror image circuit, 3 memories electric capacity, electrostatic storage tube and 4 metal-oxide-semiconductor gauge tap, and it is that the PMOS pipe that NMOS pipe and a pair of breadth length ratio of 2:1 and 1:1 is 5:1 and 1:1 forms that wherein said simple mirror image circuit has a pair of breadth length ratio; Described 3 memory electric capacity are 500fF, 50fF and tri-NW electric capacity of 500fF, their formation ring-types that joins end to end, two 500fF memory electric capacity termination power VDD that are connected; Described electrostatic storage tube adopts the PMOS pipe that breadth length ratio is 4:3, and its source S end is connected with the output terminal of simple mirror image circuit, and drain D end opens the light and is connected with control, and grid G end joins with the end that is connected of 50fF with a 500fF; 4 described metal-oxide-semiconductor gauge tap are two pairs is managed and a switch that PMOS virtual tube forms by a NMOS, wherein NMOS pipe φ ₁with PMOS virtual tube

the gauge tap one end forming connects the grid G end of electrostatic storage tube, and the other end connects the drain D end of electrostatic storage tube, and NMOS manages φ ₂with PMOS virtual tube

the gauge tap one end forming connects the end that joins of second 500fF and 50fF memory electric capacity, and the other end connects the drain D end of electrostatic storage tube;

The preposition input stage module of described SBDI adopts the direct injection circuit structure of shared buffer, the metal-oxide-semiconductor being used separately by eight shared metal-oxide-semiconductors of Mg0～Mg7 and 12 each pixels of Mg8～Mg19 forms the negative feedback amplifier of SBDI input stage module, and the integrating capacitor in the direct injection circuit of described shared buffer adopts NW electric capacity;

The annexation of reading integrated circuit is: gather detector current signal by the preposition input stage module of SBDI, suppress circuit module through the current mirror circuit module of interface channel I with background and be connected, and feed back to the input end of the preposition input stage module of SBDI through passage II; Follow-up connection sampling hold circuit module, two modules of unity gain output level module, sample, keep, amplify processing to signal.Sequential control circuit module is directly connected with the preposition input stage module of SBDI, sampling hold circuit module, unity gain output level module, directly controls this three modules by control bus, and indirectly controls background by these three modules and suppress circuit module.

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