CN203759203U - Detection circuit of IGBT (insulated gate bipolar transistor) driving board - Google Patents
Detection circuit of IGBT (insulated gate bipolar transistor) driving board Download PDFInfo
- Publication number
- CN203759203U CN203759203U CN201420173564.0U CN201420173564U CN203759203U CN 203759203 U CN203759203 U CN 203759203U CN 201420173564 U CN201420173564 U CN 201420173564U CN 203759203 U CN203759203 U CN 203759203U
- Authority
- CN
- China
- Prior art keywords
- unit
- input
- output terminal
- drive plate
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000001514 detection method Methods 0.000 title abstract description 6
- 238000012545 processing Methods 0.000 claims abstract description 45
- 238000012360 testing method Methods 0.000 claims abstract description 20
- 238000004088 simulation Methods 0.000 claims description 28
- 238000002955 isolation Methods 0.000 claims description 11
- 238000012423 maintenance Methods 0.000 abstract description 3
- 238000005457 optimization Methods 0.000 abstract description 3
- 101001122448 Rattus norvegicus Nociceptin receptor Proteins 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 102100031024 CCR4-NOT transcription complex subunit 1 Human genes 0.000 description 2
- 102100031025 CCR4-NOT transcription complex subunit 2 Human genes 0.000 description 2
- 101000919674 Caenorhabditis elegans CCR4-NOT transcription complex subunit let-711 Proteins 0.000 description 2
- 101001092183 Drosophila melanogaster Regulator of gene activity Proteins 0.000 description 2
- 101000919672 Homo sapiens CCR4-NOT transcription complex subunit 1 Proteins 0.000 description 2
- 101000919667 Homo sapiens CCR4-NOT transcription complex subunit 2 Proteins 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The utility model discloses a detection circuit of an IGBT (insulated gate bipolar transistor) driving board. The detection circuit comprises an analog pulse output unit, an analog pulse input unit, a feedback input unit, a logic processing unit, a fault locking unit and a fault resetting unit, the analog pulse output unit is connected with an input end of the IGBT driving board and an input end of the logic processing unit, an input end of the analog pulse input unit is connected with an output end of the IGBT driving board while an output end of the same is connected with the input end of the logic processing unit, an input end of the feedback input unit is connected with the output end of the IGBT driving board while an output end of the same is connected with the input end of the logic processing unit, and an output end of the logic processing unit is connected with the fault locking unit which is connected with the fault resetting unit. The detection circuit is simple in structure, low in cost and wide in application range, time for testing the IGBT driving board is greatly reduced, and great optimization is brought to maintenance and operation of places applying the IGBT driving board.
Description
Technical field
The utility model relates to field of power electronics, particularly a kind of testing circuit of IGBT drive plate.
Background technology
Along with the application of semiconductor devices IGBT in electronic power convertor technology is more and more extensive; IGBT drive plate is as the Primary Component connecting between master controller and IGBT; there is the isolation of paired pulses control signal and amplify, drive the effect of IGBT; and there is overcurrent, short-circuit detecting; overvoltage, under-voltage and the dead time and corresponding defencive function, the reliably working of guarantee IGBT.Traditional IGBT drive plate detection scheme is that drive plate is connected with IGBT, tests the quality of drive plate in system, and the shortcoming that this method is brought is: method of testing is comparatively complicated, and Measuring Time is long, is unfavorable for batch detection IGBT drive plate.
Summary of the invention
In order to solve the problems of the technologies described above, the utility model provide a kind of simple in structure, Measuring Time is short, measure the testing circuit of the high IGBT drive plate of efficiency.
The technical scheme that the utility model addresses the above problem is: a kind of testing circuit of IGBT drive plate, comprise analog pulse output unit, input block is opened in simulation, feed back input unit, Logical processing unit, fault locking unit and failure reset unit, described analog pulse output unit respectively with the input end of IGBT drive plate, the input end of Logical processing unit is connected, the analog pulse signal of output is sent into IGBT drive plate and Logical processing unit, the input end that input block is opened in simulation is connected with the output terminal of IGBT drive plate, the output terminal of input block is opened in simulation and the input end of Logical processing unit is connected, the input end of feed back input unit is connected with the output terminal of IGBT drive plate, the output terminal of feed back input unit is connected with the input end of Logical processing unit, the output terminal of Logical processing unit is connected with fault locking unit, failure reset unit is connected with fault locking unit.
The testing circuit of above-mentioned IGBT drive plate also comprises Power supply unit, and described Power supply unit is opened input block, feed back input unit, Logical processing unit, fault locking unit with analog pulse output unit, simulation respectively and is connected.
In the testing circuit of above-mentioned IGBT drive plate, described analog pulse output unit comprises adjustable resistance, digital signal processor, toggle switch, light-coupled isolation unit, described adjustable resistance is connected with digital signal processor, digital signal processor, toggle switch, light-coupled isolation unit are connected in series successively, and the output terminal of light-coupled isolation unit is connected with Logical processing unit.
In the testing circuit of above-mentioned IGBT drive plate, described simulation is opened input block and is comprised the first electric capacity, the second resistance, the 3rd resistance, the 4th resistance, the 5th resistance, the 6th resistance, the 9th resistance, differential amplifier and optocoupler, described the first electric capacity is attempted by between the gate leve and emitter of IGBT drive plate, one end of the second resistance is connected with the emitter of IGBT drive plate, the other end is connected with the inverting input of differential amplifier, one end of the 3rd resistance is connected with the gate leve of IGBT drive plate, the other end is connected with the in-phase input end of differential amplifier, the 4th one end of resistance and the in-phase input end of differential amplifier are connected, the other end is connected with the inverting input of differential amplifier, ground connection after the in-phase input end of differential amplifier is connected with the 6th resistance, the 5th one end of resistance and the inverting input of differential amplifier are connected, the other end is connected with the output terminal of differential amplifier, the output terminal of differential amplifier is connected with the input end of optocoupler, the output terminal of optocoupler is connected with Logical processing unit after the 9th resistance.
In the testing circuit of above-mentioned IGBT drive plate, described Logical processing unit comprises two two input NOR gate circuits, two not circuits and an AND circuit, wherein two of the first NOR gate circuit input ends are opened respectively the output terminal of input block with simulation, the output terminal of analog pulse output unit is connected, the output terminal of the first NOR gate circuit is connected with an input end of described AND circuit after the first not circuit, two input ends of the second NOR gate circuit respectively with the output terminal of analog pulse output unit, the output terminal of feed back input unit is connected, the output terminal of the second NOR gate circuit is connected with another input end of described AND circuit after the second not circuit, the output terminal of described AND circuit is connected with the input end of fault locking unit.
The beneficial effects of the utility model are: analog pulse output unit of the present utility model sends analog pulse signal to IGBT drive plate to be measured, signal is by after IGBT drive plate circuit, the simulation make-and-break signal of output feedback signal and IGBT drive plate, feedback signal and simulation make-and-break signal are sent into fault locking unit after Logical processing unit, detected the performance quality of drive plate by fault locking unit judges, the utility model is simple in structure, cost is low, greatly reduce the test duration of measuring an IGBT drive plate, maintenance and operation to application IGBT drive plate occasion has brought very large optimization, possesses the value of extensive popularization.
Brief description of the drawings
Fig. 1 is structured flowchart of the present utility model.
Fig. 2 is analog pulse output unit circuit diagram of the present utility model.
Fig. 3 is that input-cell circuitry figure is opened in simulation of the present utility model.
Fig. 4 is Logical processing unit circuit diagram of the present utility model.
Fig. 5 is fault locking element circuit figure of the present utility model.
Embodiment
Below in conjunction with drawings and Examples, the utility model is further described.
As shown in Figure 1, the utility model comprises analog pulse output unit, input block is opened in simulation, feed back input unit, Logical processing unit, fault locking unit and failure reset unit, described analog pulse output unit respectively with the input end of IGBT drive plate, the input end of Logical processing unit is connected, the analog pulse signal of output is sent into IGBT drive plate and Logical processing unit, the input end that input block is opened in simulation is connected with the output terminal of IGBT drive plate, the output terminal of input block is opened in simulation and the input end of Logical processing unit is connected, the input end of feed back input unit is connected with the output terminal of IGBT drive plate, the output terminal of feed back input unit is connected with the input end of Logical processing unit, the output terminal of Logical processing unit is connected with fault locking unit, failure reset unit is connected with fault locking unit.
As shown in Figure 2, analog pulse output unit comprises adjustable resistance R1, digital signal processor DSP 28027, toggle switch, light-coupled isolation unit, described adjustable resistance is connected with digital signal processor, digital signal processor, toggle switch, light-coupled isolation unit are connected in series successively, and the output terminal of light-coupled isolation unit is connected with Logical processing unit.Digital signal processor DSP 28027 is exported analog pulse signal PWM1, the PWM2 of different frequency by detecting the voltage of adjustable resistance R1, it is connected to wherein one grade of toggle switch, other two grades of connect respectively+5V VDD-to-VSSs, according to test needs, toggle switch connects different gears, and the analog pulse signal of output is connected with the driving signal input of IGBT drive plate to be measured through light-coupled isolation unit.Can be input to the signal delay of holding to output G, E after IGBT drive plate with oscilloscope measurement analog pulse, the signal delay time of measuring drive plate to be measured, IGBT drive plate self has or not Dead Time and Dead Time size.
As shown in Figure 3, simulation is opened input block and is comprised capacitor C 1, resistance R 2, resistance R 3, resistance R 4, resistance R 5, resistance R 6, resistance R 9, differential amplifier U1 and optocoupler, described capacitor C 1 is attempted by between the gate leve G and emitter E of IGBT drive plate, one end of resistance R 2 is connected with the emitter E of IGBT drive plate, the other end is connected with the inverting input of differential amplifier U1, one end of resistance R 3 is connected with the gate leve G of IGBT drive plate, the other end is connected with the in-phase input end of differential amplifier U1, one end of resistance R 4 is connected with the in-phase input end of differential amplifier U1, the other end is connected with the inverting input of differential amplifier U1, ground connection after the in-phase input end of differential amplifier U1 is connected with resistance R 6, one end of resistance R 5 is connected with the inverting input of differential amplifier U1, the other end is connected with the output terminal of differential amplifier U1, the output terminal of differential amplifier U1 is connected with the input end of optocoupler, the output terminal of optocoupler is connected with Logical processing unit after resistance R 9.G, the E end of IGBT drive plate output is connected respectively to the positive and negative input end of differential amplifier U1 by resistance, carry out the input capacitance between the GE of Reality simulation IGBT by capacitor C 1, the voltage can measure IGBT drive plate and turn on and off with multimeter time; Judge that by the voltage difference detecting between IGBT drive plate output GE analog pulse is through the result after the each functional module of IGBT drive plate.
As shown in Figure 4, Logical processing unit comprises two two input NOR gate circuit XOR1 and XOR2, two not circuit NOT1 and NOT2 and an AND circuit AND, wherein two of NOR gate circuit XOR1 input end A1, B1 opens respectively the output terminal of input block with simulation, the output terminal of analog pulse output unit is connected, the output terminal of NOR gate circuit XOR1 is connected with the input end A3 of described AND circuit AND after not circuit NOT1, two input end A2 of NOR gate circuit XOR2, B2 respectively with the output terminal of analog pulse output unit, the output terminal of feed back input unit is connected, the output terminal of NOR gate circuit XOR2 is connected with the input end B3 of described AND circuit AND after not circuit NOT2, the output terminal of described AND circuit AND is connected with the input end of fault locking unit, in Logical processing unit, when the level of opening input when analog pulse signal level and feedback signal level or drive plate simulation is all corresponding, AND circuit AND exports high level, the level of opening input when analog pulse signal level and feedback signal level or drive plate simulation is not corresponding, AND circuit AND output low level.
As shown in Figure 5, fault locking unit comprises d type flip flop, logic NOT device, Darlington driving tube, magnetic latching relay KM, LED and resistance capacitance composition.In Logical processing unit, the level of opening input when analog pulse signal level and feedback signal level or drive plate simulation is not corresponding, to output to 4 pin of d type flip flop be low level to Logical processing unit, the output low level of 6 pin of d type flip flop, be low level through 1 pin that is input to magnetic latching relay KM after Darlington driving tube, relay coil adhesive, contact 3 is connected with 6, light emitting diode Led1 lights, contact 10 is connected with 7 simultaneously, 1 pin of d type flip flop is low level, no matter above how signal changes, now because coil energy does not discharge between 1 pin of magnetic latching relay KM and 12 pin, keep connecting always, light emitting diode Led1 lights always, prove drive plate existing problems to be measured, if reset switch SW1 closes, between 1 pin of magnetic latching relay KM and 12 pin, coil energy discharges, and light emitting diode Led1 goes out, and can re-start the test of drive plate.If drive plate is existing problems still, light emitting diode Led1 is lit again.
Principle of work of the present utility model is as follows: analog pulse output unit sends analog pulse signal to IGBT drive plate to be measured and Logical processing unit, IGBT drive plate receives after analog pulse signal, the simulation make-and-break signal of output feedback signal and IGBT drive plate, feedback signal is sent into Logical processing unit through feed back input unit, simulation make-and-break signal is opened input block through simulation and is sent into Logical processing unit, in Logical processing unit, in the time that analog pulse signal level and feedback signal level or drive plate simulation make-and-break signal level are all corresponding, Logical processing unit output high level is to fault locking unit, the light emitting diode Led1 of fault locking unit does not work, when analog pulse signal level and feedback signal level or drive plate, to intend make-and-break signal level not corresponding, and Logical processing unit output low level is to fault locking unit, and the light emitting diode Led1 of fault locking unit is bright, proves drive plate existing problems to be measured, if reset switch SW1 closes, light emitting diode Led1 goes out, and can re-start the test of drive plate.If drive plate is existing problems still, light emitting diode Led1 is lit again.The utility model is simple in structure, cost is low, greatly reduces the test duration of measuring an IGBT drive plate, and the maintenance and operation of application IGBT drive plate occasion has been brought to very large optimization, possesses the value of extensive popularization.
Claims (5)
1. the testing circuit of an IGBT drive plate, it is characterized in that: comprise analog pulse output unit, input block is opened in simulation, feed back input unit, Logical processing unit, fault locking unit and failure reset unit, described analog pulse output unit respectively with the input end of IGBT drive plate, the input end of Logical processing unit is connected, the analog pulse signal of output is sent into IGBT drive plate and Logical processing unit, the input end that input block is opened in simulation is connected with the output terminal of IGBT drive plate, the output terminal of input block is opened in simulation and the input end of Logical processing unit is connected, the input end of feed back input unit is connected with the output terminal of IGBT drive plate, the output terminal of feed back input unit is connected with the input end of Logical processing unit, the output terminal of Logical processing unit is connected with fault locking unit, failure reset unit is connected with fault locking unit.
2. the testing circuit of IGBT drive plate as claimed in claim 1, it is characterized in that: also comprise Power supply unit, described Power supply unit is opened input block, feed back input unit, Logical processing unit, fault locking unit with analog pulse output unit, simulation respectively and is connected.
3. the testing circuit of IGBT drive plate as claimed in claim 2, it is characterized in that: described analog pulse output unit comprises adjustable resistance, digital signal processor, toggle switch, light-coupled isolation unit, described adjustable resistance is connected with digital signal processor, digital signal processor, toggle switch, light-coupled isolation unit are connected in series successively, and the output terminal of light-coupled isolation unit is connected with Logical processing unit.
4. the testing circuit of IGBT drive plate as claimed in claim 2, it is characterized in that: described simulation is opened input block and comprised the first electric capacity, the second resistance, the 3rd resistance, the 4th resistance, the 5th resistance, the 6th resistance, the 9th resistance, differential amplifier and optocoupler, described the first electric capacity is attempted by between the gate leve and emitter of IGBT drive plate, one end of the second resistance is connected with the emitter of IGBT drive plate, the other end is connected with the inverting input of differential amplifier, one end of the 3rd resistance is connected with the gate leve of IGBT drive plate, the other end is connected with the in-phase input end of differential amplifier, the 4th one end of resistance and the in-phase input end of differential amplifier are connected, the other end is connected with the inverting input of differential amplifier, ground connection after the in-phase input end of differential amplifier is connected with the 6th resistance, the 5th one end of resistance and the inverting input of differential amplifier are connected, the other end is connected with the output terminal of differential amplifier, the output terminal of differential amplifier is connected with the input end of optocoupler, the output terminal of optocoupler is connected with Logical processing unit after the 9th resistance.
5. the testing circuit of IGBT drive plate as claimed in claim 4, it is characterized in that: described Logical processing unit comprises two two input NOR gate circuits, two not circuits and an AND circuit, wherein two of the first NOR gate circuit input ends are opened respectively the output terminal of input block with simulation, the output terminal of analog pulse output unit is connected, the output terminal of the first NOR gate circuit is connected with an input end of described AND circuit after the first not circuit, two input ends of the second NOR gate circuit respectively with the output terminal of analog pulse output unit, the output terminal of feed back input unit is connected, the output terminal of the second NOR gate circuit is connected with another input end of described AND circuit after the second not circuit, the output terminal of described AND circuit is connected with the input end of fault locking unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420173564.0U CN203759203U (en) | 2014-04-11 | 2014-04-11 | Detection circuit of IGBT (insulated gate bipolar transistor) driving board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420173564.0U CN203759203U (en) | 2014-04-11 | 2014-04-11 | Detection circuit of IGBT (insulated gate bipolar transistor) driving board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203759203U true CN203759203U (en) | 2014-08-06 |
Family
ID=51254459
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420173564.0U Expired - Lifetime CN203759203U (en) | 2014-04-11 | 2014-04-11 | Detection circuit of IGBT (insulated gate bipolar transistor) driving board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203759203U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112485628A (en) * | 2020-11-17 | 2021-03-12 | 珠海格力电器股份有限公司 | Self-checking system of frequency converter |
-
2014
- 2014-04-11 CN CN201420173564.0U patent/CN203759203U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112485628A (en) * | 2020-11-17 | 2021-03-12 | 珠海格力电器股份有限公司 | Self-checking system of frequency converter |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102012481B (en) | Thyristor level test method for novel converter valve module | |
| CN103336235A (en) | IGBT condition detection circuit | |
| CN205232007U (en) | On -vehicle switching power supply operating condition indicating circuit | |
| CN202305717U (en) | AC power failure quick detection circuit | |
| CN102280870B (en) | Switching circuit board and protection method thereof | |
| CN207691759U (en) | A kind of tension measuring circuit | |
| CN102411082A (en) | Energy-saving zero crossing detection circuit and apparatus thereof | |
| CN203759203U (en) | Detection circuit of IGBT (insulated gate bipolar transistor) driving board | |
| CN202533526U (en) | General test circuit of switch sensor or solenoid valve | |
| CN105424997A (en) | Relay with state detection circuit and anti-electricity-theft method | |
| CN203069701U (en) | Electronic ballast reliability test device used for intelligent gas discharge lamp | |
| CN201886120U (en) | Dynamic tester with function of isolating test signals and power supplies | |
| CN203981802U (en) | Switch power source adapter automatic testing equipment | |
| CN203337775U (en) | An IGBT status detecting circuit | |
| CN202856691U (en) | Control protection circuit of solid state microwave power amplifier | |
| CN102857177B (en) | Control and protection circuit for solid-state microwave power amplifier | |
| CN202009237U (en) | Fling-cut switch auxiliary circuit device of reactive compensation device | |
| CN205103337U (en) | Opto -coupler test circuit board | |
| CN203455432U (en) | Universal optoelectronic coupler detection circuit | |
| CN201479113U (en) | Trigger interface circuit irrespective of polarity | |
| CN108761162A (en) | A kind of oscilloprobe control system and method | |
| CN104090199B (en) | Device for simulating poor power contact phenomenon in use process of electric appliance | |
| CN101162249B (en) | Digital quantity input module having multi state checking function | |
| CN204068684U (en) | For the current foldback circuit of power device | |
| CN202433488U (en) | Controlled silicon fault detection circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140806 |