CN203733787U - Chip interconnection structure - Google Patents
Chip interconnection structure Download PDFInfo
- Publication number
- CN203733787U CN203733787U CN201320882823.2U CN201320882823U CN203733787U CN 203733787 U CN203733787 U CN 203733787U CN 201320882823 U CN201320882823 U CN 201320882823U CN 203733787 U CN203733787 U CN 203733787U
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- Prior art keywords
- chip
- chips
- optical
- grating
- interconnect structure
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- 230000003287 optical effect Effects 0.000 claims abstract description 40
- 239000002184 metal Substances 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052802 copper Inorganic materials 0.000 claims abstract description 12
- 239000010949 copper Substances 0.000 claims abstract description 12
- 238000010276 construction Methods 0.000 claims description 10
- 230000005540 biological transmission Effects 0.000 abstract description 9
- 238000005516 engineering process Methods 0.000 abstract description 9
- 238000011031 large-scale manufacturing process Methods 0.000 abstract description 2
- 230000006835 compression Effects 0.000 abstract 1
- 238000007906 compression Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 16
- 229910052738 indium Inorganic materials 0.000 description 10
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 9
- 239000008188 pellet Substances 0.000 description 4
- 230000006854 communication Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Abstract
The utility model provides a chip interconnection structure. Interconnection of two chips or a plurality of chips are realized by a thermal compression bonding technology and making full use of metallic characters of copper. The metal structure arrangement makes the two chips realize optical connection, and also electrical connection is realized. Bonding among the chips is relatively firm, and strength is high. The whole interconnection technology is relatively simple, and is suitable for large scale production application. Except a protection structure covering on rasters and a waveguide, the chips have no gap. Thus, free optical transmission space between the rasters is just 2 micrometers to 4 micrometers, and optical loss caused by photodiffusion is reduced in a certain extent. The two rasters are preferably in a focusing raster structure, so that not only the optical loss in the optical transmission process is relatively reduced, but also better longitudinal and lateral error tolerance can be obtained.
Description
Technical field
The utility model relates to optical communication technique field, specifically relates to a kind of chip interconnect structure.
Background technology
Along with scientific and technological progress, more and more chips with difference in functionality pour in people's life, mutual contact mode between chip and chip is also more and more various, and wherein turning-over of chip light UNICOM technology can be described as and between chip and chip, carrying out a most common technology in the middle of interconnected all technological means.
As shown in Figure 1, after two chips (1,2) UNICOM, the UNICOM that can realize light between the grating 4 in two chips.In prior art, conventionally adopt the mode of indium projection reflow soldering to realize two UNICOMs between chip.As patent documentation application publication number to be CN102064120A a kind of based on indium salient point without scaling powder reflux technique method, it discloses, and metal layer under substrate metal, passivation layer opening, salient point thickens, indium plating salient point, electroplate the interconnected processing steps such as the coated indium salient point of silver layer, salient point backflow.The chip interconnect structure of producing according to this kind of interconnected technique has a kind of ability of good self-aligned, and often also can obtain good alignment error, and obtains preferably efficiency of transmission, is relatively applicable to rapid large-scale and produces.
Because the fusing point of indium projection itself is low, in interconnected heating process, can produce projection, form higher height (generally between 30 microns to 50 microns), as shown in Figure 2 just for the indium projection process of one of them chip adds the thermogenetic indium pellet 3 with certain altitude.During like this by two chip interconnect, between two chips, can not accomplish tight combination, as shown in Figure 1, can be because protruding existence causes the indium pellet 3 that exists some to have certain altitude between two chips.Compare knownly according to Fig. 1 and Fig. 2, will cause like this two distances between grating to increase, while realizing light UNICOM, light path strengthens, and has strengthened optical loss.The interconnected technique of carrying out by this way can have the optical loss of 6-7dB in actual transmissions.
Utility model content
For this reason, technical problem to be solved in the utility model is that chip interconnect structure of the prior art can produce larger optical loss in transmitting procedure, thereby proposes a kind of a kind of chip interconnect structure that can reduce the optical loss in transmitting procedure.
For solving the problems of the technologies described above, the utility model provides following technical scheme:
A kind of chip interconnect structure, comprising:
The first chip and the second chip, and by the metal structure of described the first chip and described the second chip UNICOM;
Wherein said the first chip and described the second chip include optical chip portion and electronics connecting portion, and described optical chip portion comprises grating and waveguide, and light signal transmits between two gratings; Described electronics connecting portion comprises the electronic device connecting by described metal structure.
Described metal structure is metallic copper further.
Two gratings are one-dimensional grating structure further.
Two gratings are focusing type optical grating construction further.
Described the first chip and described the second chip all also comprise the protection structure covering in grating and waveguide further.
Distance between two gratings is 2-4um further.
Distance between described metal structure and waveguide is greater than 3-4um further.
Technique scheme of the present utility model has the following advantages compared to existing technology:
(1) a kind of chip interconnect structure described in the utility model, combine thermocompression bonding technology, and the metallic character that takes full advantage of copper realizes interconnected to two chips or multiple chips, two chips that are arranged so that of metal structure not only can be realized optics and connect, and can also realize electricity and connect.Bonding between chip is more firm, and intensity is high; And whole interconnected technique is relatively simple, processes without edge, be relatively applicable to large-scale production application.
(2) a kind of chip interconnect structure described in the utility model, the protection structure on covering grating and waveguide, can not have interval between chip and chip.Light transmission range between grating and grating only has 2 microns to 4 microns like this, and the optical loss causing due to diffusion optical guide has just obtained reducing to a certain degree.
(3) a kind of chip interconnect structure described in the utility model, two described gratings are preferably focusing type optical grating construction, not only can reduce preferably the optical loss in optical transmission process, also can obtain good vertical and horizontal fault tolerance simultaneously.
Brief description of the drawings
For content of the present utility model is more likely to be clearly understood, according to specific embodiment of the utility model also by reference to the accompanying drawings, the utility model is described in further detail, wherein below
Fig. 1 is chip interconnect structural representation of the prior art;
Fig. 2 is the indium pellet enlarged diagram in chip interconnect structure of the prior art;
Fig. 3 is the chip interconnect structural representation described in a kind of embodiment;
Fig. 4 is the lightray propagation schematic diagram in one-dimensional grating structure;
Fig. 5 is the lightray propagation schematic diagram in focusing type optical grating construction.
In figure, Reference numeral is expressed as: 1-the first chip, 2-the second chip, 3-indium pellet, 4-grating, 5-waveguide, 6-electronic device.
Embodiment
embodiment 1
A kind of chip interconnect structure described in the present embodiment, as shown in Figure 3, comprising:
The first chip 1 and the second chip 2, and by the metal structure of described the first chip 1 and described the second chip 2 UNICOMs.
Wherein said the first chip 1 and described the second chip 2 include optical chip portion and electronics connecting portion, and described optical chip portion comprises grating 4 and waveguide 5, and light signal transmits between two gratings 4; Described electronics connecting portion comprises the electronic device 6 connecting by described metal structure.
Described metal structure is preferably metallic copper.Those skilled in the art should know, the selection of described metal structure material includes but not limited to metallic copper, and other metal can also be selected, and connects medium because metallic copper is at present main electricity, and use metallic copper as bonding medium, can simplify procedure of processing.Two chips that are arranged so that by metal structure not only can be realized optics and connect, and can also realize electricity and connect.So locate preferably to use metallic copper, but other apparent metals are replaced also within the protection range of the present embodiment.
A kind of chip interconnect structure described in the present embodiment, lays layer of metal copper by the upper surface of chip described in each, then completes the interconnected of two chips by thermocompression bonding technology.The laying of described metallic copper need to ensure upper surface smooth of whole chip, and design parameter needs set in conjunction with the actual size of concrete chip, but the final purpose of realization is to ensure that the slitless connection of two chips is interconnected.And the present embodiment not only can complete the interconnected of two chips, also can complete the interconnected of multiple chips, as long as the crystalline substrates of described the first chip 1 itself is enough wide, the metallic copper of laying on described the first chip 1 enough wide just can be on described the first chip 1 interconnected multiple chips.Those skilled in the art should know, and the quantity of described chip interconnect, not for limiting the present embodiment, is carried out the interconnected also within the protection range of the present embodiment of multiple chips according to actual needs.
Two gratings are one-dimensional grating structure.Now light signal generally will broaden optical mode gradually by a kind of very long tapered waveguide in tiny waveguiding structure one end in transmitting procedure, then by grating, optical mode near normal is spread out, and its lightray propagation process as shown in Figure 4.Wherein said optical mode is the various parameters of light signal corresponding light signal meet respective phase condition in transmitting procedure time.This tapered waveguide is often very long, for example in silicon photosystem, often need more than 300 microns, and in the integrated optics system of other low index contrast degree, this tapered waveguide part needs longer, those skilled in the art should know, and are not repeating herein.In silicon optical communication, by adopting the chip interconnect structure of one-dimensional grating structure, 3dB error range, in positive and negative 8 microns of left and right, has good longitudinal error tolerance.
Described the first chip and described the second chip all also comprise the silicon dioxide protection structure covering in grating and waveguide.Preferably the distance between two gratings is 2-4um.In order to ensure less being interfered in optical signal transmission process, preferably the distance between described metal structure and waveguide is 3-4um simultaneously.Those skilled in the art should know, and because the thickness difference of the protection structure of chip surface can cause the variation of above data, any apparent data variation is all within the protection range of the present embodiment.
A kind of chip interconnect structure described in the present embodiment, the protection structure on covering grating and waveguide, can not have interval between chip and chip.Light transmission range between grating and grating only has 2 microns to 4 microns like this, and the optical loss causing due to diffusion optical guide has just obtained reducing to a certain degree.
embodiment 2
The present embodiment is the improvement of carrying out on the basis of embodiment 1, and the difference of itself and embodiment 1 is that two gratings are focusing type optical grating construction by the one-dimensional grating structure of focusing type optical grating construction alternative embodiment 1, and the communication process of its light signal as shown in Figure 5.
No matter grating in described chip interconnect structure is one-dimensional grating structure or focusing type optical grating construction, all very outstanding in the performance of longitudinal error, and 3dB error range is in positive and negative 8 microns of left and right.If but one-dimensional grating structure width is not high, its lateral error tolerance is often very low.If but one-dimensional grating structure width is higher, lateral error tolerance can corresponding improve, but the tapered waveguide that this structure need to be very long is to realize the transmission of low-loss rate, like this can increase greatly again the area occupied of optics.
And focusing type optical grating construction is more brief than one-dimensional grating structure, even longer its length of focusing type optical grating construction also all in 30 microns, does not also just need tapered waveguide that optical mode is increased.Also therefore focusing type optical grating construction can have good performance in lateral error tolerance, and 3dB error range is in positive and negative 5-10 micron left and right.The chip interconnect structure of i.e. focusing type not only can reduce the optical loss in optical transmission process preferably, also can obtain good vertical and horizontal fault tolerance simultaneously.The design size of focusing type grating is also greatly to reduce for one-dimensional grating, is conducive to the size saving of chip design.
Obviously, above-described embodiment is only for example is clearly described, and the not restriction to execution mode.For those of ordinary skill in the field, can also make other changes in different forms on the basis of the above description.Here without also giving exhaustive to all execution modes.And among the protection range that the apparent variation of being extended out thus or variation are still created in the utility model.
Claims (7)
1. a chip interconnect structure, is characterized in that, comprising:
The first chip and the second chip, and by the metal structure of described the first chip and described the second chip UNICOM;
Wherein said the first chip and described the second chip include optical chip portion and electronics connecting portion, and described optical chip portion comprises grating and waveguide, and light signal transmits between two gratings; Described electronics connecting portion comprises the electronic device connecting by described metal structure.
2. chip interconnect structure according to claim 1, is characterized in that:
Described metal structure is metallic copper.
3. chip interconnect structure according to claim 2, is characterized in that:
Two gratings are one-dimensional grating structure.
4. chip interconnect structure according to claim 2, is characterized in that:
Two gratings are focusing type optical grating construction.
5. according to the chip interconnect structure described in claim 3 or 4, it is characterized in that:
Described the first chip and described the second chip all also comprise the protection structure covering in grating and waveguide.
6. chip interconnect structure according to claim 5, is characterized in that:
Distance between two gratings is 2-4um.
7. chip interconnect structure according to claim 6: it is characterized in that:
Distance between described metal structure and waveguide is greater than 3-4um.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320882823.2U CN203733787U (en) | 2013-12-30 | 2013-12-30 | Chip interconnection structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320882823.2U CN203733787U (en) | 2013-12-30 | 2013-12-30 | Chip interconnection structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203733787U true CN203733787U (en) | 2014-07-23 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320882823.2U Expired - Lifetime CN203733787U (en) | 2013-12-30 | 2013-12-30 | Chip interconnection structure |
Country Status (1)
| Country | Link |
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| CN (1) | CN203733787U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465613A (en) * | 2013-12-30 | 2015-03-25 | 苏州矩阵光电有限公司 | Chip interconnection structure and interconnection process thereof |
| CN107422420A (en) * | 2017-08-29 | 2017-12-01 | 中国科学院宁波材料技术与工程研究所 | A kind of three-dimensional photon device interconnection method based on melting direct write |
-
2013
- 2013-12-30 CN CN201320882823.2U patent/CN203733787U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465613A (en) * | 2013-12-30 | 2015-03-25 | 苏州矩阵光电有限公司 | Chip interconnection structure and interconnection process thereof |
| CN107422420A (en) * | 2017-08-29 | 2017-12-01 | 中国科学院宁波材料技术与工程研究所 | A kind of three-dimensional photon device interconnection method based on melting direct write |
| CN107422420B (en) * | 2017-08-29 | 2019-10-18 | 中国科学院宁波材料技术与工程研究所 | A kind of three-dimensional photon device interconnection method based on melting direct write |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140723 |
|
| CX01 | Expiry of patent term |