CN203733772U - Semiconductor groove structure - Google Patents
Semiconductor groove structure Download PDFInfo
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- CN203733772U CN203733772U CN201420106256.6U CN201420106256U CN203733772U CN 203733772 U CN203733772 U CN 203733772U CN 201420106256 U CN201420106256 U CN 201420106256U CN 203733772 U CN203733772 U CN 203733772U
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Abstract
The utility model provides a semiconductor groove structure comprising a semiconductor substrate. A groove is formed in the semiconductor substrate. The turning parts of the groove present to be arc-shaped. An oxide layer is formed on the surface of the groove and the semiconductor substrate. Therefore, the groove with great and smooth morphology is obtained, and thus the oxide layer with uniform thickness can be obtained in the groove, characteristics of a semiconductor device are improved and stability and reliability of the semiconductor device are guaranteed.
Description
Technical field
The utility model relates to ic manufacturing technology field, particularly a kind of semiconductor trench structure.
Background technology
Power device can be divided into power integrated circuit (IC) device and power discrete device two classes, and wherein, power discrete device comprises again the devices such as power MOSFET, high power transistor and IGBT.Early stage power device is all to produce based on planar technique, but along with the development of semiconductor technology, small size, the trend that high-power, high-performance has become semiconductor device development.But the planar technique MOSFET device of take is example, restriction due to JFET dead resistance in itself body, the area of single cellular reduces limited, so just makes to increase primitive unit cell density and becomes very difficult, can not make the conducting resistance RDSON of planar technique MOSFET further reduce.Trench process is due to groove is become vertically from level, eliminated the impact of the parasitic JFET resistance of planar structure, cellular size is dwindled greatly, increase on this basis cellular density, improve the overall width of raceway groove in unit are chip, thereby just can electric current increase, conducting resistance decline and relevant parameter are optimized so that the channel width-over-length ratio of device on unit silicon chip increases, the tube core of having realized smaller szie has more high-power and high performance target.
Trench process is usually used in making grid, isolation technology etc., even for P, the N-type of super knot technique, adulterates.In above-mentioned concrete application, trench process includes following process conventionally, and in conjunction with Fig. 1～Fig. 5, traditional trench process comprises:
As shown in Figure 1, provide substrate 10, and on described substrate 10 dielectric layer deposited 11; Common, described substrate 10 is N-type <100> crystal orientation substrate.
As shown in Figure 2, remove the described dielectric layer 11 of part, form first window 12.
Then, as shown in Figure 3, substrate 10 described in etching, removes dielectric layer 11, forms Second Window 13.In this process, will form a plurality of angles, concrete, between Second Window 13 sidewalls and substrate top surface, form angle theta 1; Between Second Window 13 sidewalls and Second Window 13 diapires, form angle theta 2; Between Second Window 13 diapires, form angle theta 3.Common, it is 90 °～100 ° that the angle of angle theta 1 requires; The angle of angle theta 2 and angle theta 3 all requires as obtuse angle, is greater than 90 °.
Then, as shown in Figure 4, at described Second Window 13 and substrate 10 surfaces, carry out repair layer growth; Then remove the repair layer of growth, form groove 14.This layer of repair layer forms by silicon substrate is carried out to oxidation technology, its objective is the damage to flute profile looks when repairing etching forms Second Window 13, and conventional temperature is 950 ℃～1000 ℃.Because substrate 10 is <100> crystal orientation, and Second Window 13 sidewalls are <011> crystal orientation, according to characteristic of semiconductor, the speed ratio <100> crystal orientation of <011> crystal orientation growth oxide layer wants fast.So under identical growing environment, the growth of the repair layer of Second Window 13 sidewalls is thicker, thereby cause Second Window 13 sidewalls to consume the thickness of silicon more than the thickness of substrate 10 upper surfaces.Thus, form after groove 14, will the angle of groove 14 sidewalls and substrate top surface be diminished, form acute angle angle theta 4, there is obvious projection in groove 14 tops.
Then, as shown in Figure 5, at described groove 14 and substrate 10 surfaces, carry out oxide layer 15 growths.According to semiconductor film, at smooth place, be easy to growth, in sharp-pointed/prominence, be not easy to the characteristic of growth, thereby be less than the d1 of plane place, d3, d5 oxide layer 15 thickness at oxide layer 15 thickness of corner location d2, d4, d6.That is to say, formed oxide layer 15 unevenness very, formed oxide layer 15 is of low quality.
Known, the quality of oxide layer will have influence on the quality of follow-up formed grid, isolation structure or PN junction.For example, in the making of grid, the quality of oxide layer (being commonly referred to grid oxide layer in grid) has determined the cut-in voltage of MOSFET device, a series of basic parameters such as grid source is withstand voltage, the thickness evenness of grid oxide layer is to weigh the withstand voltage key factor of grid oxygen, if grid oxide layer is in uneven thickness, when grid applies voltage, energy is understood elder generation region of thin thickness from grid oxide layer and is punctured, thereby make component failure, and have security risk.
Therefore, how to optimize groove pattern, to obtain the better oxide layer of quality, become those skilled in the art's technical barrier urgently to be resolved hurrily.
Utility model content
The purpose of this utility model is to provide a kind of semiconductor trench structure, and to solve, existing groove pattern is poor, top has obvious projection, thereby causes the uneven problem of formed oxide layer.
For solving the problems of the technologies described above, the utility model provides a kind of semiconductor trench structure, and described semiconductor trench structure comprises: Semiconductor substrate; In described Semiconductor substrate, be formed with groove, the turning point of described groove is circular arc; Described groove and semiconductor substrate surface are formed with oxide layer.
Optionally, in described semiconductor trench structure, described Semiconductor substrate is the Semiconductor substrate in N-type <100> crystal orientation.
Optionally, in described semiconductor trench structure, the degree of depth of described groove is 0.1 micron～50 microns.
In the semiconductor trench structure providing at the utility model, the turning point of described groove is circular arc, obtained good, the round and smooth groove of pattern, thereby can in this groove, obtain the oxide layer of even thickness, improve the characteristic of semiconductor device, guaranteed stability and the reliability of semiconductor device.
Accompanying drawing explanation
Fig. 1～Fig. 5 is the generalized section of traditional formation semiconductor trench structure;
Fig. 6 is the schematic flow sheet of formation method of the semiconductor trench structure of the utility model embodiment;
Fig. 7～Figure 13 is the generalized section of the formation semiconductor trench structure of the utility model embodiment;
Figure 14 is the partial enlarged drawing of generalized section shown in Figure 11;
Figure 15 is the partial enlarged drawing of generalized section shown in Figure 13.
Embodiment
Below in conjunction with the drawings and specific embodiments, the formation method of the semiconductor trench structure the utility model proposes is described in further detail.According to the following describes and claims, advantage of the present utility model and feature will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of aid illustration the utility model embodiment lucidly.
Please refer to Fig. 6, it is the schematic flow sheet of formation method of the semiconductor trench structure of the utility model embodiment.As shown in Figure 6, the formation method of described semiconductor trench structure comprises:
Step S20: Semiconductor substrate is provided, and forms in turn first medium layer and second medium layer in described Semiconductor substrate;
Step S21: remove part second medium layer, form first window;
Step S22: carry out oxidation technology, form beak structure in described first window;
Step S23: the beak structure described in etching in first window and the Semiconductor substrate of below thereof, form Second Window;
Step S24: remove described second medium layer and first medium layer, form the 3rd window;
Step S25: carry out repair layer growth at described the 3rd window and semiconductor substrate surface, then remove the repair layer of growth, form groove;
Step S26: form oxide layer at described groove and semiconductor substrate surface.
In the embodiment of the present application, between the sidewall of described the 3rd window and Semiconductor substrate upper surface, between the sidewall and sidewall of described the 3rd window, all have angle between the sidewall of described the 3rd window and diapire and between the diapire of described the 3rd window and diapire, and angle is obtuse angle.The turning point of described groove is circular arc.
Concrete, please refer to Fig. 7～Figure 15, wherein, Fig. 7～Figure 13 is the generalized section of the formation semiconductor trench structure of the utility model embodiment; Figure 14 is the partial enlarged drawing of generalized section shown in Figure 11; Figure 15 is the partial enlarged drawing of generalized section shown in Figure 13.
As shown in Figure 7, provide Semiconductor substrate 30, and form in turn first medium layer 31 and second medium layer 32 in described Semiconductor substrate 30.
In the embodiment of the present application, described Semiconductor substrate 30 can be silicon substrate, germanium silicon substrate, III-group Ⅴ element compound substrate or well known to a person skilled in the art other semiconductive material substrate.What in the present embodiment, adopt is silicon substrate.More specifically, the silicon substrate adopting in the present embodiment is the silicon substrate that forms the N-type <100> crystal orientation that power device is conventional.
In the embodiment of the present application, the material of described first medium layer 31 is silicon dioxide.Further, the thickness of described first medium layer 31 is 10 dust～1000 dusts, and for example, the thickness of described first medium layer 31 is 10 dusts, 50 dusts, 100 dusts, 150 dusts, 200 dusts, 300 dusts, 500 dusts, 650 dusts, 800 dusts or 1000 dusts.
In the embodiment of the present application, the material of described second medium layer 32 is one or more in silicon nitride, silicon oxynitride and polysilicon.Concrete, when the requirement of follow-up formed groove live width is greater than 0.5 micron, the material of second medium layer is preferably silicon nitride, and second medium layer is silicon nitride layer.When the requirement of follow-up formed groove live width is less than or equal to 0.5 micron, the material of second medium layer is preferably polysilicon and silicon nitride, concrete, and second medium layer is polysilicon layer and is positioned at the silicon nitride layer on described polysilicon layer.Material by second medium layer is preferably polysilicon and silicon nitride, can make the beak length of follow-up formed beak structure less, thereby can reduce the loss of follow-up formed groove top live width, is easy to obtain the groove that live width is less.Further, the thickness of described second medium layer 32 is 1000 dust～5000 dusts, and for example, the thickness of described second medium layer 32 is 1000 dusts, 1300 dusts, 1800 dusts, 2500 dusts, 3000 dusts, 3800 dusts, 4200 dusts or 5000 dusts.
Preferably, described second medium layer 32 is 3:1 with the Thickness Ratio of first medium layer 31.Especially, when the material of described second medium layer 32 is silicon nitride, described second medium layer 32 is made as 3:1, the stress between can mate better/balance rete with the Thickness Ratio of first medium layer 31.
Then, as shown in Figure 8, remove part second medium layer 32, form first window 33.Concrete, can form by the following method described first window 33: first, on described second medium layer 32 surface, form photoresist; Then, described photoresist is carried out to photoetching process, so that described photoresist exposes part second medium layer 32; Then, the part second medium layer 32 exposing is carried out to etching technics, thereby form first window 33; Finally, can remove photoresist and add the mode that wet method removes photoresist and remove remaining photoresist by dry method.
In the embodiment of the present application, owing to only having removed part second medium layer 32, and retained first medium layer 31, in first window 33, there is first medium layer 31, can avoid thus having particle contaminant or step difference in the region of the edge of first window 33 first medium layer 31 and second medium layer 32 handing-over, thereby improve the pattern of formed beak structure after follow-up execution oxidation technology.
Then, as shown in Figure 9, carry out oxidation technology, in described first window 33, form beak structure 34.Preferably, the thickness of described beak structure is 500 dust～10000 dusts, and for example, the thickness of described beak structure is 500 dusts, 1500 dusts, 2000 dusts, 3500 dusts, 5000 dusts, 6500 dusts, 8500 dusts or 10000 dusts.
Concrete, owing to there is no second medium layer in first window 33, therefore, when carrying out oxidation technology, will optionally in first window 33, carry out oxidation reaction, form beak structure 34.Further, when carrying out oxidation technology, first medium layer 31 in first window 33 and the interface of Semiconductor substrate 30, having oxidizing atmosphere enters, and more past to have the direction oxidizing atmosphere that second medium layer 32 covers fewer, thereby the interface that causes first medium layer 31 from first window 33 and Semiconductor substrate 30 is toward the direction that has second medium layer 32 and cover, oxidation reaction more and more a little less than, reduce gradually toward having the direction that second medium layer 32 covers the interface of the first medium layer 31 of the corresponding Semiconductor substrate 30 consuming from first window 33 and Semiconductor substrate 30, thereby in first window 33, form the structure that industry is called " beak ".
Further, in first window 33, the growth thickness of formed beak structure 34 is thicker, and the beak length of beak structure 34 is longer, thereby the angle at follow-up formation groove top is rounder and more smooth.This kind of situation is applicable to for the less demanding product of groove live width.
In addition, when the material of the second medium layer 32 of selecting is polysilicon and silicon nitride (concrete, to cover silicon nitride layer on polysilicon layer), can effectively reduce the beak length of beak structure 34, thereby be applicable to the product of having relatively high expectations for groove live width.
Further, when the material of the second medium layer 32 of selecting is silicon nitride, under identical oxidation technology condition, second medium layer 32(silicon nitride) thickness is thicker, and the beak length of beak structure 34 is less.But at this, preferred described second medium layer 32 is 3:1 with the Thickness Ratio of first medium layer 31, thus the stress between can mate better/balance rete.
Then, as shown in figure 10, beak structure 34 and Semiconductor substrate 30 described in etching, form Second Window 35.Concrete, beak structure 34 and Semiconductor substrate 30 described in etching, form Second Window 35 and comprise: carry out first step etching technics, remove described beak structure 34; Carry out second step etching technics, remove part semiconductor substrate 30.In the embodiment of the present application, first step etching technics adopts dry etch process; Preferably, this first step etching technics adopts over etching technique, and etching is excessive.Thus, in the time of can avoiding second step etching, there is the problems such as residual, burr, thereby improve the quality of formed semiconductor device.In the embodiment of the present application, the etching depth of second step etching technics is 0.1 micron～50 microns, and wherein, the etching depth of this second step etching technics is determined by the degree of depth of the groove that will form.
Then, as shown in figure 11, remove described second medium layer 32 and first medium layer 31, form the 3rd window 36.At this, between the sidewall of described the 3rd window 36 and Semiconductor substrate 30 upper surfaces, between the sidewall and sidewall of described the 3rd window 36, all have angle between the sidewall of described the 3rd window 36 and diapire and between the diapire of described the 3rd window 36 and diapire, and angle is obtuse angle.In the embodiment of the present application, can add wet-etching technology by dry method and remove described second medium layer 32 and first medium layer 31, form the 3rd window 36.
Concrete, please also refer to Figure 11 and Figure 14, between the sidewall of described the 3rd window 36 and Semiconductor substrate 30 upper surfaces, have between the sidewall of angle theta 5, described the 3rd window 36 and sidewall, to have between the sidewall of angle theta 6, described the 3rd window 36 and diapire, to have between the diapire of angle theta 7 and described the 3rd window 36 and diapire and there is angle theta 8, wherein, angle theta 5, angle theta 6, angle theta 7 and angle theta 8 are obtuse angle.
Contrast Figure 11 and Fig. 3 are visible, and in the embodiment of the present application, owing to having formed beak structure, two obtuse angles appear in the top of formed the 3rd window 36, compared to the right-angle structure in Fig. 3, have effectively improved the pattern of window.
Then, please refer to Figure 12, at described the 3rd window 36 and Semiconductor substrate 30 surfaces, carry out repair layer growth, then remove the repair layer of growth, form groove 37.At this, the turning point of described groove 37 is circular arc.In the embodiment of the present application, by high temperature oxidation process, form described repair layer, the material of formed repair layer is oxide thus.Preferably, the temperature of described high temperature oxidation process is 1000 ℃～1200 ℃.High temperature can make sidewall and the diapire of the angle between diapire and described the 3rd window 36 and the angle corners between diapire of the sidewall of the sidewall of the 3rd window 36 and the angle between Semiconductor substrate 30 upper surfaces, described the 3rd window 36 and the angle between sidewall, described the 3rd window 36, and temperature is higher, the effect of ovaler angling of time is better, and the circular arc of the turning point of formed groove 37 is more round and smooth.
Further, the thickness of described repair layer is 500 dust～5000 dusts.The thickness of described repair layer is thicker, and the thickness of the Semiconductor substrate 30 of consumption is also thicker, will produce thus larger live width loss, and therefore, preferred, the thickness of described repair layer is 500 dust～5000 dusts.Concrete, can select suitable process time and repair layer thickness according to the actual conditions of the semiconductor device/product that will form.
In the embodiment of the present application, by rinsing (being wet processing), remove described repair layer.Incorporated by reference to reference to Figure 14 and Figure 12; original angle theta 5, angle theta 6, angle theta 7 and angle theta 8 places, all become circular arc, makes thus the pattern integral body of groove 37 relax very much; when applying voltage and energy, can make whole groove ideal in an equipotentiality state.
Then, please refer to Figure 13, at described groove 37 and Semiconductor substrate 30 surfaces, form oxide layer 38.In the embodiment of the present application, the technological temperature that forms described oxide layer 38 is preferably 1050 ℃～1150 ℃.Preferably, utilize and mix oxychloride in described groove 37 and Semiconductor substrate 30 surface formation oxide layers 38, mix oxychloride and can effectively reduce the mobile ion in oxide layer 38, improve the quality of described oxide layer 38.
Further, contrast Figure 15 and Fig. 5, wherein, in Figure 15, d7, d8, d9, d10, d11, d12 position are corresponding with d1, d2 in Fig. 5, d3, d4, d5, d6 position respectively, can find out, in the embodiment of the present application, corner is due to the optimization of groove pattern, oxidated layer thickness uniformity is obviously promoted, thereby improved the characteristic of semiconductor device, guarantee stability and the reliability of semiconductor device.
Please continue to refer to Figure 13, the formation method by above-mentioned semiconductor trench structure will form following semiconductor groove structure as seen, and it specifically comprises: Semiconductor substrate 30; In described Semiconductor substrate 30, being formed with groove 37(can be with reference to Figure 12), the turning point of described groove 37 is circular arc; Described groove 37 and Semiconductor substrate 30 surfaces are formed with oxide layer 38.Further, described Semiconductor substrate 30 is the Semiconductor substrate in N-type <100> crystal orientation.The degree of depth of described groove 37 is 0.1 micron～50 microns.
As fully visible, in semiconductor trench structure providing in the embodiment of the present application and forming method thereof, by carrying out oxidation technology, in first window, form beak structure, due to the existence of described beak structure, will obtain good, the round and smooth groove of pattern, thereby can in this groove, obtain the oxide layer of even thickness, improve the characteristic of semiconductor device, guaranteed stability and the reliability of semiconductor device.
Foregoing description is only the description to the utility model preferred embodiment; the not any restriction to the utility model scope; any change, modification that the those of ordinary skill in the utility model field is done according to above-mentioned disclosure, all belong to the protection range of claims.
Claims (3)
1. a semiconductor trench structure, is characterized in that, comprising: Semiconductor substrate; In described Semiconductor substrate, be formed with groove, the turning point of described groove is circular arc; Described groove and semiconductor substrate surface are formed with oxide layer.
2. semiconductor trench structure as claimed in claim 1, is characterized in that, described Semiconductor substrate is the Semiconductor substrate in N-type <100> crystal orientation.
3. semiconductor trench structure as claimed in claim 1, is characterized in that, the degree of depth of described groove is 0.1 micron～50 microns.
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| CN201420106256.6U CN203733772U (en) | 2014-03-10 | 2014-03-10 | Semiconductor groove structure |
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| CN201420106256.6U CN203733772U (en) | 2014-03-10 | 2014-03-10 | Semiconductor groove structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111986992A (en) * | 2019-05-23 | 2020-11-24 | 芯恩（青岛）集成电路有限公司 | Groove etching method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111986992A (en) * | 2019-05-23 | 2020-11-24 | 芯恩（青岛）集成电路有限公司 | Groove etching method |
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