CN109390209B - Semiconductor device, manufacturing method thereof and electronic device - Google Patents
Semiconductor device, manufacturing method thereof and electronic device Download PDFInfo
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- CN109390209B CN109390209B CN201710656780.9A CN201710656780A CN109390209B CN 109390209 B CN109390209 B CN 109390209B CN 201710656780 A CN201710656780 A CN 201710656780A CN 109390209 B CN109390209 B CN 109390209B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
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Abstract
The invention provides a semiconductor device, a method of manufacturing the same, and an electronic apparatus, including: providing a semiconductor substrate, wherein a convex structure is formed on the surface of the semiconductor substrate; and processing the surface of the semiconductor substrate by using oxygen-containing plasma to form a rough oxidation layer on the surface of the semiconductor substrate. The rough oxide layer can relatively slow down the flowing speed of the mask layer on the surface of the substrate, reduce the difference between the thicknesses of the mask layer at the height difference between the protruding structure and the surface of the substrate, further improve the consistency of the feedback of the mask layer on the exposure capability, improve the consistency of the subsequently formed source/drain critical dimension, and increase the adhesion between the surface of the semiconductor substrate and the mask layer.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof and an electronic device.
Background
With the continuous development of semiconductor technology, the performance of integrated circuits is improved mainly by the continuous reduction of the size of integrated circuit devices to increase the speed thereof. Currently, as the semiconductor industry has progressed to the point of nanotechnology process in pursuit of high device density, high performance, and low cost, the fabrication of semiconductor devices is limited by various physical limitations.
High-voltage power devices in semiconductor devices are widely applied in the fields of aerospace, industrial control and automotive electronics. However, in the manufacturing process of the high-voltage device with a smaller line width, two common problems exist in the source and drain structure process part, which have negative influence on the yield (yield) and the electrical performance of the product, one problem is that the consistency of the critical dimension of the source and drain part is poor, the difference of the chip dimension of a single wafer is 50nm at most, and the variability exceeds 20%; another problem is that on the substrate with the crystal orientation (1,0,0), the tunneling effect often occurs due to the high frequency sub-high energy implantation of the source and drain, resulting in low product yield or poor electrical stability.
Therefore, in view of the above problems, it is necessary to provide a new method for manufacturing a semiconductor device.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In view of the shortcomings of the prior art, one aspect of the present invention provides a method for manufacturing a semiconductor device, comprising:
providing a semiconductor substrate, wherein a convex structure is formed on the surface of the semiconductor substrate;
and processing the surface of the semiconductor substrate by using oxygen-containing plasma to form a rough oxidation layer on the surface of the semiconductor substrate.
Illustratively, after the forming the oxide layer, the method further comprises the following steps: and annealing the surface of the semiconductor substrate to smooth the surface of the semiconductor substrate and form an amorphous material layer between the semiconductor substrate and the rough oxide layer.
Illustratively, the laser annealing is excimer laser annealing.
Illustratively, the semiconductor substrate is a silicon substrate and the amorphous material layer comprises amorphous silicon.
Illustratively, the protruding structure is a gate structure.
Exemplarily, the method further comprises the following steps after the forming of the rough oxide layer:
and forming a mask layer to cover the surface of the semiconductor substrate and the protruding structure.
Illustratively, the method further comprises the following steps after the mask layer is formed:
patterning the mask layer to form an opening in the mask layer, wherein the opening exposes a region, in the semiconductor substrate, where a source electrode and a drain electrode are scheduled to be formed;
performing source-drain ion implantation by taking the mask layer as a mask to form a source electrode and a drain electrode in the semiconductor substrate;
and removing the mask layer.
Illustratively, the oxygen-containing plasma is generated from a mixed gas of a rare gas and an oxygen-containing gas, wherein the plasma generated from the rare gas performs ion bombardment on the surface of the semiconductor substrate to form a rough surface, and the oxygen-containing gas oxidizes the surface of the semiconductor substrate to form the rough oxide layer.
Illustratively, the rare gas has a flow rate ranging from 100sccm to 150sccm, the oxygen-containing gas has a flow rate ranging from 30sccm to 70sccm, the upper electrode has a radio frequency power ranging from 100W to 200W, and the lower electrode has a power ranging from 30W to 60W.
Still another aspect of the present invention provides a semiconductor device including:
the semiconductor device comprises a semiconductor substrate, wherein a convex structure is formed on the surface of the semiconductor substrate;
a rough oxide layer is formed on the surface of the semiconductor substrate.
Exemplarily, the method further comprises the following steps: and an amorphous material layer formed between the semiconductor substrate and the roughened oxide layer.
Illustratively, the semiconductor substrate is a silicon substrate and the amorphous material layer comprises amorphous silicon.
Illustratively, the protruding structure is a gate structure, and a source electrode and a drain electrode are respectively formed in the semiconductor substrate on two sides of the gate structure.
Another aspect of the present invention provides an electronic apparatus including the semiconductor device described above.
The manufacturing method of the invention processes the surface of the substrate through plasma to form a rough oxidation layer on the surface of the semiconductor substrate, wherein the rough oxidation layer can relatively slow down the flowing speed of a mask layer (such as photoresist) on the surface of the substrate, the difference between the thicknesses of the mask layer (such as photoresist) at the height difference of the convex structure and the surface of the substrate is reduced, the feedback consistency of the mask layer (such as photoresist) on the exposure capability is improved, the consistency of the subsequently formed source/drain critical dimension is improved, and the adhesion between the surface of the semiconductor substrate and the mask layer can be increased.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIG. 1 is a schematic cross-sectional view of a device after a photoresist layer is formed on the surface of a substrate before source-drain implantation in a conventional process;
fig. 2 shows a process flow diagram of a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 3 shows a process flow diagram of a method of manufacturing a semiconductor device according to another embodiment of the present invention;
fig. 4 shows a schematic diagram of an electronic device in an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
In the existing preparation process of a semiconductor device, for example, in the preparation process of a small-linewidth high-voltage device, the consistency of the sizes of source and drain structures is very poor, the maximum difference of critical sizes in a chip reaches 50nm, the variability exceeds 20 percent, and the target of less than 10 percent of the process requirement cannot be achieved. The analysis and research on the phenomenon show that the height difference of different areas of the substrate exceeds 2000 angstroms due to the existence of patterns of a substrate surface such as a gate structure (such as a polysilicon gate structure) during the process of forming the source and drain. The photoresist is dropped through a nozzle at the center of the substrate, and then the liquid is flowed over the entire surface of the substrate (i.e., wafer) rotating at a high speed. The photoresist flows fast on the surface of a smooth substrate, the photoresist thickness can have obvious difference at the junction of the height difference of the pattern, as shown in fig. 1, a plurality of spaced polysilicon gate structures 101 are arranged on the substrate, the photoresist 102 covers the surface of the substrate and the surface of the polysilicon gate structures, the height difference is formed between the polysilicon gate structures 101 and the surface of the substrate, the photoresist thickness can have obvious difference at the junction of the height difference of the pattern, whether the dimension of the concerned pattern in the chip is abnormal can be shown by monitoring the change of the dimension of L-Bar, and the L-Bar is the pattern which is arranged on a cutting channel in particular for detecting the key dimension of the concerned pattern in the chip in the semiconductor production. Due to the fact that different photoresist thicknesses have different feedback on exposure energy, the source and drain critical dimensions are greatly different. On the other hand, the high-voltage device requires multiple times of ion implantation with high energy at the source and drain part, and tunneling effect occurs sometimes for a substrate with a crystal orientation of (1,0,0), which causes that the stability of the electrical performance of the product cannot meet the requirement of mass production, and even causes the device to fail under severe conditions.
For the above problems, there is no effective radical measure in the industry, and for the uniformity problem of the substrate, it is usually improved by adding a bottom anti-reflective coating (BARC) on the bottom of the photoresist or a top anti-reflective coating (TARC) on the top of the photoresist, but this greatly increases the production cost. The problem of the tunneling effect is mainly to achieve the optimal result by debugging the injection angle and the injection energy of different products, which greatly slows down the progress of new product development and simultaneously increases the labor cost of engineers and the like.
In view of the above problems, the present invention provides a method for manufacturing a semiconductor device, as shown in fig. 2, mainly comprising the following steps:
step S1, providing a semiconductor substrate, wherein a convex structure is formed on the surface of the semiconductor substrate;
step S2, processing the surface of the semiconductor substrate using oxygen-containing plasma to form a rough oxide layer on the surface of the semiconductor substrate.
In summary, the manufacturing method of the present invention processes the substrate surface by plasma to form a rough oxide layer on the surface of the semiconductor substrate, wherein the rough oxide layer can relatively slow down the flow speed of the mask layer (e.g. photoresist) on the substrate surface, and the difference between the thicknesses of the mask layer (e.g. photoresist) at the height difference between the bump structure and the substrate surface is reduced, thereby improving the consistency of the feedback of the mask layer (e.g. photoresist) to the exposure capability and the consistency of the subsequently formed source/drain critical dimension.
Next, a method for manufacturing a semiconductor device of the present invention is described in detail with reference to fig. 3, in which fig. 3 shows a process flow chart of a method for manufacturing a semiconductor device of another embodiment of the present invention.
As an example, a method for manufacturing a semiconductor device of the present invention includes the steps of:
first, step S11 is performed to provide a semiconductor substrate having a bump structure formed on a surface thereof.
Specifically, the constituent material of the semiconductor substrate may be undoped single-crystal silicon, impurity-doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stack (SSOI), silicon-on-insulator germanium (S-SiGeOI), silicon-on-insulator germanium (SiGeOI), germanium-on-insulator (GeOI), or the like. As an example, in the present embodiment, the constituent material of the semiconductor substrate is single crystal silicon.
The semiconductor substrate may also be a P-type semiconductor substrate or an N-type semiconductor substrate, for example, a P-type semiconductor substrate may be selected for an N-type high-voltage device, and an N-type semiconductor substrate may be selected for a P-type high-voltage device.
Illustratively, various well regions may also be formed in the semiconductor substrate, and shallow trench isolation structures may also be provided in the semiconductor substrate to define active regions.
Illustratively, a raised structure is further formed on the surface of the semiconductor substrate, and a height difference is formed between the raised structure and the surface of the semiconductor substrate, and the raised structure can be any structure with a certain height formed on the surface of the semiconductor substrate, which is well known to those skilled in the art.
In one example, for a high voltage device, such as an LDMOS device, a drift region is further formed in the semiconductor substrate, and the drift region has different conductivity types according to the type of the specific LDMOS device, for example, if the LDMOS device is an N-type LDMOS device, the drift region is an N-type drift region, and if the LDMOS device is a P-type LDMOS device, the drift region is a P-type drift region.
In general, the doping concentration of the drift region is lower than that of the source and the drain, which is equivalent to forming a high resistance layer between the source and the drain, so that the breakdown voltage can be improved, the parasitic capacitance between the source and the drain can be reduced, and the frequency characteristic can be improved.
Illustratively, the protruding structure is a gate structure, and the gate structure may further cover a portion of the surface of the drift region to serve as a field plate.
In an embodiment, the gate dielectric layer may comprise conventional dielectric materials such as oxides, nitrides and oxynitrides of silicon having a dielectric constant from about 4 to about 20 (measured in vacuum), or the gate dielectric layer may comprise a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant electrolyte materials may include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, Barium Strontium Titanate (BSTs), and lead zirconate titanate (PZTs). The gate layer is made of polysilicon, and typically, a metal nitride, a metal silicide or the like may be used as the material of the gate layer.
In one example, a plurality of raised structures, such as gate structures, may also be provided on the semiconductor substrate.
The gate structure may be formed by any suitable method known to those skilled in the art and will not be described in detail herein.
In one example, spacers are formed on sidewalls of the gate structure. The spacer can be made of one of silicon oxide, silicon nitride and silicon oxynitride or a combination of the silicon oxide and the silicon nitride.
Next, step S12 is performed to process the surface of the semiconductor substrate with oxygen-containing plasma to form a rough oxide layer on the surface of the semiconductor substrate.
Illustratively, the oxygen-containing plasma is generated from a mixed gas of a rare gas and an oxygen-containing gas.
Wherein the rare gas may include at least one of He, Ne, Ar, Kr, and Xe, the oxygen-containing gas may include at least one of oxygen, ozone, and oxynitride gas, and in this embodiment, the rare gas is mainly Ar, and the oxygen-containing gas is O2。
Illustratively, the oxygen-containing plasma is a weak plasma having a lower energy that only slightly modifies the surface of the semiconductor substrate, and the weak plasma can be generated by having a plasma generating apparatus with a low rf power and a low flow rate of the reactive gas, wherein the weak plasma is used to only slightly modify the surface of the semiconductor substrate to facilitate subsequent repair of the surface of the semiconductor substrate by annealing.
In one example, during the plasma treatment of the surface of the semiconductor substrate, the plasma generated from the rare gas performs ion bombardment on the surface of the semiconductor substrate to form a rough surface, and the oxygen-containing gas oxidizes the surface of the semiconductor substrate to form a rough oxide layer.
This step may be performed in a semiconductor etching apparatus, and any type of etching apparatus known to those skilled in the art may be used, and may also be performed in other apparatuses capable of generating plasma.
In one example, a semiconductor substrate is placed in a reaction apparatus, such as an etching apparatus, and Ar and O are introduced into a chamber of the reaction apparatus2Ar and O2Generating a weak plasma with a semiconductor substrateSurface reactions, e.g. ion bombardment of the surface of the semiconductor substrate by Ar plasma, to obtain a rough surface, and O2React with the surface of the semiconductor substrate to form a rough oxide layer.
The weak plasma may be formed by controlling process parameters of the plasma process, and illustratively, the rare gas may be made to have a low flow rate, for example, the flow rate of the rare gas (e.g., Ar and/or He) ranges from 100sccm to 150sccm, the flow rate of the oxygen-containing gas (e.g., oxygen) ranges from 30 to 70sccm, and a lower upper electrode rf Power, for example, an upper electrode rf Power range of 100W to 200W, for example, 120W, 150W, 180W, 200W, and a lower electrode Power (Bottom Power) range of 30 to 60W, may be used.
Illustratively, the thickness of the generated rough oxide layer can also be controlled by controlling the plasma treatment time, for example, the oxygen-containing plasma treatment time is in the range of 30s to 45 s.
In one example, the rough oxide layer is formed to have a very thin thickness, for example, the rough oxide layer may have a thickness ranging from 20 angstroms to 30 angstroms.
Next, step S13 is performed to anneal the surface of the semiconductor substrate to smooth the surface of the semiconductor substrate and form an amorphous material layer between the semiconductor substrate and the roughened oxide layer.
In particular, the annealing may be any suitable annealing means known to those skilled in the art capable of smoothing the surface of the semiconductor substrate, the annealing being performed for a portion of the thickness of the semiconductor substrate surface.
In one example, the semiconductor substrate is a silicon substrate and the amorphous material layer includes amorphous silicon.
The annealing may be laser annealing, and in this embodiment, the laser annealing is preferably Excimer Laser Annealing (ELA).
Wherein, the excimer laser annealing is used for processing the surface of the semiconductor substrate, repairing the plasma damage on the surface of the semiconductor substrate, and simultaneously forming micro-local co-melting on the surface of the semiconductor substrate, wherein the micro-local is a region of less than 1 micron on the surface of the semiconductor substrate, and when the semiconductor substrate is monocrystalline silicon, after the excimer laser annealing, the surface of the semiconductor substrate is cooled to form amorphous silicon (namely amorphous silicon) without fixed crystal orientation after the silicon in the single crystal orientation (1,1,0) is locally melted, so as to obtain a smooth surface, wherein the rough surface obtained by processing the surface of the substrate by plasma in the previous step is relatively sharp, and the sharp rough surface has negative influence on the leakage performance of the device, therefore, the surface of the semiconductor substrate is properly smoothed by the laser annealing, for example, the sharp rough surface is slightly smoothed into a smooth surface with protrusions similar to a circular arc shape, the smoothed surface retains a certain degree of roughness, thereby facilitating the formation of a mask layer (e.g., a photoresist) with good thickness uniformity in subsequent steps.
In one example, the light source for excimer laser annealing can be XeCl, or other suitable light source, the laser is uv light, such as uv light with a wavelength of 308nm, the pulse time is 30 ns-150 ns, preferably 150ns, and the laser Energy Density (ED) ranges from 0-3J/cm2The annealing time is in the range of 60s to 200s, for example, preferably 120 s.
After excimer laser annealing, the semiconductor substrate obtains a smooth surface, and an amorphous material layer is formed between the semiconductor substrate and the rough oxide layer, so that the occurrence of tunneling effect is avoided, and the adhesion between a subsequently formed mask layer (such as photoresist) and the semiconductor substrate can be improved.
Next, step S14 is performed to form a mask layer to cover the surface of the semiconductor substrate and the bump structure.
The mask layer includes a photoresist layer, but may be other mask layers that can be applied to the surface of the semiconductor substrate by, for example, a spin-on process.
In one example, a photoresist layer is formed on the surface of a semiconductor substrate by a spin coating process, for example, the photoresist is dripped to the center of the semiconductor substrate through a nozzle, then the liquid photoresist covers the whole surface of the semiconductor substrate by flowing on the semiconductor substrate rotating at a high speed, and because a rough oxide layer is formed on the surface of the semiconductor substrate, the flowing speed of the photoresist on the surface of the semiconductor substrate is reduced, so that the relative difference of the photoresist thickness is reduced at the interface of the height difference between a protruding structure (such as a gate structure) and the surface of the semiconductor substrate, thereby avoiding the problem of inconsistent feedback of exposure energy caused by inconsistent thickness, further improving the dimensional consistency of subsequently formed source and drain electrodes, and simultaneously increasing the adhesion between the semiconductor substrate and the photoresist.
It is to be noted that a plurality of gate structures may be formed on the semiconductor substrate, and a source electrode and a drain electrode may be formed in the semiconductor substrate at both sides of each gate structure, and thus, a plurality of source electrodes and drain electrodes may be formed on the semiconductor substrate.
Next, step S15 is performed to pattern the mask layer to form openings in the mask layer, where the openings expose areas of the semiconductor substrate where the source and the drain are to be formed.
In one example, when the mask layer is a photoresist layer, the mask layer may be patterned using a photolithography process to form an opening in the mask layer, where the opening exposes a region of the semiconductor substrate where a source and a drain are to be formed.
The photolithography process includes exposing and developing the photoresist layer.
Next, in step S16, a source/drain ion implantation is performed using the mask layer as a mask to form a source and a drain in the semiconductor substrate.
The source and drain ion implantation may be a process well known to those skilled in the art, in which the type of doping impurities of the ion implantation is selected according to the type of device to be formed, for example, N-type source and drain are to be formed, and then N-type doping impurities, for example, one of phosphorus and arsenic, are used, and if P-type source and drain are to be formed, then P-type doping impurities, for example, boron, are used.
Subsequently, an annealing process may be performed, and the annealing process may use any annealing method known to those skilled in the art, including but not limited to rapid thermal annealing, furnace annealing, spike annealing, laser annealing, etc., for example, a rapid thermal annealing process is performed to activate the dopants in the source/drain regions by using a high temperature of 900 to 1050 ℃, and simultaneously repair the lattice structure of the semiconductor substrate surface damaged in each ion implantation process. In addition, depending on the product requirements and functional considerations, Lightly Doped Drains (LDDs) may be formed between the source/drain regions and the gates, respectively.
Finally, step S17 is executed to remove the mask layer.
For example, when the mask layer is a photoresist layer, the photoresist layer may be removed by ashing or wet cleaning, where the wet cleaning may use an SPM solution, and the SPM solution includes sulfuric acid and hydrogen peroxide.
After that, the semiconductor substrate may be selectively subjected to a wet cleaning step to remove impurities on the surface of the semiconductor substrate, the wet cleaning step may remove the rough oxide layer, and the wet cleaning step may use a hydrofluoric acid solution, such as a Buffered Oxide Etchant (BOE) or a buffered hydrofluoric acid (BHF) or a diluted hydrofluoric acid solution.
Of course, the rough oxide layer may be retained without affecting the device function.
Thus, the key steps of the method for manufacturing a semiconductor device of the present invention are described, wherein other steps are required for the complete device fabrication, which is not described herein again. It is worth mentioning that the semiconductor device of the present invention may be a high voltage device known to those skilled in the art, such as an LDMOS device or a VDMOS device, and may also be a standard CMOS device or other devices.
In summary, the manufacturing method of the present invention processes the surface of the substrate by plasma to form a rough oxide layer on the surface of the semiconductor substrate, wherein the rough oxide layer can relatively slow down the speed of the mask layer (e.g. photoresist) on the surface of the substrate, reduce the difference between the thicknesses of the mask layer (e.g. photoresist) at the height difference between the protruding structure (e.g. gate structure) and the substrate surface, thereby improving the consistency of the feedback of the mask layer (e.g. photoresist) to the exposure capability, improve the consistency of the critical dimension of the formed source/drain, and simultaneously increase the adhesion between the mask layer (e.g. photoresist) and the semiconductor substrate, and process the surface of the semiconductor substrate by an annealing process (e.g. excimer laser annealing) to obtain a smooth surface and simultaneously form an amorphous material layer (e.g. amorphous silicon), furthermore, the method is simple and easy to operate, has low production cost, does not need to consume too much labor cost, and finally improves the performance and yield of the device.
Example two
The invention also provides a semiconductor device prepared by the method in the first embodiment.
As an example, the semiconductor device includes: a semiconductor substrate.
Specifically, the constituent material of the semiconductor substrate may be undoped single-crystal silicon, impurity-doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stack (SSOI), silicon-on-insulator germanium (S-SiGeOI), silicon-on-insulator germanium (SiGeOI), germanium-on-insulator (GeOI), or the like. As an example, in the present embodiment, the constituent material of the semiconductor substrate is single crystal silicon.
The semiconductor substrate may also be a P-type semiconductor substrate or an N-type semiconductor substrate, for example, a P-type semiconductor substrate may be selected for an N-type high-voltage device, and an N-type semiconductor substrate may be selected for a P-type high-voltage device.
Illustratively, various well regions may also be formed in the semiconductor substrate, and shallow trench isolation structures may also be provided in the semiconductor substrate to define active regions.
Illustratively, a raised structure is further formed on the surface of the semiconductor substrate, and a height difference is formed between the raised structure and the surface of the semiconductor substrate, and the raised structure can be any structure with a certain height formed on the surface of the semiconductor substrate, which is well known to those skilled in the art.
In one example, for a high voltage device, such as an LDMOS device, a drift region is further formed in the semiconductor substrate, and the drift region has different conductivity types according to the type of the specific LDMOS device, for example, if the LDMOS device is an N-type LDMOS device, the drift region is an N-type drift region, and if the LDMOS device is a P-type LDMOS device, the drift region is a P-type drift region.
In general, the doping concentration of the drift region is lower than that of the source and the drain, which is equivalent to forming a high resistance layer between the source and the drain, so that the breakdown voltage can be improved, the parasitic capacitance between the source and the drain can be reduced, and the frequency characteristic can be improved.
Illustratively, the protruding structure is a gate structure, and the gate structure may further cover a portion of the surface of the drift region to serve as a field plate.
In an embodiment, the gate dielectric layer may comprise conventional dielectric materials such as oxides, nitrides and oxynitrides of silicon having a dielectric constant from about 4 to about 20 (measured in vacuum), or the gate dielectric layer may comprise a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant electrolyte materials may include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, Barium Strontium Titanate (BSTs), and lead zirconate titanate (PZTs). The gate layer is made of polysilicon, and typically, a metal nitride, a metal silicide or the like may be used as the material of the gate layer.
In one example, a plurality of raised structures, such as gate structures, may also be provided on the semiconductor substrate.
In one example, spacers are formed on sidewalls of the gate structure. The spacer can be made of one of silicon oxide, silicon nitride and silicon oxynitride or a combination of the silicon oxide and the silicon nitride.
In one example, a rough oxide layer is formed on a surface of the semiconductor substrate. The material of the rough oxide layer may be silicon oxide, silicon oxynitride, or the like.
In one example, the rough oxide layer is formed to have a very thin thickness, for example, the rough oxide layer may have a thickness ranging from 20 angstroms to 30 angstroms.
Illustratively, the semiconductor device further comprises an amorphous material layer formed between the semiconductor substrate and the roughened oxide layer.
In one example, the semiconductor substrate is a silicon substrate and the amorphous material layer includes amorphous silicon.
The surface of the semiconductor substrate is a smooth surface, and an amorphous material layer is formed between the semiconductor substrate and the rough oxide layer, so that the tunneling effect is avoided.
In one example, a source and a drain are formed in the semiconductor substrate on either side of the gate structure.
The source and the drain have the same conductivity type as the drift region 101, for example, the drift region is an N-type drift region, and the drain and the source may be an N-type source and a drain, and may also be a source and a drain heavily doped with N-type doped ions.
And because the surface of the semiconductor device is formed with the rough oxide layer, the consistency of the critical dimensions of the source electrode and the drain electrode can be improved.
The semiconductor device of the present invention has the same advantages as the above embodiment because it is manufactured by the method of the above embodiment.
EXAMPLE III
The invention also provides an electronic device comprising the semiconductor device of the second embodiment, and the semiconductor device is prepared according to the method of the first embodiment.
The electronic device of this embodiment may be any electronic product or device, such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, and the like, and may also be any intermediate product including a circuit. The electronic device of the embodiment of the invention has better performance due to the use of the semiconductor device.
Wherein figure 4 shows an example of a mobile telephone handset. The mobile phone handset 300 is provided with a display portion 302, operation buttons 303, an external connection port 304, a speaker 305, a microphone 306, and the like, which are included in a housing 301.
Wherein the mobile phone handset comprises the semiconductor device of embodiment two, the semiconductor device comprising:
the semiconductor device comprises a semiconductor substrate, wherein a convex structure is formed on the surface of the semiconductor substrate;
a rough oxide layer is formed on the surface of the semiconductor substrate.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (11)
1. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate, wherein a convex structure is formed on the surface of the semiconductor substrate;
processing the surface of the semiconductor substrate by using oxygen-containing plasma to form a rough oxidation layer on the surface of the semiconductor substrate, wherein the rough oxidation layer is used for slowing down the flowing speed of the photoresist layer on the surface of the semiconductor substrate;
annealing the surface of the semiconductor substrate to smooth the surface of the semiconductor substrate and form an amorphous material layer between the semiconductor substrate and the roughened oxide layer;
and forming a mask layer by a spin coating process to cover the surface of the semiconductor substrate and the protruding structure, wherein the mask layer comprises a photoresist layer.
2. The method of manufacturing of claim 1, wherein the annealing is excimer laser annealing.
3. The manufacturing method according to claim 1, wherein the semiconductor substrate is a silicon substrate, and the amorphous material layer includes amorphous silicon.
4. The method of manufacturing of claim 1, wherein the raised structure is a gate structure.
5. The method of manufacturing of claim 1, further comprising, after forming the mask layer, the steps of:
patterning the mask layer to form an opening in the mask layer, wherein the opening exposes a region, in the semiconductor substrate, where a source electrode and a drain electrode are scheduled to be formed;
performing source-drain ion implantation by taking the mask layer as a mask to form a source electrode and a drain electrode in the semiconductor substrate;
and removing the mask layer.
6. The manufacturing method according to claim 1, wherein the oxygen-containing plasma is generated from a mixed gas of a rare gas and an oxygen-containing gas, wherein the plasma generated from the rare gas performs ion bombardment on the surface of the semiconductor substrate to form a rough surface, and the oxygen-containing gas oxidizes the surface of the semiconductor substrate to form the rough oxide layer.
7. The method according to claim 6, wherein the rare gas has a flow rate ranging from 100sccm to 150sccm, the oxygen-containing gas has a flow rate ranging from 30sccm to 70sccm, the upper electrode RF power ranges from 100W to 200W, and the lower electrode RF power ranges from 30W to 60W.
8. A semiconductor device manufactured by the manufacturing method according to any one of claims 1 to 7, comprising:
the semiconductor device comprises a semiconductor substrate, wherein a convex structure is formed on the surface of the semiconductor substrate;
forming a rough oxide layer on the surface of the semiconductor substrate;
and an amorphous material layer formed between the semiconductor substrate and the roughened oxide layer.
9. The semiconductor device according to claim 8, wherein the semiconductor substrate is a silicon substrate, and the amorphous material layer comprises amorphous silicon.
10. The semiconductor device according to claim 8, wherein the protruding structure is a gate structure, and a source and a drain are formed in the semiconductor substrate on both sides of the gate structure, respectively.
11. An electronic device, characterized in that the electronic device comprises the semiconductor device according to one of claims 8 to 10.
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| US5536534A (en) * | 1994-03-25 | 1996-07-16 | Hyundai Electronics Industries Co. Ltd. | Method and apparatus for coating photoresist |
| US20020004300A1 (en) * | 1999-08-09 | 2002-01-10 | Marina V. Plat | Ultra-thin resist coating qualityby by increasing surface roughness of the substrate |
| CN102386065A (en) * | 2010-09-01 | 2012-03-21 | 无锡华润上华半导体有限公司 | Method of improving photoetching critical dimension uniformity |
| CN102810464A (en) * | 2011-06-02 | 2012-12-05 | 无锡华润上华半导体有限公司 | Photoetching method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5536534A (en) * | 1994-03-25 | 1996-07-16 | Hyundai Electronics Industries Co. Ltd. | Method and apparatus for coating photoresist |
| US20020004300A1 (en) * | 1999-08-09 | 2002-01-10 | Marina V. Plat | Ultra-thin resist coating qualityby by increasing surface roughness of the substrate |
| CN102386065A (en) * | 2010-09-01 | 2012-03-21 | 无锡华润上华半导体有限公司 | Method of improving photoetching critical dimension uniformity |
| CN102810464A (en) * | 2011-06-02 | 2012-12-05 | 无锡华润上华半导体有限公司 | Photoetching method |
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