CN109390209A - A kind of semiconductor devices and its manufacturing method and electronic device - Google Patents
A kind of semiconductor devices and its manufacturing method and electronic device Download PDFInfo
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- CN109390209A CN109390209A CN201710656780.9A CN201710656780A CN109390209A CN 109390209 A CN109390209 A CN 109390209A CN 201710656780 A CN201710656780 A CN 201710656780A CN 109390209 A CN109390209 A CN 109390209A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
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Abstract
The present invention provides a kind of semiconductor devices and its manufacturing method and electronic device, comprising: provides semiconductor substrate, is formed with bulge-structure on the surface of the semiconductor substrate；It is handled using the surface to the semiconductor substrate containing oxygen plasma, forms coarse oxide layer with the surface in the semiconductor substrate.The coarse oxide layer can be such that mask layer slows down relatively in the flowing velocity of substrate surface, difference at the high and low fall of bulge-structure and substrate surface between the thickness of mask layer reduces, and then improve mask layer to the consistency of the feedback of exposure capability, improve the consistency for the source/drain critical size being subsequently formed, and the adhesiveness between semiconductor substrate surface and mask layer can be increased.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and its manufacturing method and electronics
Device.
Background technique
With the continuous development of semiconductor technology, the raising of performance of integrated circuits mainly passes through constantly diminution integrated circuit
The size of device is realized with improving its speed.Currently, due in pursuing high device density, high-performance and low cost half
Conductor industry has advanced to nanotechnology process node, and the preparation of semiconductor devices is limited by various physics limits.
High voltage power device in semiconductor devices is widely answered in space flight and aviation, Industry Control and vehicle electric field
With.However, in smaller line width high tension apparatus manufacturing process, source-drain structure process portion there is a problem of two it is more universal to production
The yield (yield) and electrical property of product have compared with negative impact, and a problem is, the consistency of source and drain Partial key size compared with
Difference, the piece inside dimension difference maximum of single-wafer have 50nm, and variability is more than 20%；Another problem is, be in crystal orientation (1,0,
0) on substrate, due to the big energy injection of the high frequency time of source and drain, tunneling effect frequent occurrence, cause product yield low or
Electrical stability is poor.
Therefore, presence in view of the above problems, it is necessary to propose a kind of manufacturing method of new semiconductor devices.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, one aspect of the present invention provides a kind of manufacturing method of semiconductor devices, comprising:
Semiconductor substrate is provided, is formed with bulge-structure on the surface of the semiconductor substrate；
It is handled using the surface to the semiconductor substrate containing oxygen plasma, in the table of the semiconductor substrate
Face forms coarse oxide layer.
Illustratively, further comprising the steps of after forming the oxide layer: to the surface of the semiconductor substrate into
Row annealing with the surface of the smooth semiconductor substrate, and forms nothing between semiconductor substrate and the coarse oxide layer
Amorphous layer.
Illustratively, the laser annealing is quasi-molecule laser annealing.
Illustratively, the semiconductor substrate is silicon substrate, and the amorphous material layer includes amorphous silicon.
Illustratively, the bulge-structure is gate structure.
Illustratively, further comprising the steps of after forming the coarse oxide layer:
Formed mask layer, with cover the semiconductor substrate surface and the bulge-structure.
Illustratively, further comprising the steps of after forming the mask layer:
The mask layer is patterned, to form opening in the mask layer, the opening exposes the semiconductor substrate
In make a reservation for form the region of source electrode and drain electrode；
Using the mask layer as exposure mask, source and drain ion implanting is executed, to form source electrode and drain electrode in the semiconductor substrate；
Remove the mask layer.
Illustratively, described to be generated containing oxygen plasma by the mixed gas of rare gas and oxygen-containing gas, wherein by institute
The plasma for stating rare gas generation carries out ion bombardment to the semiconductor substrate surface, forms rough surface, and by institute
It states oxygen-containing gas and aoxidizes the surface of the semiconductor substrate, and form the coarse oxide layer.
Illustratively, the range of flow of the rare gas is 100sccm~150sccm, the flow of the oxygen-containing gas
Range is 30sccm~70sccm, and top electrode radio frequency power range is 100W~200W, and lower electrode power range is 30W~60W.
Further aspect of the present invention provides a kind of semiconductor devices, comprising:
Semiconductor substrate is formed with bulge-structure on the surface of the semiconductor substrate；
Coarse oxide layer is formed on the surface of the semiconductor substrate.
Illustratively, further includes: the amorphous material layer being formed between semiconductor substrate and the coarse oxide layer.
Illustratively, the semiconductor substrate is silicon substrate, and the amorphous material layer includes amorphous silicon.
Illustratively, the bulge-structure is gate structure, in the semiconductor substrate of the gate structure two sides respectively
It is formed with source electrode and drain electrode.
Another aspect of the present invention provides a kind of electronic device, and the electronic device includes semiconductor devices above-mentioned.
The manufacturing method of the present invention is handled substrate surface by plasma, in the surface shape of semiconductor substrate
At coarse oxide layer, wherein the coarse oxide layer can make mask layer (such as photoresist) in the flowing velocity of substrate surface
Opposite to slow down, the difference at the high and low fall of bulge-structure and substrate surface between such as thickness of the mask layer of photoresist subtracts
It is small, and then improve mask layer (such as photoresist) to the consistency of the feedback of exposure capability, improve the source/drain being subsequently formed and closes
The consistency of key size, and the adhesiveness between semiconductor substrate surface and mask layer can be increased.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
The section that Fig. 1 shows the device in common process before source and drain injection after substrate surface forms photoresist layer shows
It is intended to；
Fig. 2 shows the process flow charts of the manufacturing method of the semiconductor devices of one embodiment of the present invention；
Fig. 3 shows the process flow chart of the manufacturing method of the semiconductor devices of another embodiment of the present invention；
Fig. 4 shows the schematic diagram of the electronic device in one embodiment of the invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that spatial relation term intention further includes making other than orientation shown in figure
With the different orientation with the device in operation.For example, then, being described as " under other elements if the device in attached drawing is overturn
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
It describes to send out herein with reference to the cross-sectional view of the schematic diagram as desirable embodiment (and intermediate structure) of the invention
Bright embodiment.As a result, it is contemplated that from the variation of shown shape as caused by such as manufacturing technology and/or tolerance.Therefore,
The embodiment of the present invention should not necessarily be limited to the specific shape in area shown here, but including due to for example manufacturing caused shape
Shape deviation.For example, being shown as the injection region of rectangle usually has round or bending features and/or implantation concentration ladder at its edge
Degree, rather than binary from injection region to non-injection regions changes.Equally, which can lead to by the disposal area that injection is formed
Some injections in area between the surface passed through when injection progress.Therefore, the area shown in figure is substantially schematic
, their shape is not intended the true form in the area of display device and is not intended to limit the scope of the invention.
In order to thoroughly understand the present invention, detailed step and structure will be proposed in following description, to illustrate this hair
The technical solution of bright proposition.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention
There can also be other embodiments.
At present in the preparation process of semiconductor devices, such as in the preparation process of small line width high tension apparatus, source-drain structure
Size consistency it is excessively poor, critical size difference is up to 50nm in piece, and variability is more than 20%, far from reaching work
The target less than 10% that skill requires.Analysis and research discovery is carried out to this phenomenon, when forming source and drain technical process, due to substrate table
The presence of face such as gate structure (such as polysilicon gate construction) figure is more than 2000 in substrate different zones high and low fall
Angstrom.Photoresist drips the heart in the substrate through spray head, and liquid is whole by flowing covering on high-speed rotating substrate (namely wafer) later
A substrate surface.Photoresist quickly flows on smooth substrates surface, and in figure high and low fall intersection, photoresist thickness can exist brighter
Aobvious difference, as shown in Figure 1, the polysilicon gate construction 101 at several intervals is arranged on substrate, photoresist 102 covers substrate
Surface and the surface of polysilicon gate construction, constitute high and low fall between polysilicon gate construction 101 and substrate surface, are scheming
Shape high and low fall intersection, photoresist thickness can have obvious difference, can by monitor L-bar size variation can be bright
Whether the size that figure is paid close attention in chip is abnormal, and L-Bar is in semiconductor production, to pay close attention to figure in detection chip
Critical size and the figure that is especially arranged on Cutting Road.Since different photoresist thickness are different to the feedback of exposure energy, lead
Cause the larger difference of source and drain critical size.Still further aspect, high tension apparatus require source and drain part repeatedly several and high-energy ions
Injection is the substrate of (1,0,0) for crystal orientation, and tunneling effect happens occasionally, this causes product electrical performance stability that cannot accord with
Resultant produces demand, even results in component failure under serious conditions.
In response to the above problems, more effective radical-ability measure is had no in industry at present, for the consistency problem of substrate, is led to
It can often take and increase bottom antireflective coating (BARC) in photoresist bottom or increase reflection coating provided at the top of photoresist
(TARC) mode is improved, but this greatly improves production cost.And the problem of to tunneling effect, mainly by difference
Product implant angle and Implantation Energy debugged with it is being optimal as a result, this dragged slowly significantly new product development into
Degree, while improving engineer's human cost etc..
Presence in view of the above problems, the present invention propose a kind of manufacturing method of semiconductor devices, as shown in Fig. 2, mainly
The following steps are included:
Step S1, provides semiconductor substrate, is formed with bulge-structure on the surface of the semiconductor substrate；
Step S2 is handled using the surface to the semiconductor substrate containing oxygen plasma, in the semiconductor
The surface of substrate forms coarse oxide layer.
In conclusion the manufacturing method of the present invention is handled substrate surface by plasma, to serve as a contrast in semiconductor
The surface at bottom forms coarse oxide layer, wherein the coarse oxide layer can make mask layer (such as photoresist) in substrate surface
Flowing velocity it is opposite slow down, at the high and low fall of bulge-structure and substrate surface between such as thickness of the mask layer of photoresist
Difference reduce, and then improve mask layer (such as photoresist) to the consistency of the feedback of exposure capability, improve the source being subsequently formed
Pole/drain electrode critical size consistency.
In the following, being described in detail with reference to manufacturing method of the Fig. 3 to semiconductor devices of the invention, wherein Fig. 3 shows this
The process flow chart of the manufacturing method of the semiconductor devices of invention another embodiment.
As an example, the manufacturing method of semiconductor devices of the invention the following steps are included:
Firstly, executing step S11, semiconductor substrate is provided, is formed with bulge-structure on the surface of the semiconductor substrate.
Specifically, the constituent material of semiconductor substrate can using undoped monocrystalline silicon, doped with impurity monocrystalline silicon,
Silicon (SSOI) is laminated on silicon-on-insulator (SOI), insulator, SiGe (S-SiGeOI), germanium on insulator are laminated on insulator
SiClx (SiGeOI) and germanium on insulator (GeOI) etc..As an example, in the present embodiment, the constituent material of semiconductor substrate
Select monocrystalline silicon.
The semiconductor substrate can also be P-type semiconductor substrate or N-type semiconductor substrate, such as N-type high tension apparatus
It then may be selected to use P-type semiconductor substrate, and p-type high tension apparatus then may be selected to use N-type semiconductor substrate, in the present embodiment,
The semiconductor substrate is P-type semiconductor substrate.
Illustratively, it can also be formed with various well regions in the semiconductor substrate, and in the semiconductor substrate can be with
It is provided with fleet plough groove isolation structure, to define active area.
Illustratively, bulge-structure, the bulge-structure and semiconductor substrate are also formed on the surface of semiconductor substrate
Surface between constitute form high and low fall, which can be any be formed in well known to those skilled in the art and partly leads
The structure with certain altitude on body substrate surface, in the present embodiment, the bulge-structure is to be formed in semiconductor substrate table
Gate structure on face, the gate structure may include the gate dielectric and grid layer set gradually from bottom to top.
In one example, for high tension apparatus, such as LDMOS device, it is also formed with drift region in the semiconductor substrate,
There is different conduction types according to drift region described in the type of specific LDMOS device, for example, if LDMOS device is N-type
LDMOS device, then drift region is N-type drift region, if LDMOS device is p-type LDMOS device, drift region is P drift area.
In general, the doping concentration of drift region is lower, is lower than the doping concentration of source electrode and drain electrode, is equivalent in source electrode
A resistive formation is formed between drain electrode, can be improved breakdown voltage, and reduce the parasitic capacitance between source electrode and drain electrode, has
Conducive to raising frequency characteristic.
Illustratively, the bulge-structure is gate structure, which can be with drift region described in covering part
Surface is using as field plate.
In one embodiment, gate dielectric may include traditional dielectric substance such as with electric medium constant from big
Oxide, nitride and the nitrogen oxides of the silicon of about 4 to about 20 (true aerial surveties), alternatively, gate dielectric may include
With the usual compared with high dielectric constant dielectric substance of electric medium constant from about 20 at least about 100.This higher electricity
Dielectric constant electrolyte can include but is not limited to: hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs) and zirconium titanium
Lead plumbate (PZTs).Grid layer is made of polycrystalline silicon material, and metal, metal nitride, metal silicide or class generally can also be used
Material like compound as grid layer, in the present embodiment, the material of the grid layer is preferably comprised polysilicon.
In one example, the bulge-structure of multiple such as gate structures can also be set on a semiconductor substrate.
The gate structure can be formed by any suitable method well known to those skilled in the art, do not done herein superfluous
It states.
In one example, clearance wall is formed on the side wall of the gate structure.The clearance wall can for silica,
A kind of or their combinations are constituted in silicon nitride, silicon oxynitride.
Then, execute step S12, handled using the surface to the semiconductor substrate containing oxygen plasma, with
The surface of the semiconductor substrate forms coarse oxide layer.
Illustratively, described to be generated containing oxygen plasma by the mixed gas of rare gas and oxygen-containing gas.
Wherein, the rare gas may include at least one of He, Ne, Ar, Kr and Xe, and the oxygen-containing gas can be with
It is mainly Ar with the rare gas in the present embodiment including at least one of oxygen, ozone and oxynitrides gas,
Oxygen-containing gas is O2。
Illustratively, the oxygen plasma that contains is weak plasma, which has lower energy, only
Slighter is modified the surface of semiconductor substrate, can be by making plasma generating apparatus have low radio-frequency power
And the flow of low reaction gas, to generate weak plasma, wherein half-and-half led using weak plasma is only slighter
The surface of body substrate is modified, and is conducive to the surface subsequently through annealing repairing semiconductor substrate.
In one example, in plasma to the surface of semiconductor substrate in the process of processing, by rare gas
The plasma of generation carries out ion bombardment to semiconductor substrate surface, forms rough surface, and is partly led by oxygen-containing gas oxidation
The surface of body substrate, and form coarse oxide layer.
The step can carry out in semiconductor etching device, and any model well known to those skilled in the art can be used
Etching apparatus, can also others can generate plasma equipment in carry out, in the present embodiment, mainly in semiconductor
For the method handled in etching apparatus substrate surface.
In one example, semiconductor substrate is placed in consersion unit, such as be placed in etching apparatus, Xiang Fanying
Ar and O are passed through in apparatus cavity2, Ar and O2It generates weak plasma to react with the surface of semiconductor substrate, for example, Ar plasma
Ion bombardment is carried out to the surface of semiconductor substrate, and obtains rough surface, and O2It reacts to be formed with the surface of semiconductor substrate
Coarse oxide layer.
Weak plasma can be formed by controlling the technological parameter of corona treatment, illustratively, can made dilute
There is gas that there is low flow, for example, the range of flow of rare gas (such as Ar and/or He) is 100sccm-150sccm, institute
The range of flow for stating oxygen-containing gas (such as oxygen) is 30-70sccm, uses lower top electrode radio-frequency power, such as top electrode
Radio frequency power range is 100W~200W, for example, 120W, 150W, 180W, 200W, lower electrode power (Bottom Power) model
It encloses for 30-60W.
Illustratively, the thickness of the coarse oxide layer of generation can also be controlled by the time of control corona treatment
Degree, such as the time range containing oxygen plasma treatment are 30s~45s.
In one example, the coarse oxide layer of formation has very thin thickness, for example, the coarse oxidation
The thickness range of layer can be 20 angstroms~30 angstroms.
Then, step S13 is executed, is annealed to the surface of the semiconductor substrate, with the smooth semiconductor substrate
Surface, and form amorphous material layer between semiconductor substrate and the coarse oxide layer.
Specifically, the annealing can be it is well known to those skilled in the art it is any it is suitable being capable of the smooth semiconductor
The annealing way of substrate surface, the annealing are carried out for semiconductor substrate surface segment thickness.
In one example, the semiconductor substrate is silicon substrate, and the amorphous material layer includes amorphous silicon.
Illustratively, the annealing can be laser annealing, and in the present embodiment, the laser annealing is preferably quasi-molecule
Laser annealing (Excimer laser annealing, abbreviation ELA).
Wherein, quasi-molecule laser annealing handles semiconductor substrate surface, repairing semiconductor substrate surface it is equal from
Son damage, while it is co-melting to form micro- part to semiconductor substrate surface, wherein micro- part refers to that semiconductor substrate surface is less than
1 micron of region, and when the semiconductor substrate is monocrystalline silicon, by quasi-molecule laser annealing, semiconductor substrate surface by
Monocrystalline is cooled into the amorphous silicon (namely amorphous silicon) without fixed crystal orientation to the silicon partial melting of (1,1,0) later, is put down
Sliding surface, wherein it is relatively sharp that abovementioned steps plasma handles the rough surface that substrate surface obtains, and this is sharp
Rough surface the electric leakage performance of device is adversely affected, therefore, using laser annealing to the surface of semiconductor substrate into
Row is appropriate smooth, for example, being smoothly slightly the smooth surface with similar arc-shaped protrusion by sharp rough surface, this is smooth
Surface afterwards retains a degree of roughness, to be conducive to form the good mask layer of the thickness uniformity in the next steps
(such as photoresist).
In one example, the light source of the quasi-molecule laser annealing can be XeCl, or other suitable light
Source, laser are ultraviolet light, such as wavelength is the ultraviolet light of 308nm, and the burst length is, for example, 30ns~150ns, preferably
150ns, laser energy density (ED) range are 0-3J/cm2, annealing time range is 60s~200s, such as is preferably
120s。
After quasi-molecule laser annealing, semiconductor substrate obtains smooth surface, and in semiconductor substrate and described coarse
Oxide layer between form amorphous material layer, and then avoid the generation of tunneling effect, while covering of being subsequently formed can be improved
Adhesiveness between film layer (such as photoresist) and semiconductor substrate.
Then, step S14 is executed, mask layer is formed, is tied with covering surface and the protrusion of the semiconductor substrate
Structure.
Illustratively, the mask layer includes photoresist layer, or others can be coated for example, by spin coating proceeding
Mask layer on semiconductor substrate surface.
In one example, photoresist layer is formed on the surface of semiconductor substrate by spin coating proceeding, for example, photoresist is through spray head
The center of semiconductor substrate is dripped to, the photoresist of liquid passes through flowing covering entire half in high-speed rotating semiconductor substrate later
The surface of conductor substrate, and since the surface in semiconductor substrate is formed with coarse oxide layer, photoresist is served as a contrast in semiconductor
Flowing velocity on bottom surface slows down, and then the height between bulge-structure (such as gate structure) and semiconductor substrate surface is low
Poor intersection, photoresist thickness relative different reduce, thus avoid because thickness it is inconsistent caused by exposure energy feedback not
Consensus, and then improve the dimensional uniformity of source electrode and drain electrode being subsequently formed, at the same can also increase semiconductor substrate and
Adhesiveness between photoresist.
It is noted that could be formed with multiple gate structures on a semiconductor substrate, in each gate structure two sides
Semiconductor substrate in can form source electrode and drain electrode, therefore, multiple source electrode and drain electrodes can be formed on a semiconductor substrate.
Then, step S15 is executed, the mask layer is patterned, to form opening, the opening dew in the mask layer
Make a reservation for be formed the region of source electrode and drain electrode in the semiconductor substrate out.
In one example, when the mask layer is photoresist layer, photoetching process can be used and pattern the mask layer, with
Opening is formed in the mask layer, the opening exposes the region for making a reservation for be formed source electrode and drain electrode in the semiconductor substrate.
Wherein, photoetching process includes the steps that being exposed photoresist layer and developing.
Then, step S16 is executed, using the mask layer as exposure mask, source and drain ion implanting is executed, in the semiconductor substrate
Form source electrode and drain electrode.
The source and drain ion implanting can be technique well known to those skilled in the art, wherein according to the predetermined device formed
Type selection ion implanting impurity type, such as it is predetermined form N-type source and drain electrode, then ion implanting uses N
Type impurity, such as one of phosphorus and arsenic, if predetermined form p-type source electrode and drain electrode, ion implanting is adulterated miscellaneous using p-type
Matter, such as boron.
Then, annealing process can also be carried out, illustratively, annealing can be used well known to those skilled in the art any
Annealing method, including but not limited to rapid thermal annealing, furnace anneal, peak value annealing, laser annealing etc., for example, carry out
Rapid thermal annealing process is activated the doping in regions and source/drain using 900 to 1050 DEG C of high temperature, and repaired simultaneously
Mend the lattice structure for the semiconductor substrate surface being damaged in each ion implantation technology.In addition, also visible product demand and function
Property is considered, and lightly doped drain (LDD) is separately respectively formed between regions and source/drain and each grid.
Finally, executing step S17, the mask layer is removed.
Illustratively, when the mask layer is photoresist layer, then such as method of ashing or wet-cleaning can be used and go
Except the photoresist layer, which can use SPM solution, include sulfuric acid and hydrogen peroxide in SPM solution.
Later, it is also an option that property to semiconductor substrate carry out wet-cleaning the step of, to remove semiconductor substrate table
The impurity in face, wet-cleaning can remove coarse oxide layer, which can use hydrofluoric acid solution, such as buffer
Oxide etching agent (buffer oxide etchant (BOE)) or hydrofluoric acid buffer solution (buffer solution of
Hydrofluoric acid (BHF)) or diluted hydrofluoric acid solution.
Certainly under the premise of not influencing device function, the coarse oxide layer can also be retained.
So far the explanation of the committed step of the manufacturing method of semiconductor devices of the invention is completed, wherein for complete
The step of element manufacturing also needs other, this will not be repeated here.It is noted that semiconductor devices of the invention can be ability
High tension apparatus known to field technique personnel, such as LDMOS device or VDMOS device etc., are also possible to the cmos device of standard
Or other devices.
In conclusion the manufacturing method of the present invention is handled substrate surface by plasma, to serve as a contrast in semiconductor
The surface at bottom forms coarse oxide layer, wherein the coarse oxide layer can make mask layer (such as photoresist) in substrate surface
Speed it is opposite slow down, the mask layer of such as photoresist at bulge-structure (such as gate structure) and the high and low fall of substrate surface
Thickness between difference reduce, and then improve mask layer (such as photoresist) to the consistency of the feedback of exposure capability, improve shape
At source/drain critical size consistency, while also adding between mask layer (such as photoresist) and semiconductor substrate
Adhesiveness, and by the surface of annealing process (such as quasi-molecule laser annealing) processing semiconductor substrate, obtain smooth surface
While, amorphous material layer (such as amorphous silicon) is formd, and then avoid the generation of tunneling effect, ensure that mask layer
With the generation that tunneling effect is also avoided while the adhesiveness of semiconductor substrate, in addition, method of the invention is simple to operation,
Production cost is low, without excessive human cost is consumed, finally improves the performance and yield of device.
Embodiment two
The present invention also provides a kind of semiconductor devices that the method using in previous embodiment one prepares.
As in example, the semiconductor devices includes: semiconductor substrate.
Specifically, the constituent material of semiconductor substrate can using undoped monocrystalline silicon, doped with impurity monocrystalline silicon,
Silicon (SSOI) is laminated on silicon-on-insulator (SOI), insulator, SiGe (S-SiGeOI), germanium on insulator are laminated on insulator
SiClx (SiGeOI) and germanium on insulator (GeOI) etc..As an example, in the present embodiment, the constituent material of semiconductor substrate
Select monocrystalline silicon.
The semiconductor substrate can also be P-type semiconductor substrate or N-type semiconductor substrate, such as N-type high tension apparatus
It then may be selected to use P-type semiconductor substrate, and p-type high tension apparatus then may be selected to use N-type semiconductor substrate, in the present embodiment,
The semiconductor substrate is P-type semiconductor substrate.
Illustratively, it can also be formed with various well regions in the semiconductor substrate, and in the semiconductor substrate can be with
It is provided with fleet plough groove isolation structure, to define active area.
Illustratively, bulge-structure, the bulge-structure and semiconductor substrate are also formed on the surface of semiconductor substrate
Surface between constitute form high and low fall, which can be any be formed in well known to those skilled in the art and partly leads
The structure with certain altitude on body substrate surface, in the present embodiment, the bulge-structure is to be formed in semiconductor substrate table
Gate structure on face, the gate structure may include the gate dielectric and grid layer set gradually from bottom to top.
In one example, for high tension apparatus, such as LDMOS device, it is also formed with drift region in the semiconductor substrate,
There is different conduction types according to drift region described in the type of specific LDMOS device, for example, if LDMOS device is N-type
LDMOS device, then drift region is N-type drift region, if LDMOS device is p-type LDMOS device, drift region is P drift area.
In general, the doping concentration of drift region is lower, is lower than the doping concentration of source electrode and drain electrode, is equivalent in source electrode
A resistive formation is formed between drain electrode, can be improved breakdown voltage, and reduce the parasitic capacitance between source electrode and drain electrode, has
Conducive to raising frequency characteristic.
Illustratively, the bulge-structure is gate structure, which can be with drift region described in covering part
Surface is using as field plate.
In one embodiment, gate dielectric may include traditional dielectric substance such as with electric medium constant from big
Oxide, nitride and the nitrogen oxides of the silicon of about 4 to about 20 (true aerial surveties), alternatively, gate dielectric may include
With the usual compared with high dielectric constant dielectric substance of electric medium constant from about 20 at least about 100.This higher electricity
Dielectric constant electrolyte can include but is not limited to: hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs) and zirconium titanium
Lead plumbate (PZTs).Grid layer is made of polycrystalline silicon material, and metal, metal nitride, metal silicide or class generally can also be used
Material like compound as grid layer, in the present embodiment, the material of the grid layer is preferably comprised polysilicon.
In one example, the bulge-structure of multiple such as gate structures can also be set on a semiconductor substrate.
In one example, clearance wall is formed on the side wall of the gate structure.The clearance wall can for silica,
A kind of or their combinations are constituted in silicon nitride, silicon oxynitride.
In one example, coarse oxide layer is formed on the surface of the semiconductor substrate.The coarse oxidation
The material of layer can be silica, silicon oxynitride etc..
In one example, the coarse oxide layer of formation has very thin thickness, for example, the coarse oxidation
The thickness range of layer can be 20 angstroms~30 angstroms.
Illustratively, semiconductor devices further includes that the nothing being formed between semiconductor substrate and the coarse oxide layer is determined
Shape material layer.
In one example, the semiconductor substrate is silicon substrate, and the amorphous material layer includes amorphous silicon.
Wherein, the surface of semiconductor substrate is smooth surface, and between semiconductor substrate and the coarse oxide layer
It is formed with amorphous material layer, and then avoids the generation of tunneling effect.
In one example, source electrode and drain electrode is respectively formed in the semiconductor substrate of the gate structure two sides.
The source electrode and it is described drain electrode have and the identical conduction type in the drift region 101, for example, the drift region
For N-type drift region, it can also be that n-type doping ion is heavily doped that the drain electrode and the source electrode, which then can be N-type source and drain electrode,
Miscellaneous source electrode and drain electrode.
And since semiconductor device surface of the invention is formed with coarse oxide layer, can improve source electrode and
The consistency of drain electrode critical size.
Since semiconductor devices of the invention is prepared using the method for aforementioned implementation one, have and aforementioned implementation
One identical advantage.
Embodiment three
The present invention also provides a kind of electronic devices, including semiconductor devices described in embodiment two, the semiconductor device
Part is prepared according to one the method for embodiment.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, Digital Frame, camera, video camera, recording pen, MP3, MP4, PSP is set
It is standby, it can also be any intermediate products including circuit.The electronic device of the embodiment of the present invention, due to having used above-mentioned semiconductor
Device, thus there is better performance.
Wherein, Fig. 4 shows the example of mobile phone handsets.Mobile phone handsets 300, which are equipped with, to be included in shell 301
Display portion 302, operation button 303, external connection port 304, loudspeaker 305, microphone 306 etc..
Wherein the mobile phone handsets include semiconductor devices described in embodiment two, and the semiconductor devices includes:
Semiconductor substrate is formed with bulge-structure on the surface of the semiconductor substrate；
Coarse oxide layer is formed on the surface of the semiconductor substrate.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (14)
1. a kind of manufacturing method of semiconductor devices characterized by comprising
Semiconductor substrate is provided, is formed with bulge-structure on the surface of the semiconductor substrate；
It is handled using the surface to the semiconductor substrate containing oxygen plasma, in the surface shape of the semiconductor substrate
At coarse oxide layer.
2. manufacturing method as described in claim 1, which is characterized in that further include following step after forming the oxide layer
It is rapid: anneal to the surface of the semiconductor substrate, with the surface of the smooth semiconductor substrate, and in semiconductor substrate and
Amorphous material layer is formed between the coarse oxide layer.
3. manufacturing method as claimed in claim 2, which is characterized in that described to be annealed into quasi-molecule laser annealing.
4. manufacturing method as claimed in claim 2, which is characterized in that the semiconductor substrate is silicon substrate, described amorphous
Material layer includes amorphous silicon.
5. manufacturing method as described in claim 1, which is characterized in that the bulge-structure is gate structure.
6. manufacturing method as described in claim 1, which is characterized in that after forming the coarse oxide layer further include with
Lower step:
Formed mask layer, with cover the semiconductor substrate surface and the bulge-structure.
7. manufacturing method as claimed in claim 6, which is characterized in that after forming the mask layer further include following step
It is rapid:
The mask layer is patterned, to form opening in the mask layer, the opening is exposed pre- in the semiconductor substrate
It is shaped as the region of source electrode and drain electrode；
Using the mask layer as exposure mask, source and drain ion implanting is executed, to form source electrode and drain electrode in the semiconductor substrate；
Remove the mask layer.
8. manufacturing method as described in claim 1, which is characterized in that it is described containing oxygen plasma by rare gas and oxygenous
The mixed gas of body generates, wherein the plasma generated by the rare gas to the semiconductor substrate surface carry out from
Son bombardment, forms rough surface, and the surface of the semiconductor substrate is aoxidized by the oxygen-containing gas, and is formed described coarse
Oxide layer.
9. manufacturing method as claimed in claim 8, which is characterized in that the range of flow of the rare gas be 100sccm~
150sccm, the range of flow of the oxygen-containing gas are 30sccm~70sccm, top electrode radio frequency power range be 100W~
200W, lower electrode power range are 30W~60W.
10. a kind of semiconductor devices characterized by comprising
Semiconductor substrate is formed with bulge-structure on the surface of the semiconductor substrate；
Coarse oxide layer is formed on the surface of the semiconductor substrate.
11. semiconductor devices as claimed in claim 10, which is characterized in that further include: it is formed in semiconductor substrate and described
Amorphous material layer between coarse oxide layer.
12. semiconductor devices as claimed in claim 11, which is characterized in that the semiconductor substrate is silicon substrate, the nothing
Amorphous layer includes amorphous silicon.
13. semiconductor devices as claimed in claim 10, which is characterized in that the bulge-structure is gate structure, described
Source electrode and drain electrode is respectively formed in the semiconductor substrate of gate structure two sides.
14. a kind of electronic device, which is characterized in that the electronic device includes partly leading as described in one of claim 10 to 13
Body device.
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| CN110148556A (en) * | 2019-05-20 | 2019-08-20 | 上海华虹宏力半导体制造有限公司 | A method of improving photoetching in semiconductor manufacture glue and falls glue |
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| US5536534A (en) * | 1994-03-25 | 1996-07-16 | Hyundai Electronics Industries Co. Ltd. | Method and apparatus for coating photoresist |
| US20020004300A1 (en) * | 1999-08-09 | 2002-01-10 | Marina V. Plat | Ultra-thin resist coating qualityby by increasing surface roughness of the substrate |
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