CN102569070B - Method for manufacturing MIS (Metal-Insulator-Semiconductor) capacitor - Google Patents
Method for manufacturing MIS (Metal-Insulator-Semiconductor) capacitor Download PDFInfo
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- CN102569070B CN102569070B CN201210075130.2A CN201210075130A CN102569070B CN 102569070 B CN102569070 B CN 102569070B CN 201210075130 A CN201210075130 A CN 201210075130A CN 102569070 B CN102569070 B CN 102569070B
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Abstract
The invention provides a method for manufacturing an MIS (Metal-Insulator-Semiconductor) capacitor, which can effectively reduce the thickness of a film interface layer by etching a silicon island on an SOI (Silicon On Insulator) substrate and removing an oxide layer on the surface of the silicon island by adopting HF. The method comprises the following steps of: firstly, growing a thin oxynitride passivation layer on the Si surface by using a plasma atomic layer deposition method and adopting in-situ O2 and NH3 plasma so as to restrict the growth of the interface layer; and secondly, growing an HfLaO dielectric film by using a plasma growth manner, carrying out oxygen plasma aftertreatment on the HfLaO dielectric film in situ to reduce oxygen vacancy in the film; and thirdly, processing photoresist by using a chlorobenzene solution, so that burrs on the edge of the photoresist can be modified to ensure that the subsequent metal lifting process is simpler and more accurate. The MIS capacitor manufactured by adopting the method disclosed by the invention is beneficial to reduction of the quantity of additional interface layers, thinning of thickness of each interface layer, reduction of roughness of the interface layers, restriction of element dispersion between the substrate and the film and reduction of equivalent gate oxide thickness, and thus the electric property of the MIS capacitor is effectively improved.
Description
Technical field
The invention belongs to microelectronics and solid electronics technical field, particularly relate to a kind of manufacture method of MIS electric capacity.
Background technology
Along with the development of large-scale integrated circuit technique, as the metal of si-substrate integrated circuit core devices.The characteristic size of oxide semiconductor field effect transistor (MOSFET) respects Moore's Law always and constantly reduces.But metal-oxide-semiconductor grid medium thickness is more and more less, close to its limit.When the gate medium of silicon dioxide is below 10nm thickness (manufacturing limit of silicon materials is commonly considered as 10 nano-scale linewidths), will occur that tunnel current increases, the problems such as needle pore defect and performance failure less reliable.In order to address these problems, some integrated circuits research maker has started to explore, and adopts high-k gate dielectric material to replace SiO
2show good effect, the 45nm height k process technique of Intel Company is exactly good example, has led people to conduct extensive research high-K gate dielectric material.
The burning the hotest high-k gate dielectric material of current research is exactly HfO
2, its dielectric constant is 25 ~ 40, and energy gap is 5.7eV, and is all greater than 1.5eV with the conduction band valence band offset value of Si, and Heat stability is good, 500 DEG C.That another is very promising is exactly La
2o
3, its dielectric constant is 30, and energy gap is 4.0eV, has contacted good thermal stability with silicon substrate.And a kind of special construction is bianry alloy gate medium stacking provisions in high-k gate dielectric research, its component does not have strict metering ratio, but it combines the advantage of two oxides, the interface cohesion of they and silicon very good, interfacial state is quite low, add that the energy gap of oxide layer is large, can tunnelling current be reduced.
Silicon-on-insulator (SOI) technology be at the bottom of top layer silicon and backing between introduce one deck and bury oxide layer.By forming semiconductive thin film on insulator, SOI material is provided with the incomparable advantage of body silicon: the medium isolation that can realize components and parts in integrated circuit, completely eliminates the parasitic latch-up in Bulk CMOS circuit; The integrated circuit adopting this material to make also has that parasitic capacitance is little, integration density is high, speed is fast, technique is simple, short-channel effect is little and be specially adapted to the advantages such as low voltage and low power circuits, therefore can say that SOI will likely become the low pressure of deep-submicron, the mainstream technology of low power consumption integrated circuit.In addition, ultra-thin SiO
2also there are stable reliability and uniformity etc. in gate dielectric layer.
In the method for the high-quality High-K dielectric layer of preparation, plasma enhanced atomic layer deposition (PEALD) is all well and good selection.The manufacture method of existing gate medium directly on SOI, makes a MOS capacitor, but owing to there is oxygen buried layer in SOI material, if directly at material both sides long electrode, at least 3 additional boundary layers can be introduced, these boundary layers can store electric charge, have impact on gate medium electric property widely.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of manufacture method of MIS electric capacity, for solve the additional interface layer introduced in MIS electric capacity preparation process in prior art too much and additional interface layer blocked up and affect the problem of its electric property.
For achieving the above object and other relevant objects, the invention provides a kind of manufacture method of MIS electric capacity, at least comprise step: 1) SOI substrate is provided, the top layer silicon of described SOI substrate etches multiple separate silicon island; 2) remove the oxide layer on each this surface, silicon island, then form oxynitrides passivation layer on each this surface, silicon island; 3) using plasma enhancement mode atomic layer deposition method forms HfLaO dielectric film in described oxynitrides passivation layer surface, and carries out oxygen plasma treatment to described HfLaO dielectric film; 4) HfLaO dielectric film island is etched at described HfLaO dielectric film; 5) forming photoresist in described HfLaO dielectric film island and surface, described silicon island, and adopt chlorobenzene solution to soak described photoresist, then the litho pattern that the position be formed in for preparing electrode has window being developed to described photoresist; 6) in described litho pattern forming metal layer on surface, then adopt metal to lift off technique and form the first electrode and the second electrode respectively at described HfLaO dielectric film island and surface, silicon island, and annealing is to make described first electrode and the second electrode form ohmic contact with described HfLaO dielectric film island and silicon island respectively.
In the manufacture method of MIS electric capacity of the present invention, described step 3) also comprise described HfLaO dielectric film is placed in N
2the step of middle annealing, wherein, annealing temperature is 400 ~ 600 DEG C, and annealing time is 30 ~ 90s.
In the manufacture method of MIS electric capacity of the present invention, described step 2) in, described in the HF aqueous corrosion that employing volume ratio is 0.5% ~ 1.5%, surface, silicon island is to remove described oxide layer.
In the manufacture method of MIS electric capacity of the present invention, described step 2) in, the SOI substrate with silicon island is placed in ALD reaction chamber, first passes into O to described ALD reaction chamber
2and add that RF power processes SOI substrate to produce O plasma, then original position passes into NH to described ALD reaction chamber
3, then add that RF power processes described Si substrate or SOI substrate to produce N, H plasma, to form oxynitrides passivation layer on its surface.
In the manufacture method of MIS electric capacity of the present invention, described step 3) in, with [(CH
3) (C
2h
5) N]
4hf is as HfO
2precursors, La [N (TMS)
2]
3as La
2o
3precursors, O
2as oxidant, using plasma enhancement mode atomic layer deposition method forms HfLaO dielectric film in described oxynitrides passivation layer surface.
In the manufacture method of MIS electric capacity of the present invention, described step 4) in, first make litho pattern, then adopt HfLaO dielectric film described in the HF solution etches of 1% ~ 3% to surface, described silicon island to form described HfLaO dielectric film island.
In the manufacture method of MIS electric capacity of the present invention, described step 5) in, the time adopting chlorobenzene solution to soak is 4 ~ 6min.
In the manufacture method of MIS electric capacity of the present invention, described step 6) in, adopt magnetron sputtering method to be formed successively in described litho pattern surface Ti layer that thickness is 5 ~ 15nm and thickness are that the Pt layer of 50 ~ 150nm is to form described metal level.
In the manufacture method of MIS electric capacity of the present invention, described step 6) in, be the N of 15 ~ 25: 1 in volume ratio
2, H
2anneal in gaseous mixture, annealing temperature is 400 ~ 500 DEG C, and annealing time is 2 ~ 4min, forms ohmic contact respectively to make described first electrode and the second electrode with described HfLaO dielectric film island and silicon island.
As mentioned above, the manufacture method of MIS electric capacity of the present invention, has following beneficial effect: in SOI substrate, etch silicon island, adopts HF to remove the oxide layer on surface, silicon island, can effectively reduce film interface layer thickness.Utilize Plasma-Atomic deposition method, adopt original position O
2, NH
3the technology on plasma treatment Si surface, between HfLaO dielectric film and Si, grow the oxynitrides passivation layer that one deck is very thin, this passivation layer can suppress the growth of boundary layer.Then use plasma-grown mode to grow HfLaO dielectric film, and original position carry out oxygen plasma post-treatment to described HfLaO dielectric film, reduces the Lacking oxygen in film.Adopting chlorobenzene solution to process the photoresist lifting off technique for carrying out metal, the burr at photoresist edge can be modified, make photoresist edge round and smooth, thus also make metal below lift off technique more simply and accurately.The MIS electric capacity adopting this method to prepare is conducive to the roughness reducing the quantity of additional interface layer, thinning interfacial layer thickness and reduce boundary layer, be conducive to suppressing the Elements Diffusion between substrate and film and reducing equivalent gate oxide thickness, effectively can improve the electric property of MIS electric capacity.
Accompanying drawing explanation
Fig. 1 is shown as the manufacture method Making programme schematic diagram of MIS electric capacity of the present invention.
Fig. 2 ~ Fig. 3 is shown as the manufacture method step 1 of MIS electric capacity of the present invention) structural representation that presents.
Fig. 4 is shown as the manufacture method step 2 of MIS electric capacity of the present invention) structural representation that presents.
Fig. 5 is shown as the manufacture method step 3 of MIS electric capacity of the present invention) structural representation that presents.
Fig. 6 is shown as the manufacture method step 4 of MIS electric capacity of the present invention) structural representation that presents.
Fig. 7 is shown as the manufacture method step 5 of MIS electric capacity of the present invention) structural representation that presents.
Fig. 8 ~ Fig. 9 is shown as the manufacture method step 6 of MIS electric capacity of the present invention) structural representation that presents.
Element numbers explanation
S1-S6 step 1) ~ step 6)
101 ~ 103 SOI substrate
103 top layer silicon
104 silicon island
105 oxynitrides passivation layers
106 HfLaO dielectric films
107 HfLaO dielectric film islands
108 litho patterns
109 Ti layers
110 Pt layers
111 first electrodes
112 second electrodes
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to Fig. 1 to Fig. 9.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
As shown in the figure, the invention provides a kind of manufacture method of MIS electric capacity, it is characterized in that, at least comprise step:
Refer to S1 and Fig. 2 in Fig. 1 ~ Fig. 3, as shown in the figure, first carry out step 1), a SOI substrate 101 ~ 103 is provided, the top layer silicon 103 of described SOI substrate 101 ~ 103 etches multiple separate silicon island 104.
In the present embodiment, after litho pattern is made on described SOI substrate 101 ~ 103 surface, be placed in RIE etch chamber, adopt SF6 as corrosive agent, described SOI top layer silicon 103 to oxygen buried layer is etched, to form multiple separate silicon island 104 by reactive ion etching (RIE) method.Certainly, in other embodiments, other etching method also can be adopted to etch described SOI substrate 101 ~ 103.
Refer to S2 and Fig. 4 in Fig. 1, as shown in the figure, then carry out step 2), remove the oxide layer on each this surface, silicon island 104, then form oxynitrides passivation layer 105 on each this surface, silicon island 104.
Particularly, adopt surface, silicon island 104 described in the HF aqueous corrosion that volume ratio is 0.5% ~ 1.5% to remove described oxide layer.In the present embodiment, adopt 1% HF aqueous corrosion described in surface, silicon island 104 to remove described oxide layer.Due to SOI substrate 101 ~ 103 is cleaned or photoetching process in can again its surface produce SiO
2layer, SiO
2layer can have a strong impact on the reduction of interfacial layer thickness and leakage current, so adopt HF to remove surface oxide layer, effectively can reduce interfacial layer thickness herein.
After removing oxide layer, the SOI substrate 101 ~ 103 with silicon island 104 is placed in ALD reaction chamber, first passes into O to described ALD reaction chamber
2and add that RF power processes SOI substrate 101 ~ 103 to produce O plasma, then original position passes into NH to described ALD reaction chamber
3, then add that RF power processes the described SOI substrate 101 ~ 103 with silicon island 104 to produce N, H plasma, form oxynitrides passivation layer 105 with the surface in each this silicon island 104.This passivation layer effectively can suppress the growth of boundary layer.
Refer to S3 and Fig. 5 in Fig. 1, as shown in the figure, then carry out step 3), using plasma enhancement mode atomic layer deposition method forms HfLaO dielectric film 106 on described oxynitrides passivation layer 105 surface, and carries out oxygen plasma treatment to described HfLaO dielectric film 106.
In the present embodiment, SOI substrate 101 ~ 103 is placed in ALD reaction chamber, with [(CH
3) (C
2h
5) N]
4hf is as HfO
2precursors, La [N (TMS)
2]
3as La
2o
3precursors, O
2as oxidant, using plasma enhancement mode atomic layer deposition method forms HfLaO dielectric film 106 on described oxynitrides passivation layer 105 surface.
Also comprise after this step and described HfLaO dielectric film 106 is placed in N
2the step of middle annealing, wherein, annealing temperature is 400 ~ 600 DEG C, and annealing time is 30 ~ 90s.In the present embodiment, annealing temperature is 500 DEG C, and annealing time is 60s.This step can eliminate HfLaO dielectric film 106 put in internal stress and the defect of internal structure.
After annealing, the SOI substrate 101 ~ 103 with HfLaO dielectric film 106 is placed in ALD reaction chamber, and passes into O to described ALD reaction chamber
2, then add that RF power is to produce O plasma and original position processes described HfLaO dielectric film 106, to reduce the Lacking oxygen in described HfLaO dielectric film 106.Namely keep the state of ALD reaction chamber constant, pass into O to it
2, then add that RF power processes described HfLaO dielectric film 106 to produce O plasma, to reduce the Lacking oxygen in described HfLaO dielectric film 106.
Refer to S4 and Fig. 6 in Fig. 1, as shown in the figure, then carry out step 4), etch HfLaO dielectric film 107 at described HfLaO dielectric film 106.
Particularly, first make litho pattern, then adopt HfLaO dielectric film 106 described in the HF solution etches of 1% ~ 3% to surface, described silicon island 104 to form described HfLaO dielectric film 107, meanwhile, the extra-regional region that photoresist covers produces hydrophobic property due to the etching of HF solution.In the present embodiment, adopt 2% HF solution etches described in HfLaO dielectric film 106 to surface, described silicon island 104 to form described HfLaO dielectric film 107.
Refer to S5 and Fig. 7 in Fig. 1, as shown in the figure, first carry out step 5), photoresist is formed in described HfLaO dielectric film 107 and surface, described silicon island 104, and adopt chlorobenzene solution to soak described photoresist, then the litho pattern 108 that the position be formed in for preparing electrode has window is developed to described photoresist.
Particularly, the time adopting chlorobenzene solution to soak is 4 ~ 6min.In the present embodiment, the time adopting chlorobenzene solution to soak is 5min.Adopting chlorobenzene solution to process the photoresist lifting off technique for carrying out metal, the burr at photoresist edge can be modified, make photoresist edge round and smooth, thus also make metal below lift off technique more simply and accurately.
Refer to S6 and Fig. 8 in Fig. 1 ~ Fig. 9, as shown in the figure, first carry out step 6), in described litho pattern 108 forming metal layer on surface, then adopt metal to lift off technique and form the first electrode 111 and the second electrode 112 respectively at described HfLaO dielectric film 107 and surface, silicon island 104, and annealing is to make described first electrode 111 and the second electrode 112 form ohmic contact with described HfLaO dielectric film 107 and silicon island 104 respectively.
Particularly, magnetron sputtering method is adopted to form Ti layer 109 that thickness is 5 ~ 15nm successively in described litho pattern 108 surface and thickness is that the Pt layer 110 of 50 ~ 150nm is to form described metal level.Described metal level is contacted with described HfLaO dielectric film 107 and silicon island 104 respectively by the window of described litho pattern 108.Then acetone soln is adopted to soak the above-mentioned structure 8 ~ 16h with litho pattern 108, metal level on photoresist and photoresist is peeled off, last only retains metal structure corresponding to litho pattern 108 window the first electrode 111 and the second electrode 112 respectively as HfLaO dielectric film 107 and silicon island 104.After electrode is formed, be the N of 15 ~ 25: 1 in volume ratio
2, H
2anneal in gaseous mixture, annealing temperature is 400 ~ 500 DEG C, and annealing time is 2 ~ 4min, forms ohmic contact respectively to make described first electrode 111 and the second electrode 112 with described HfLaO dielectric film 107 and silicon island 104.
In the present embodiment, magnetron sputtering method is adopted to form Ti layer 109 that thickness is 10nm successively in described litho pattern 108 surface and thickness is that the Pt layer 110 of 100nm is to form described metal level.Described metal level is contacted with described HfLaO dielectric film 107 and silicon island 104 respectively by the window of described litho pattern 108.Then acetone soln is adopted to soak the above-mentioned structure 12h with litho pattern 108, metal level on photoresist and photoresist is peeled off, last only retains metal structure corresponding to the litho pattern 108 window electrode respectively as HfLaO dielectric film 107 and silicon island 104.After electrode is formed, be the N of 19: 1 in volume ratio
2, H
2anneal in gaseous mixture, annealing temperature is 450 DEG C, and annealing time is 3min, forms ohmic contact respectively to make described first electrode 111 and the second electrode 112 with described HfLaO dielectric film 107 and silicon island 104.
In sum, the manufacture method of MIS electric capacity of the present invention, etches silicon island in SOI substrate, adopts HF to remove the oxide layer on surface, silicon island, can effectively reduce film interface layer thickness.Utilize Plasma-Atomic deposition method, adopt original position O
2, NH
3the technology on plasma treatment Si surface, between HfLaO dielectric film and Si, grow the oxynitrides passivation layer that one deck is very thin, this passivation layer can suppress the growth of boundary layer.Then use plasma-grown mode to grow HfLaO dielectric film, and original position carry out oxygen plasma post-treatment to described HfLaO dielectric film, reduces the Lacking oxygen in film.Adopting chlorobenzene solution to process the photoresist lifting off technique for carrying out metal, the burr at photoresist edge can be modified, make photoresist edge round and smooth, thus also make metal below lift off technique more simply and accurately.The MIS electric capacity adopting this method to prepare is conducive to the roughness reducing the quantity of additional interface layer, thinning interfacial layer thickness and reduce boundary layer, be conducive to suppressing the Elements Diffusion between substrate and film and reducing equivalent gate oxide thickness, effectively can improve the electric property of MIS electric capacity.So the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (7)
1. a manufacture method for MIS electric capacity, is characterized in that, at least comprises step:
1) SOI substrate is provided, the top layer silicon of described SOI substrate etches multiple separate silicon island;
2) remove the oxide layer on each this surface, silicon island, then form oxynitrides passivation layer on each this surface, silicon island;
3) with [(CH
3) (C
2h
5) N]
4hf is as HfO
2precursors, La [N (TMS)
2]
3as La
2o
3precursors, O
2as oxidant, using plasma enhancement mode atomic layer deposition method forms HfLaO dielectric film in described oxynitrides passivation layer surface, then described HfLaO dielectric film is placed in N
2middle annealing, wherein, annealing temperature is 400 ~ 600 DEG C, and annealing time is 30 ~ 90s, finally carries out oxygen plasma treatment to described HfLaO dielectric film;
4) HfLaO dielectric film island is etched at described HfLaO dielectric film;
5) forming photoresist in described HfLaO dielectric film island and surface, described silicon island, and adopt chlorobenzene solution to soak described photoresist, then the litho pattern that the position be formed in for preparing electrode has window being developed to described photoresist;
6) in described litho pattern forming metal layer on surface, then adopt metal to lift off technique and form the first electrode and the second electrode respectively at described HfLaO dielectric film island and surface, silicon island, and annealing is to make described first electrode and the second electrode form ohmic contact with described HfLaO dielectric film island and silicon island respectively.
2. the manufacture method of MIS electric capacity according to claim 1, is characterized in that: described step 2) in, described in the HF aqueous corrosion that employing volume ratio is 0.5% ~ 1.5%, surface, silicon island is to remove described oxide layer.
3. the manufacture method of MIS electric capacity according to claim 1, is characterized in that: described step 2) in, the SOI substrate with silicon island is placed in ALD reaction chamber, first passes into O to described ALD reaction chamber
2and add that RF power processes SOI substrate to produce O plasma, then original position passes into NH to described ALD reaction chamber
3, then add that RF power processes described SOI substrate to produce N, H plasma, to form oxynitrides passivation layer on its surface.
4. the manufacture method of MIS electric capacity according to claim 1, it is characterized in that: described step 4) in, first make litho pattern, then adopt HfLaO dielectric film described in the HF solution etches of 1% ~ 3% to surface, described silicon island to form described HfLaO dielectric film island.
5. the manufacture method of MIS electric capacity according to claim 1, is characterized in that: described step 5) in, the time adopting chlorobenzene solution to soak is 4 ~ 6min.
6. the manufacture method of MIS electric capacity according to claim 1, it is characterized in that: described step 6) in, adopt magnetron sputtering method to be formed successively in described litho pattern surface Ti layer that thickness is 5 ~ 15nm and thickness are that the Pt layer of 50 ~ 150nm is to form described metal level.
7. the manufacture method of MIS electric capacity according to claim 1, is characterized in that: described step 6) in, be the N of 15 ~ 25: 1 in volume ratio
2, H
2anneal in gaseous mixture, annealing temperature is 400 ~ 500 DEG C, and annealing time is 2 ~ 4min, forms ohmic contact respectively to make described first electrode and the second electrode with described HfLaO dielectric film island and silicon island.
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| CN201210075130.2A CN102569070B (en) | 2012-03-20 | 2012-03-20 | Method for manufacturing MIS (Metal-Insulator-Semiconductor) capacitor |
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| CN102226270A (en) * | 2011-04-29 | 2011-10-26 | 中国科学院上海微系统与信息技术研究所 | Method for depositing gate dielectric, method for preparing MIS capacitor and MIS capacitor |
| CN102254821A (en) * | 2011-07-11 | 2011-11-23 | 中国科学院上海微系统与信息技术研究所 | Metal oxide semiconductor (MOS) capacitor based on silicon-on-insulator (SOI) material and method for making MOS capacitor |
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| CN102226270A (en) * | 2011-04-29 | 2011-10-26 | 中国科学院上海微系统与信息技术研究所 | Method for depositing gate dielectric, method for preparing MIS capacitor and MIS capacitor |
| CN102254821A (en) * | 2011-07-11 | 2011-11-23 | 中国科学院上海微系统与信息技术研究所 | Metal oxide semiconductor (MOS) capacitor based on silicon-on-insulator (SOI) material and method for making MOS capacitor |
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