CN102569070A - Method for manufacturing MIS (Metal-Insulator-Semiconductor) capacitor - Google Patents
Method for manufacturing MIS (Metal-Insulator-Semiconductor) capacitor Download PDFInfo
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- CN102569070A CN102569070A CN2012100751302A CN201210075130A CN102569070A CN 102569070 A CN102569070 A CN 102569070A CN 2012100751302 A CN2012100751302 A CN 2012100751302A CN 201210075130 A CN201210075130 A CN 201210075130A CN 102569070 A CN102569070 A CN 102569070A
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Abstract
The invention provides a method for manufacturing an MIS (Metal-Insulator-Semiconductor) capacitor, which can effectively reduce the thickness of a film interface layer by etching a silicon island on an SOI (Silicon On Insulator) substrate and removing an oxide layer on the surface of the silicon island by adopting HF. The method comprises the following steps of: firstly, growing a thin oxynitride passivation layer on the Si surface by using a plasma atomic layer deposition method and adopting in-situ O2 and NH3 plasma so as to restrict the growth of the interface layer; and secondly, growing an HfLaO dielectric film by using a plasma growth manner, carrying out oxygen plasma aftertreatment on the HfLaO dielectric film in situ to reduce oxygen vacancy in the film; and thirdly, processing photoresist by using a chlorobenzene solution, so that burrs on the edge of the photoresist can be modified to ensure that the subsequent metal lifting process is simpler and more accurate. The MIS capacitor manufactured by adopting the method disclosed by the invention is beneficial to reduction of the quantity of additional interface layers, thinning of thickness of each interface layer, reduction of roughness of the interface layers, restriction of element dispersion between the substrate and the film and reduction of equivalent gate oxide thickness, and thus the electric property of the MIS capacitor is effectively improved.
Description
Technical field
The invention belongs to microelectronics and solid electronics technical field, particularly relate to a kind of manufacture method of MIS electric capacity.
Background technology
Along with the continuous development of large-scale integrated circuit technique, as the metal of si-substrate integrated circuit core devices.The characteristic size of oxide semiconductor field effect transistor (MOSFET) is being observed Moore's Law always and is constantly being dwindled.Yet the metal-oxide-semiconductor grid medium thickness is more and more littler, near its limit.The gate medium of silicon dioxide is (manufacturing limit of silicon materials is commonly considered as 10 nano-scale linewidths) when 10nm thickness is following, tunnel current will occur and increase problems such as needle pore defect and performance failure reliability variation.In order to address these problems, some integrated circuit research makers have begun to explore, and adopt high-k gate dielectric material to replace SiO
2Shown good effect, the high k process technique of the 45nm of Intel Company is exactly good example, has led people that the high-K gate dielectric material has been carried out extensive studies.
The burning the hotest high-k gate dielectric material of research is exactly HfO at present
2, its dielectric constant is 25～40, energy gap is 5.7eV, and with the conduction band valence band offset value of Si all greater than 1.5eV, and Heat stability is good, 500 ℃.That another is very promising is exactly La
2O
3, its dielectric constant is 30, energy gap is 4.0eV, has contacted good thermal stability with silicon substrate.And a kind of special construction is a bianry alloy gate medium stacking provisions in the high-k gate dielectric research; Its component does not have strict metering ratio; But it has combined the advantage of two kinds of oxides, they with the interface of silicon combine very good, interfacial state is quite low; The energy gap that adds oxide layer is big, can reduce tunnelling current.
Silicon-on-insulator (SOI) technology is to have introduced one deck between at the bottom of top layer silicon and the backing to bury oxide layer.Through on insulator, forming semiconductive thin film, the SOI material had body silicon incomparable advantage: can realize the dielectric isolation of components and parts in the integrated circuit, thoroughly eliminate the parasitic latch-up in the body silicon CMOS circuit; The integrated circuit that adopts this material to process has also that parasitic capacitance is little, integration density is high, speed is fast, technology is simple, short-channel effect is little and is specially adapted to advantage such as low-voltage and low-power dissipation circuit, therefore we can say that SOI might become the low pressure of deep-submicron, the mainstream technology of low power consumption integrated circuit.In addition, ultra-thin SiO
2Gate dielectric layer also exists stable reliability and uniformity etc.
In the method for the high-quality High-K dielectric layer of preparation, plasma-enhanced ald (PEALD) is all well and good selection.The manufacture method of existing gate medium is directly on SOI, to make a mos capacitance device; But owing to have oxygen buried layer in the SOI material; If directly at material both sides long electrode then can introduce at least 3 additional boundary layers; These boundary layers can store charge, has influenced the gate medium electric property widely.
Summary of the invention
The shortcoming of prior art in view of the above; The object of the present invention is to provide a kind of manufacture method of MIS electric capacity, be used for solving prior art MIS electric capacity and prepare the additional interface layer of introducing in the process too much to reach the additional interface layer blocked up and influence the problem of its electric property.
For realizing above-mentioned purpose and other relevant purposes, the present invention provides a kind of manufacture method of MIS electric capacity, comprises step at least: 1) a SOI substrate is provided, on the top layer silicon of said SOI substrate, etches a plurality of separate silicon island; 2) remove the respectively oxide layer on this surface, silicon island, form oxynitrides passivation layer on this surface, silicon island respectively then; 3) using plasma enhancement mode atomic layer deposition method forms the HfLaO dielectric film in said oxynitrides passivation layer surface, and said HfLaO dielectric film is carried out oxygen plasma treatment; 4) etch HfLaO dielectric film island at said HfLaO dielectric film; 5) in said HfLaO dielectric film island and said silicon island surface form photoresist, and adopt chlorobenzene solution that said photoresist is soaked, then said photoresist is developed to be formed on the litho pattern that position that desire prepares electrode has window; 6) form metal level in said litho pattern surface; Adopt metal to lift separating process then and form first electrode and second electrode, and annealing is so that said first electrode and second electrode form ohmic contact with said HfLaO dielectric film island and silicon island respectively respectively at said HfLaO dielectric film island and surface, silicon island.
In the manufacture method of MIS electric capacity of the present invention, said step 3) also comprises said HfLaO dielectric film is placed N
2The step of middle annealing, wherein, annealing temperature is 400～600 ℃, annealing time is 30～90s.
In the manufacture method of MIS electric capacity of the present invention, said step 2) in, adopting volume ratio is that 0.5%～1.5% surface, the said silicon island of HF aqueous corrosion is to remove said oxide layer.
In the manufacture method of MIS electric capacity of the present invention, said step 2) in, the SOI substrate that will have the silicon island places the ALD reaction chamber, feeds O to said ALD reaction chamber earlier
2And adding that RF power handles the SOI substrate to produce the O plasma, original position feeds NH to said ALD reaction chamber then
3, add then RF power with produce N, the H plasma is handled said Si substrate or SOI substrate, to form the oxynitrides passivation layer on its surface.
In the manufacture method of MIS electric capacity of the present invention, in the said step 3), with [(CH
3) (C
2H
5) N]
4Hf is as HfO
2The reaction precursor body, La [N (TMS)
2]
3As La
2O
3The reaction precursor body, O
2As oxidant, using plasma enhancement mode atomic layer deposition method forms the HfLaO dielectric film in said oxynitrides passivation layer surface.
In the manufacture method of MIS electric capacity of the present invention, in the said step 4), make earlier litho pattern, adopt 1%～3% the said HfLaO dielectric film of HF solution etching to surface, said silicon island to form said HfLaO dielectric film island then.
In the manufacture method of MIS electric capacity of the present invention, in the said step 5), the time of adopting chlorobenzene solution to soak is 4～6min.
In the manufacture method of MIS electric capacity of the present invention, in the said step 6), adopt magnetron sputtering method to form Pt layer that Ti layer that thickness is 5～15nm and thickness is 50～150nm successively in said litho pattern surface to form said metal level.
In the manufacture method of MIS electric capacity of the present invention, in the said step 6), in volume ratio 15～25: 1 N
2, H
2Anneal in the gaseous mixture, annealing temperature is 400～500 ℃, and annealing time is 2～4min, so that said first electrode and second electrode form ohmic contact with said HfLaO dielectric film island and silicon island respectively.
As stated, the manufacture method of MIS electric capacity of the present invention has following beneficial effect: in the SOI substrate, etch the silicon island, adopt HF to remove the oxide layer on surface, silicon island, can reduce the film interface layer thickness effectively.Utilize the plasma Atomic layer deposition method, adopt original position O
2, NH
3The technology on Cement Composite Treated by Plasma Si surface, the very thin oxynitrides passivation layer of growth one deck between HfLaO dielectric film and Si, this passivation layer can suppress the growth of boundary layer.Then use the plasma-grown mode HfLaO dielectric film of growing, and original position carries out oxygen plasma post-treatment to said HfLaO dielectric film, reduce the oxygen room in the film.Adopt chlorobenzene solution to lift the photoresist of separating process and handle, can modify the burr at photoresist edge, make the photoresist edge slick and sly, thereby it is simpler and accurate to make that also the metal of back is lifted separating process being used to carry out metal.Adopt the MIS electric capacity of this method preparation to help reducing the quantity of additional interface layer, the interfacial layer thickness of attenuate and the roughness of reduction boundary layer; Help suppressing the Elements Diffusion between substrate and the film and reduce equivalent gate oxide thickness, can effectively improve the electric property of MIS electric capacity.
Description of drawings
Fig. 1 is shown as the manufacture method of MIS electric capacity of the present invention and makes schematic flow sheet.
Fig. 2～Fig. 3 is shown as the structural representation that the manufacture method step 1) of MIS electric capacity of the present invention is appeared.
Fig. 4 is shown as the manufacture method step 2 of MIS electric capacity of the present invention) structural representation that appeared.
Fig. 5 is shown as the structural representation that the manufacture method step 3) of MIS electric capacity of the present invention is appeared.
Fig. 6 is shown as the structural representation that the manufacture method step 4) of MIS electric capacity of the present invention is appeared.
Fig. 7 is shown as the structural representation that the manufacture method step 5) of MIS electric capacity of the present invention is appeared.
Fig. 8～Fig. 9 is shown as the structural representation that the manufacture method step 6) of MIS electric capacity of the present invention is appeared.
The element numbers explanation
S1-S6 step 1)～step 6)
101～103 SOI substrates
103 top layer silicon
104 silicon island
105 oxynitrides passivation layers
106 HfLaO dielectric films
107 HfLaO dielectric film islands
108 litho patterns
109 Ti layers
110 Pt layers
111 first electrodes
112 second electrodes
Embodiment
Below through specific instantiation execution mode of the present invention is described, those skilled in the art can understand other advantages of the present invention and effect easily by the content that this specification disclosed.The present invention can also implement or use through other different embodiment, and each item details in this specification also can be based on different viewpoints and application, carries out various modifications or change under the spirit of the present invention not deviating from.
See also Fig. 1 to Fig. 9.Need to prove; The diagram that is provided in the present embodiment is only explained basic conception of the present invention in a schematic way; Satisfy only show in graphic with the present invention in relevant assembly but not component count, shape and plotted when implementing according to reality; Kenel, quantity and the ratio of each assembly can be a kind of random change during its actual enforcement, and its assembly layout kenel also maybe be more complicated.
As shown in the figure, the present invention provides a kind of manufacture method of MIS electric capacity, it is characterized in that, comprises step at least:
See also S1 and Fig. 2～Fig. 3 among Fig. 1, as shown in the figure, at first carry out step 1), a SOI substrate 101～103 is provided, on the top layer silicon 103 of said SOI substrate 101～103, etch a plurality of separate silicon island 104.
In the present embodiment; After litho pattern is made on said SOI substrate 101～103 surfaces, be placed in the RIE etch chamber, adopt SF6 as corrosive agent; Through the said SOI top layer silicon of reactive ion etching (RIE) method etching 103 to oxygen buried layer, to form a plurality of separate silicon island 104.Certainly, in other embodiment, also can adopt other the said SOI substrate 101～103 of etching method etching.
See also S2 and Fig. 4 among Fig. 1, as shown in the figure, carry out step 2 then), remove the respectively oxide layer on these 104 surfaces, silicon island, form oxynitrides passivation layers 105 on these 104 surfaces, silicon island respectively then.
Particularly, adopting volume ratio is that 0.5%～1.5% 104 surfaces, the said silicon island of HF aqueous corrosion are to remove said oxide layer.In the present embodiment, 104 surfaces, the said silicon island of HF aqueous corrosion of employing 1% are to remove said oxide layer.Since SOI substrate 101～103 is cleaned or the process of photoetching in again its surface produce SiO
2Layer, SiO
2Layer can have a strong impact on reducing of interfacial layer thickness and leakage current, so adopt HF to remove surface oxide layer, can reduce interfacial layer thickness effectively here.
After removing oxide layer, the SOI substrate 101～103 that will have silicon island 104 places the ALD reaction chamber, feeds O to said ALD reaction chamber earlier
2And adding that RF power handles SOI substrate 101～103 to produce the O plasma, original position feeds NH to said ALD reaction chamber then
3, add then RF power with produce N, the H plasma is handled said SOI substrate 101～103 with silicon island 104, to form oxynitrides passivation layer 105 on the surface of this silicon island 104 respectively.This passivation layer can effectively suppress the growth of boundary layer.
See also S3 and Fig. 5 among Fig. 1; As shown in the figure; Then carry out step 3), using plasma enhancement mode atomic layer deposition method forms HfLaO dielectric film 106 on said oxynitrides passivation layer 105 surfaces, and said HfLaO dielectric film 106 is carried out oxygen plasma treatment.
In the present embodiment, SOI substrate 101～103 is placed the ALD reaction chamber, with [(CH
3) (C
2H
5) N]
4Hf is as HfO
2The reaction precursor body, La [N (TMS)
2]
3As La
2O
3The reaction precursor body, O
2As oxidant, using plasma enhancement mode atomic layer deposition method forms HfLaO dielectric film 106 on said oxynitrides passivation layer 105 surfaces.
Also comprise after this step said HfLaO dielectric film 106 is placed N
2The step of middle annealing, wherein, annealing temperature is 400～600 ℃, annealing time is 30～90s.In the present embodiment, annealing temperature is 500 ℃, and annealing time is 60s.This step can be eliminated internal stress and the defective of internal structure of HfLaO dielectric film 106 in putting.
After the annealing, the SOI substrate 101～103 that will have HfLaO dielectric film 106 places the ALD reaction chamber, and feeds O to said ALD reaction chamber
2, add that then RF power handles said HfLaO dielectric film 106 to produce O plasma and original position, to reduce the oxygen room in the said HfLaO dielectric film 106.Promptly keep the state of ALD reaction chamber constant, feed O to it
2, add that then RF power handles said HfLaO dielectric film 106 to produce the O plasma, to reduce the oxygen room in the said HfLaO dielectric film 106.
See also S4 and Fig. 6 among Fig. 1, as shown in the figure, then carry out step 4), etch HfLaO dielectric film 107 at said HfLaO dielectric film 106.
Particularly; Make litho pattern earlier; Adopt 1%～3% the said HfLaO dielectric film 106 of HF solution etching to 104 surfaces, said silicon island to form said HfLaO dielectric film 107 then, simultaneously, the outer zone of photoresist region covered is owing to the etching of HF solution produces hydrophobic property.In the present embodiment, the said HfLaO dielectric film 106 of HF solution etching to 104 surfaces, said silicon island of employing 2% are to form said HfLaO dielectric film 107.
See also S5 and Fig. 7 among Fig. 1; As shown in the figure; At first carry out step 5); 104 surfaces form photoresists in said HfLaO dielectric film 107 and said silicon island, and adopt chlorobenzene solution that said photoresist is soaked, and then said photoresist are developed to be formed on the litho pattern 108 that position that desire prepares electrode has window.
The time of particularly, adopting chlorobenzene solution to soak is 4～6min.The time of in the present embodiment, adopting chlorobenzene solution to soak is 5min.Adopt chlorobenzene solution to lift the photoresist of separating process and handle, can modify the burr at photoresist edge, make the photoresist edge slick and sly, thereby it is simpler and accurate to make that also the metal of back is lifted separating process being used to carry out metal.
See also S6 and Fig. 8～Fig. 9 among Fig. 1; As shown in the figure; At first carry out step 6); Form metal level in said litho pattern 108 surfaces, adopt metal to lift separating process then and form first electrode 111 and second electrode 112, and annealing is so that said first electrode 111 and second electrode 112 form ohmic contact with said HfLaO dielectric film 107 and silicon island 104 respectively respectively at said HfLaO dielectric film 107 and 104 surfaces, silicon island.
Particularly, adopt magnetron sputtering method to form Pt layer 110 that Ti layer 109 that thickness is 5～15nm and thickness is 50～150nm successively in said litho pattern 108 surfaces to form said metal level.Said metal level contacts with said HfLaO dielectric film 107 and silicon island 104 respectively through the window of said litho pattern 108.Adopt acetone soln to soak above-mentioned structure 8～16h then with litho pattern 108; Metal level on photoresist and the photoresist is peeled off, only keep at last the pairing metal structure of litho pattern 108 windows respectively as first electrode 111 and second electrode 112 of HfLaO dielectric film 107 and silicon island 104.After electrode forms, in volume ratio 15～25: 1 N
2, H
2Anneal in the gaseous mixture, annealing temperature is 400～500 ℃, and annealing time is 2～4min, so that said first electrode 111 and second electrode 112 form ohmic contact with said HfLaO dielectric film 107 and silicon island 104 respectively.
In the present embodiment, adopt magnetron sputtering method to form Pt layer 110 that Ti layer 109 that thickness is 10nm and thickness is 100nm successively in said litho pattern 108 surfaces to form said metal level.Said metal level contacts with said HfLaO dielectric film 107 and silicon island 104 respectively through the window of said litho pattern 108.Adopt acetone soln to soak above-mentioned structure 12h then with litho pattern 108; Metal level on photoresist and the photoresist is peeled off, only keep at last the pairing metal structure of litho pattern 108 windows respectively as the electrode of HfLaO dielectric film 107 and silicon island 104.After electrode forms, in volume ratio 19: 1 N
2, H
2Anneal in the gaseous mixture, annealing temperature is 450 ℃, and annealing time is 3min, so that said first electrode 111 and second electrode 112 form ohmic contact with said HfLaO dielectric film 107 and silicon island 104 respectively.
In sum, the manufacture method of MIS electric capacity of the present invention etches the silicon island in the SOI substrate, adopts HF to remove the oxide layer on surface, silicon island, can reduce the film interface layer thickness effectively.Utilize the plasma Atomic layer deposition method, adopt original position O
2, NH
3The technology on Cement Composite Treated by Plasma Si surface, the very thin oxynitrides passivation layer of growth one deck between HfLaO dielectric film and Si, this passivation layer can suppress the growth of boundary layer.Then use the plasma-grown mode HfLaO dielectric film of growing, and original position carries out oxygen plasma post-treatment to said HfLaO dielectric film, reduce the oxygen room in the film.Adopt chlorobenzene solution to lift the photoresist of separating process and handle, can modify the burr at photoresist edge, make the photoresist edge slick and sly, thereby it is simpler and accurate to make that also the metal of back is lifted separating process being used to carry out metal.Adopt the MIS electric capacity of this method preparation to help reducing the quantity of additional interface layer, the interfacial layer thickness of attenuate and the roughness of reduction boundary layer; Help suppressing the Elements Diffusion between substrate and the film and reduce equivalent gate oxide thickness, can effectively improve the electric property of MIS electric capacity.So the present invention has effectively overcome various shortcoming of the prior art and the tool high industrial utilization.
The foregoing description is illustrative principle of the present invention and effect thereof only, but not is used to limit the present invention.Any be familiar with this technological personage all can be under spirit of the present invention and category, the foregoing description is modified or is changed.Therefore, have common knowledge the knowledgeable in the affiliated such as technical field, must contain by claim of the present invention not breaking away from all equivalence modifications of being accomplished under disclosed spirit and the technological thought or changing.
Claims (9)
1. the manufacture method of a MIS electric capacity is characterized in that, comprises step at least:
1) a SOI substrate is provided, on the top layer silicon of said SOI substrate, etches a plurality of separate silicon island;
2) remove the respectively oxide layer on this surface, silicon island, form oxynitrides passivation layer on this surface, silicon island respectively then;
3) using plasma enhancement mode atomic layer deposition method forms the HfLaO dielectric film in said oxynitrides passivation layer surface, and said HfLaO dielectric film is carried out oxygen plasma treatment;
4) etch HfLaO dielectric film island at said HfLaO dielectric film;
5) in said HfLaO dielectric film island and said silicon island surface form photoresist, and adopt chlorobenzene solution that said photoresist is soaked, then said photoresist is developed to be formed on the litho pattern that position that desire prepares electrode has window;
6) form metal level in said litho pattern surface; Adopt metal to lift separating process then and form first electrode and second electrode, and annealing is so that said first electrode and second electrode form ohmic contact with said HfLaO dielectric film island and silicon island respectively respectively at said HfLaO dielectric film island and surface, silicon island.
2. the manufacture method of MIS electric capacity according to claim 1 is characterized in that: said step 3) also comprises said HfLaO dielectric film is placed N
2The step of middle annealing, wherein, annealing temperature is 400～600 ℃, annealing time is 30～90s.
3. the manufacture method of MIS electric capacity according to claim 1 is characterized in that: said step 2), adopting volume ratio is that 0.5%～1.5% surface, the said silicon island of HF aqueous corrosion is to remove said oxide layer.
4. the manufacture method of MIS electric capacity according to claim 1 is characterized in that: said step 2), the SOI substrate that will have the silicon island places the ALD reaction chamber, feeds O to said ALD reaction chamber earlier
2And adding that RF power handles the SOI substrate to produce the O plasma, original position feeds NH to said ALD reaction chamber then
3, add then RF power with produce N, the H plasma is handled said Si substrate or SOI substrate, to form the oxynitrides passivation layer on its surface.
5. the manufacture method of MIS electric capacity according to claim 1 is characterized in that: in the said step 3), with [(CH
3) (C
2H
5) N]
4Hf is as HfO
2The reaction precursor body, La [N (TMS)
2]
3As La
2O
3The reaction precursor body, O
2As oxidant, using plasma enhancement mode atomic layer deposition method forms the HfLaO dielectric film in said oxynitrides passivation layer surface.
6. the manufacture method of MIS electric capacity according to claim 1; It is characterized in that: in the said step 4); Make earlier litho pattern, adopt 1%～3% the said HfLaO dielectric film of HF solution etching to surface, said silicon island then to form said HfLaO dielectric film island.
7. the manufacture method of MIS electric capacity according to claim 1 is characterized in that: in the said step 5), the time of adopting chlorobenzene solution to soak is 4～6min.
8. the manufacture method of MIS electric capacity according to claim 1; It is characterized in that: in the said step 6), adopt magnetron sputtering method to form Pt layer that Ti layer that thickness is 5～15nm and thickness is 50～150nm successively in said litho pattern surface to form said metal level.
9. the manufacture method of MIS electric capacity according to claim 1 is characterized in that: in the said step 6), be 15～25: 1 N in volume ratio
2, H
2Anneal in the gaseous mixture, annealing temperature is 400～500 ℃, and annealing time is 2～4min, so that said first electrode and second electrode form ohmic contact with said HfLaO dielectric film island and silicon island respectively.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108335981A (en) * | 2018-03-01 | 2018-07-27 | 大连理工大学 | One kind having metal oxide dielectric layer MIS structure method of preparing capacitor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102226270A (en) * | 2011-04-29 | 2011-10-26 | 中国科学院上海微系统与信息技术研究所 | Method for depositing gate dielectric, method for preparing MIS capacitor and MIS capacitor |
| CN102254821A (en) * | 2011-07-11 | 2011-11-23 | 中国科学院上海微系统与信息技术研究所 | Metal oxide semiconductor (MOS) capacitor based on silicon-on-insulator (SOI) material and method for making MOS capacitor |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102226270A (en) * | 2011-04-29 | 2011-10-26 | 中国科学院上海微系统与信息技术研究所 | Method for depositing gate dielectric, method for preparing MIS capacitor and MIS capacitor |
| CN102254821A (en) * | 2011-07-11 | 2011-11-23 | 中国科学院上海微系统与信息技术研究所 | Metal oxide semiconductor (MOS) capacitor based on silicon-on-insulator (SOI) material and method for making MOS capacitor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108335981A (en) * | 2018-03-01 | 2018-07-27 | 大连理工大学 | One kind having metal oxide dielectric layer MIS structure method of preparing capacitor |
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