CN203732575U - PCB test board for chip testing - Google Patents
PCB test board for chip testing Download PDFInfo
- Publication number
- CN203732575U CN203732575U CN201420134651.5U CN201420134651U CN203732575U CN 203732575 U CN203732575 U CN 203732575U CN 201420134651 U CN201420134651 U CN 201420134651U CN 203732575 U CN203732575 U CN 203732575U
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- CN
- China
- Prior art keywords
- holes
- pcb
- group
- test
- pcb board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Abstract
The utility model discloses a PCB test board for chip testing. The PCB test board comprises a PCB. The PCB is provided with four through holes in square distribution and for connecting chips. The four through holes in square distribution form a group of through holes. The PCB is provided with a plurality of groups of through holes. The plurality of groups of through holes are distributed in the PCB in 7-8 lines from top down, and the lines are mutually parallel. The inner wall of each through hole in the PCB is provided with a conductive layer. Four welding points are arranged under each group of through holes respectively. The four welding points under each group of through holes are in electrical connection with the four through holes in the group respectively through copper wires on the surface of the PCB, and all the welding points are then connected to a test interface through other copper wires on the surface of the PCB. The PCB test board can test the plurality of chips simultaneously, and carry out a unified integration batch test on the chips, thereby greatly improving the testing efficiency.
Description
Technical field
The utility model relates to semiconductor die testing field, particularly a kind of PCB test board for chip testing.
Background technology
When at present SC88 semi-conductor chip test, one by one the respective pins of chip (chip) is connected with testing tool by artificial line, re-use testing tool the various unit for electrical property parameters of chip are carried out to test record, test separately one by one, testing efficiency is low.
Utility model content
The purpose of this utility model is to overcome existing above-mentioned deficiency in prior art, and the PCB test board for chip testing that a kind of testing efficiency is high is provided.
In order to realize foregoing invention object, the technical solution adopted in the utility model is:
A kind of PCB test board for chip testing, comprise pcb board, described pcb board is provided with four through holes that are square profile for connecting chip, four through holes of this square profile form one group of through hole, on described pcb board, there are many group through holes, organize through hole more and on pcb board, distribute from top to bottom that 7-8 is capable and every a line is parallel to each other; On described pcb board, each through-hole wall is provided with conductive layer, every group of through hole below is equipped with four solder joints, four solder joints of every group of through hole below are electrically connected with four through holes of this group respectively by the copper conductor on pcb board surface, and all solder joints are connected to test interface by the other copper conductor in pcb board surface respectively again.
Preferably, described conductive layer is metal conducting layer.
compared with prior art, the beneficial effects of the utility model:
PCB test board of the present utility model is provided with four through holes that are square profile for connecting chip, four through holes of this square profile form one group of through hole, on described pcb board, there are many group through holes, organize through hole more and on pcb board, distribute from top to bottom that 7-8 is capable and every a line is parallel to each other; On described pcb board, each through-hole wall is provided with conductive layer, every group of through hole below is equipped with four solder joints, four solder joints of every group of through hole below are electrically connected with four through holes of this group respectively by the copper conductor on pcb board surface, and all solder joints are connected to test interface by the other copper conductor in pcb board surface respectively again.When test, the respective pins of multiple SC88 chips is inserted in four through holes of every group, then by test interface, testing circuit board is connected with testing tool, can test some chips simultaneously, chip is carried out to Unified Set and become batch test, testing efficiency improves greatly.
brief description of the drawings:
Fig. 1 is the structural representation in the utility model embodiment.
Embodiment
Below in conjunction with embodiment, the utility model is described in further detail.But this should be interpreted as to the scope of the above-mentioned theme of the utility model only limits to following embodiment, all technology realizing based on the utility model content all belong to scope of the present utility model.
The PCB test board for chip testing as shown in Figure 1, comprise pcb board 1, described pcb board 1 is provided with four through holes 2 that are square profile for connecting chip, four through holes 2 of this square profile form one group of through hole, on described pcb board 1, there are many group through holes 2, many group through holes 2 distribute from top to bottom on pcb board 1, and 7-8 is capable and every a line is parallel to each other, and in the present embodiment, with 8 behavior example explanations, every row has 10 groups of through holes; On described pcb board 1, each through-hole wall is provided with conductive layer (not shown), every group of through hole 2 belows are equipped with four solder joints 3, four solder joints 3 of every group of through hole 2 belows are electrically connected with four through holes 2 of this group respectively by the copper conductor (not shown) on pcb board 1 surface, all solder joints 3 are connected to test interface 4 by the pcb board 1 other copper conductor (not shown) in surface respectively again, and described test interface 4 is row's needle interface.In Fig. 1, unshowned copper conductor is the pcb board 1 surface cabling of isolation mutually, and those skilled in the art know how to realize foregoing circuit connection according to word instruction of the present utility model.Preferably, described conductive layer is metal conducting layer, is preferably copper conductive layer.
When test, the respective pins of multiple SC88 chips is inserted on pcb board 1 in four through holes 2 of every group, four through holes that are square profile on this pcb board 1 and pin size are adaptive, after insertion, realize being connected of chip under test and circuit, by test interface, testing circuit board is connected with testing tool (as curve tracker) again, can test some chips simultaneously, as unit for electrical property parameters test etc., chip is carried out to Unified Set and become batch test, testing efficiency improves greatly.
By reference to the accompanying drawings embodiment of the present utility model is had been described in detail above, but the utility model is not restricted to above-mentioned embodiment, in the spirit and scope situation of claim that does not depart from the application, those skilled in the art can make various amendments or remodeling.
Claims (2)
1. the PCB test board for chip testing, comprise pcb board, it is characterized in that, described pcb board is provided with four through holes that are square profile for connecting chip, four through holes of this square profile form one group of through hole, on described pcb board, there are many group through holes, organize through hole more and on pcb board, distribute from top to bottom that 7-8 is capable and every a line is parallel to each other; On described pcb board, each through-hole wall is provided with conductive layer, every group of through hole below is equipped with four solder joints, four solder joints of every group of through hole below are electrically connected with four through holes of this group respectively by the copper conductor on pcb board surface, and all solder joints are connected to test interface by the other copper conductor in pcb board surface respectively again.
2. the PCB test board for chip testing according to claim 1, is characterized in that, described conductive layer is metal conducting layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420134651.5U CN203732575U (en) | 2014-03-24 | 2014-03-24 | PCB test board for chip testing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420134651.5U CN203732575U (en) | 2014-03-24 | 2014-03-24 | PCB test board for chip testing |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203732575U true CN203732575U (en) | 2014-07-23 |
Family
ID=51202638
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420134651.5U Expired - Fee Related CN203732575U (en) | 2014-03-24 | 2014-03-24 | PCB test board for chip testing |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203732575U (en) |
-
2014
- 2014-03-24 CN CN201420134651.5U patent/CN203732575U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140723 Termination date: 20160324 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |