CN203745490U - PCB test board used for SC70 chip test - Google Patents
PCB test board used for SC70 chip test Download PDFInfo
- Publication number
- CN203745490U CN203745490U CN201420135189.0U CN201420135189U CN203745490U CN 203745490 U CN203745490 U CN 203745490U CN 201420135189 U CN201420135189 U CN 201420135189U CN 203745490 U CN203745490 U CN 203745490U
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- pcb
- holes
- test
- chip
- pcb board
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- Expired - Fee Related
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Abstract
The utility model discloses a PCB test board used for an SC70 chip test. The PCB test board comprises a PCB which is provided with three through holes which are used for being connected with an SC70 chip and are distributed in triangle. One set of through holes is formed by the triangularly distributed three through holes. The PCB is provided with multiple sets of the through holes which are distributed on the PCB from the top to the bottom in 3-10 rows, and the rows are parallel with each other. The internal wall of each through hole on the PCB is provided with a conductive layer. Three welding points are arranged below each set of the through holes. The three welding points below each set of the through holes are electrically connected with the three through holes of the set respectively via copper conductive wires on the surface of the PCB. Then all the welding points are connected with test interfaces via other copper conductive wires on the surface of the PCB respectively. Multiple SC70 chips can be tested at the same time, and the chips are tested in unified and integrated batches so that test efficiency is greatly enhanced.
Description
Technical field
The utility model relates to semiconductor die testing field, particularly a kind of PCB test board for SC70 chip testing.
Background technology
When at present SC70 semi-conductor chip is tested, by artificial line, one by one the respective pins of chip (SC70 chip) is connected with testing tool, re-use testing tool the various unit for electrical property parameters of chip are carried out to test record, test separately one by one, testing efficiency is low.
Utility model content
The purpose of this utility model is to overcome existing above-mentioned deficiency in prior art, and the PCB test board for SC70 chip testing that a kind of testing efficiency is high is provided.
In order to realize foregoing invention object, the technical solution adopted in the utility model is:
A kind of PCB test board for SC70 chip testing, comprise pcb board, described pcb board is provided with for connecting three through holes of the distribution triangular in shape of SC70 chip, three through holes of this Triangle-Profile form one group of through hole, on described pcb board, there are many group through holes, organize through hole more and on pcb board, distribute from top to bottom that 3-10 is capable and every a line is parallel to each other; On described pcb board, each through-hole wall is provided with conductive layer, every group of through hole below is equipped with three solder joints, three solder joints of every group of through hole below are electrically connected to three through holes of this group respectively by the copper conductor on pcb board surface, and all solder joints are connected to test interface by the other copper conductor in pcb board surface respectively again.
Preferably, described conductive layer is metal conducting layer.
Further, described metal conducting layer is copper conductive layer.
Preferably, described test interface is row's needle interface.
compared with prior art, the beneficial effects of the utility model:
PCB test board of the present utility model is provided with for connecting three through holes of the distribution triangular in shape of SC70 chip, three through holes of this Triangle-Profile form one group of through hole, on described pcb board, there are many group through holes, organize through hole more and on pcb board, distribute from top to bottom that 3-10 is capable and every a line is parallel to each other; On described pcb board, each through-hole wall is provided with conductive layer, every group of through hole below is equipped with three solder joints, three solder joints of every group of through hole below are electrically connected to three through holes of this group respectively by the copper conductor on pcb board surface, and all solder joints are connected to test interface by the other copper conductor in pcb board surface respectively again.During test, the corresponding pin of a plurality of SC70 chips is inserted in three through holes of every group, by test interface, testing circuit board is connected with testing tool again, can test some SC70 chips simultaneously, chip be carried out to Unified Set and become batch test, testing efficiency improves greatly.
accompanying drawing explanation:
Fig. 1 is the structural representation of PCB test board in the utility model embodiment.
Embodiment
Below in conjunction with embodiment, the utility model is described in further detail.But this should be interpreted as to the scope of the above-mentioned theme of the utility model only limits to following embodiment, all technology realizing based on the utility model content all belong to scope of the present utility model.
The PCB test board for SC70 chip testing as shown in Figure 1, comprise pcb board 1, described pcb board 1 is provided with for connecting three through holes 2 of the distribution triangular in shape of SC70 chip, three through holes 2 of this Triangle-Profile form one group of through hole, on described pcb board 1, there are many group through holes, many group through holes distribute from top to bottom on pcb board 1, and 3-10 is capable and every a line is parallel to each other, in the present embodiment with 8 behaviors example explanations, every row have 10 groups described in through hole.On described pcb board 1, each through-hole wall is provided with conductive layer (not shown), every group of through hole 2 belows are equipped with three solder joints 3, three solder joints 3 of every group of through hole 2 belows are electrically connected to three through holes 2 of this group respectively by the copper conductor (not shown) on pcb board 1 surface, and all solder joints 3 are connected to test interface 4 by the pcb board 1 other copper conductor (not shown) in surface respectively again.In Fig. 1, unshowned copper conductor is the pcb board 1 surface cabling of isolation mutually, and those skilled in the art know how to realize foregoing circuit connection according to word instruction of the present utility model.Preferably, described conductive layer is metal conducting layer, and described metal conducting layer is copper conductive layer.Described test interface 4 is row's needle interface.
During test, the corresponding pin of a plurality of SC70 chips is inserted on pcb board 1 in three through holes 2 of every group, three through holes 2 of the distribution triangular in shape on this pcb board 1 are adaptive with chip pin size, after insertion, realize being connected of chip under test and circuit, by test interface 4, testing circuit board is connected with testing tool (as curve tracker) again, can test some SC70 chips simultaneously, as unit for electrical property parameters test etc., chip is carried out to Unified Set and become batch test, testing efficiency improves greatly.
By reference to the accompanying drawings embodiment of the present utility model is had been described in detail above, but the utility model is not restricted to above-mentioned embodiment, in the spirit and scope situation of claim that does not depart from the application, those skilled in the art can make various modifications or remodeling.
Claims (4)
1. the PCB test board for SC70 chip testing, comprise pcb board, it is characterized in that, described pcb board is provided with for connecting three through holes of the distribution triangular in shape of SC70 chip, three through holes of this Triangle-Profile form one group of through hole, on described pcb board, there are many group through holes, organize through hole more and on pcb board, distribute from top to bottom that 3-10 is capable and every a line is parallel to each other; On described pcb board, each through-hole wall is provided with conductive layer, every group of through hole below is equipped with three solder joints, three solder joints of every group of through hole below are electrically connected to three through holes of this group respectively by the copper conductor on pcb board surface, and all solder joints are connected to test interface by the other copper conductor in pcb board surface respectively again.
2. the PCB test board for SC70 chip testing according to claim 1, is characterized in that, described conductive layer is metal conducting layer.
3. the PCB test board for SC70 chip testing according to claim 2, is characterized in that, described metal conducting layer is copper conductive layer.
4. the PCB test board for SC70 chip testing according to claim 1, is characterized in that, described test interface is row's needle interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420135189.0U CN203745490U (en) | 2014-03-24 | 2014-03-24 | PCB test board used for SC70 chip test |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420135189.0U CN203745490U (en) | 2014-03-24 | 2014-03-24 | PCB test board used for SC70 chip test |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203745490U true CN203745490U (en) | 2014-07-30 |
Family
ID=51345275
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420135189.0U Expired - Fee Related CN203745490U (en) | 2014-03-24 | 2014-03-24 | PCB test board used for SC70 chip test |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203745490U (en) |
-
2014
- 2014-03-24 CN CN201420135189.0U patent/CN203745490U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140730 Termination date: 20160324 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |