CN203745603U - PCB test board used for SOD123 chip test - Google Patents
PCB test board used for SOD123 chip test Download PDFInfo
- Publication number
- CN203745603U CN203745603U CN201420134308.0U CN201420134308U CN203745603U CN 203745603 U CN203745603 U CN 203745603U CN 201420134308 U CN201420134308 U CN 201420134308U CN 203745603 U CN203745603 U CN 203745603U
- Authority
- CN
- China
- Prior art keywords
- pcb
- holes
- sod123
- test
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Abstract
The utility model discloses a PCB test board used for an SOD123 chip test. The PCB test board comprises a PCB which is provided with two through holes which are used for being connected with an SOD123 chip and are symmetrically distributed. One set of through holes is formed by the symmetrically distributed two through holes. The PCB is provided with multiple sets of the through holes which are distributed on the PCB from the top to the bottom in 4-8 rows, and the rows are parallel with each other. The internal wall of the each through hole on the PCB is provided with a conductive layer. Two welding points are arranged below each set of through holes. The two welding points below each set of the through holes are electrically connected with the two through holes of the set respectively via copper conductive wires arranged on the surface of the PCB. Then all the welding points are connected with test interfaces via other copper conductive wires arranged on the surface of the PCB respectively. Multiple SOD123 chips can be tested at the same time, and the chips are tested in unified and integrated batches so that test efficiency is greatly enhanced.
Description
Technical field
The utility model relates to semiconductor die testing field, particularly a kind of PCB test board for SOD123 chip testing.
Background technology
When at present SOD123 semi-conductor chip test, one by one the respective pins of chip (SOD123 chip) is connected with testing tool by artificial line, re-use testing tool the various unit for electrical property parameters of chip are carried out to test record, test separately one by one, testing efficiency is low.
Utility model content
The purpose of this utility model is to overcome existing above-mentioned deficiency in prior art, and the PCB test board for SOD123 chip testing that a kind of testing efficiency is high is provided.
In order to realize foregoing invention object, the technical solution adopted in the utility model is:
A kind of PCB test board for SOD123 chip testing, comprise pcb board, described pcb board is provided with two the symmetrical through holes for connecting SOD123 chip, these two symmetrical through holes form one group of through hole, on described pcb board, there are many group through holes, organize through hole more and on pcb board, distribute from top to bottom that 4-8 is capable and every a line is parallel to each other; On described pcb board, each through-hole wall is provided with conductive layer, every group of through hole below is equipped with two solder joints, two solder joints of every group of through hole below are electrically connected with two through holes of this group respectively by the copper conductor on pcb board surface, and all solder joints are connected to test interface by the other copper conductor in pcb board surface respectively again.
Preferably, described conductive layer is metal conducting layer.
Further, described metal conducting layer is copper conductive layer.
Preferably, described test interface is row's needle interface.
compared with prior art, the beneficial effects of the utility model:
PCB test board of the present utility model is provided with two the symmetrical through holes for connecting SOD123 chip, these two symmetrical through holes form one group of through hole, on described pcb board, there are many group through holes, organize through hole more and on pcb board, distribute from top to bottom that 4-8 is capable and every a line is parallel to each other; On described pcb board, each through-hole wall is provided with conductive layer, every group of through hole below is equipped with two solder joints, two solder joints of every group of through hole below are electrically connected with two through holes of this group respectively by the copper conductor on pcb board surface, and all solder joints are connected to test interface by the other copper conductor in pcb board surface respectively again.When test, the respective pins of multiple SOD123 chips is inserted in two through holes of every group, by test interface, testing circuit board is connected with testing tool again, can test some SOD123 chips simultaneously, chip be carried out to Unified Set and become batch test, testing efficiency improves greatly.
brief description of the drawings:
Fig. 1 is the structural representation in the utility model embodiment.
Embodiment
Below in conjunction with embodiment, the utility model is described in further detail.But this should be interpreted as to the scope of the above-mentioned theme of the utility model only limits to following embodiment, all technology realizing based on the utility model content all belong to scope of the present utility model.
The PCB test board for SOD123 chip testing as shown in Figure 1, comprise pcb board 1, described pcb board 1 is provided with two the symmetrical through holes 2 for connecting SOD123 chip, these two symmetrical through holes 2 form one group of through hole, on described pcb board 1, there are many group through holes, many group through holes distribute from top to bottom on pcb board, and 4-8 is capable and every a line is parallel to each other, in the present embodiment with 5 behaviors examples explanations, every row has 10 groups of through holes, on described pcb board 1, each through-hole wall is provided with conductive layer (not shown), every group of through hole 2 belows are equipped with two solder joints 3, two solder joints 3 of every group of through hole 2 belows are electrically connected with two through holes 2 of this group respectively by the copper conductor (not shown) on pcb board 1 surface, all solder joints 3 are connected to test interface 4 by the pcb board 1 other copper conductor (not shown) in surface respectively again.The unshowned copper conductor of Fig. 1 is the pcb board 1 surface cabling of isolation mutually, and those skilled in the art know how to realize foregoing circuit connection according to word instruction of the present utility model.Preferably, described conductive layer is metal conducting layer, and described metal conducting layer is copper conductive layer.Described test interface is row's needle interface.
When test, the respective pins of multiple SOD123 chips is inserted on pcb board in two through holes of every group, on this pcb board, symmetrical two through holes and pin size are adaptive, after insertion, realize being connected of chip under test and circuit, by test interface, testing circuit board is connected with testing tool (as curve tracker) again, can test some SOD123 chips simultaneously, as unit for electrical property parameters test etc., chip is carried out to Unified Set and become batch test, testing efficiency improves greatly.
By reference to the accompanying drawings embodiment of the present utility model is had been described in detail above, but the utility model is not restricted to above-mentioned embodiment, in the spirit and scope situation of claim that does not depart from the application, those skilled in the art can make various amendments or remodeling.
Claims (4)
1. the PCB test board for SOD123 chip testing, comprise pcb board, it is characterized in that, described pcb board is provided with two the symmetrical through holes for connecting SOD123 chip, these two symmetrical through holes form one group of through hole, on described pcb board, there are many group through holes, organize through hole more and on pcb board, distribute from top to bottom that 4-8 is capable and every a line is parallel to each other; On described pcb board, each through-hole wall is provided with conductive layer, every group of through hole below is equipped with two solder joints, two solder joints of every group of through hole below are electrically connected with two through holes of this group respectively by the copper conductor on pcb board surface, and all solder joints are connected to test interface by the other copper conductor in pcb board surface respectively again.
2. the PCB test board for SOD123 chip testing according to claim 1, is characterized in that, described conductive layer is metal conducting layer.
3. the PCB test board for SOD123 chip testing according to claim 2, is characterized in that, described metal conducting layer is copper conductive layer.
4. the PCB test board for SOD123 chip testing according to claim 1, is characterized in that, described test interface is row's needle interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420134308.0U CN203745603U (en) | 2014-03-24 | 2014-03-24 | PCB test board used for SOD123 chip test |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420134308.0U CN203745603U (en) | 2014-03-24 | 2014-03-24 | PCB test board used for SOD123 chip test |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203745603U true CN203745603U (en) | 2014-07-30 |
Family
ID=51345388
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420134308.0U Expired - Fee Related CN203745603U (en) | 2014-03-24 | 2014-03-24 | PCB test board used for SOD123 chip test |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203745603U (en) |
-
2014
- 2014-03-24 CN CN201420134308.0U patent/CN203745603U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140730 Termination date: 20160324 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |