CN203720836U - Data acquisition system based on source synchronous system - Google Patents
Data acquisition system based on source synchronous system Download PDFInfo
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- CN203720836U CN203720836U CN201420033882.7U CN201420033882U CN203720836U CN 203720836 U CN203720836 U CN 203720836U CN 201420033882 U CN201420033882 U CN 201420033882U CN 203720836 U CN203720836 U CN 203720836U
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Abstract
The utility model discloses a data acquisition system based on a source synchronous system. The data acquisition system comprises a sampling controller, a synchronizer, a RAM controller, two caches and a single-interface RAM. The sampling controller is used for acquiring input data and storing into the caches, the caches are used for sending fulfilling signals to the sampling controller, the sampling controller receives the fulfilling signals sent by the caches, stores the acquired data into the caches respectively and correspondingly and outputs handshake signals to the synchronizer. The synchronizer is used for converting the handshake signals so as to control the RAM controller to read data from the caches and store into the single-interface RAM. According to the data acquisition system based on the source synchronous system, the two caches are adopted, on the basis of guaranteeing the reliability of data transmitting, RAM source can be saved, requirements on the frequency of a local system clock during high-speed data acquisition are lowered greatly, and cost is saved.
Description
Technical field
The utility model relates to a kind of data acquisition system (DAS) based on source synchro system.
Background technology
Data acquisition is a ring of the most original also most critical of obtaining information, thereby has demand and application widely in a lot of industries or field.Particularly high-speed data acquisition, has high sampling rate, is particularly useful for the occasion that signal changes rapidly.In a lot of applications, such as distributed optical fiber temperature measurement aspect, original signal is very faint, and the same data that conventionally all need repeatedly to sample, to carry out progressive mean, are gone the object of disturbing thereby reach de-noising.
Because ordinary clock system exists the drawback that limits clock frequency, now a lot of high-speed data acquisition all adopt source synchro system.So-called source synchro system, be exactly source data and the clock signal sent be synchronous transmission, they meet certain sequential requirement, optimal situation is that clock effectively appears at the centre of data-signal along (as rising edge), as shown in Figure 1, in accompanying drawing 1, the first half represents the data-signal that source is sent, and the latter half represents the clock signal that source is sent.The advantage of source synchro system maximum is exactly the speed that has greatly promoted bus, and the transmission of signal can not be subject to the impact of transmission delay in theory.
In addition, in digital circuitry, conventionally all can relate to the conversion of clock zone, and how realize the data Focal point and difficult point of cross clock domain in designing often reliably.In the High Speed Data Collection Method based on source synchro system, needing the main problem of considering is exactly that the transmitting of solution cross clock domain data and the de-noising of weak useful signal go to disturb.In prior art, the design of the High Speed Data Collection Method based on source synchro system is that local system clock is done to synchronization process to the clock signal of external source synchro system output.
Although such disposal route has solved the integrity problem of data transmission, for improving the read-write speed of data, can cause cannot using or improving in the more nervous occasion of resource the cost of realizing of system.Simultaneously the frequency for local system clock has higher requirement, generally needs the frequency of local system clock to reach the more than four times of clock frequency of external source synchro system.The cost of realizing that this just causes the method cannot be applied in data acquisition occasion more at a high speed or greatly improve system.Cyclone IV Series FPGA (field programmable gate array) such as altera corp, its maximum clock frequency is 450MHz, according to the requirement of minimum four times, this means and adopt this Series FPGA can only be applied in external source synchro system clock frequency not higher than the occasion of 112.5MHz.If be applied in external source synchro system clock frequency up to occasion more than 200MHz, just must adopt performance higher, price also more expensive FPGA realizes.
Utility model content
The technical problems to be solved in the utility model is in order to overcome in prior art the data acquisition system (DAS) based on source synchro system in order to guarantee the reliability of data transmission, in RAM(random access memory) the more nervous occasion of resource cannot be used, for the frequency of local system clock require too high, be difficult in lower-cost situation, be applied to the defect under data acquisition occasion at a high speed, propose a kind of data acquisition system (DAS) based on source synchro system.
The utility model solves above-mentioned technical matters by following technical proposals:
The utility model provides a kind of data acquisition system (DAS) based on source synchro system, and its feature is, comprises sampling controller, synchronizer, RAM controller, the first buffer memory, the second buffer memory and single port RAM;
This sampling controller is for the data of Gather and input, and deposit the data that collect in the first buffer memory and the second buffer memory, the first buffer memory is filled with signal for sending one first to this sampling controller, the second buffer memory is filled with signal for sending one second to this sampling controller, this sampling controller receive this first be filled with signal the data that collect are deposited in to the second buffer memory and export the first handshake to this synchronizer, receive this and second be filled with signal and the data that collect deposited in to the first buffer memory and export the second handshake to this synchronizer;
This synchronizer is used for the first handshake receiving and the second handshake to be converted to respectively the 3rd handshake and the 4th handshake, and exports the 3rd handshake and the 4th handshake to this RAM controller;
This RAM controller, for fetching data and deposit single port RAM in from the first cache read when receiving the 3rd handshake, fetches data and deposits single port RAM in from the second cache read when receiving the 4th handshake.
It will be appreciated by those skilled in the art that RAM refers to random access memory, the data of this sampling controller institute Gather and input, gather the data-signal that external source synchro system is inputted.Correspondingly, the clock frequency for the collection of the data-signal of external source synchro system input corresponding to external source synchro system, therefore the first handshake and the second handshake are also corresponding to the clock frequency of external source synchro system.
This synchronizer is converted to the first handshake and the second handshake after the 3rd handshake and the 4th handshake, the 3rd handshake and the 4th handshake be no longer corresponding to the clock frequency of external source synchro system, and can be the clock frequency corresponding to local system.The 3rd handshake and the 4th handshake can trigger respectively this RAM controller sense data from two buffer memorys, and deposit in single port RAM.And the data that deposit single port RAM in can be, and the form adding up deposits in to single port RAM.
Need to should be mentioned that, the first buffer memory and the second buffer memory are just used as data buffer storage, and its capacity occupying is the size of several to dozens of bytes only, and the storage resources occupying is very little.
Preferably, this synchronizer comprises chopped-off head trigger and final stage trigger, and this chopped-off head trigger is used for latching the first handshake and the second handshake, and this final stage trigger is used for exporting the 3rd handshake and the 4th handshake to this RAM controller.The trigger pip of this chopped-off head trigger and this final stage trigger can be the clock frequency corresponding to local system, and not identical with the clock frequency of external source synchro system.
Preferably, the data width that the first buffer memory and the second buffer memory deposit in is less than the data width of reading.That is to say, the data width of the data storage mouth of the first buffer memory and the second buffer memory is less than respectively the data width of data reading-port.
Preferably, this first buffer memory is the first dual port RAM, and this second buffer memory is the second dual port RAM.
Those skilled in the art are to be understood that, dual port RAM is on a SRAM storer (being static RAM), to have two covers completely independently data line, address wire and read-write control line, and allow two independently system this storer is carried out the access of randomness, i.e. shared multiport memory simultaneously.
An advantage of the present utility model is, the data width that two buffer memorys deposit in can be less than the data width of reading, and the clock frequency that so just can be applicable to local system is less than in the situation of clock frequency of external source synchro system.And, although the clock frequency of local system may be lower, by the first buffer memory and the second buffer memory, bear separately certain data buffer storage effect, sample rate does not reduce.
Need to should be mentioned that, although the data acquisition system (DAS) so arranging has adopted three RAM resources, the RAM resource that seems employing is more, but in fact wherein the first buffer memory and the second buffer memory are just used as buffer memory, the capacity occupying is the size of several to dozens of bytes only, compared to existing technology, as the RAM of general data storage unit, need to take several thousand and even hundreds of kilobyte, resources occupation rate reduces greatly, almost can ignore.
Preferably, this data acquisition system (DAS) also comprises output unit, and this output unit is used for from single port RAM reading out data and exports external unit to.
Should be understood that, reading and exporting of this data can be conventionally after completing the data acquisition number and accumulative frequency of appointment, completed, and the output of data can be to issue other logical OR interfaces process or transmit by output unit.
Meeting on the basis of this area general knowledge, above-mentioned each optimum condition, can combination in any, obtains each preferred embodiments of the utility model.
Positive progressive effect of the present utility model is:
Data acquisition system (DAS) based on source synchro system of the present utility model, by adopting two buffer memorys, on the basis of reliability that guarantees data transmission, can save RAM resource and greatly reduce in high-speed data acquisition the requirement for the clock frequency of local system, provide cost savings.
Accompanying drawing explanation
Fig. 1 is clock signal desirable in the synchro system of source and the sequential relationship schematic diagram of data-signal.
Fig. 2 is the schematic diagram of the data acquisition system (DAS) of the utility model one preferred embodiment.
Embodiment
Mode below by embodiment further illustrates the utility model, but therefore the utility model is not limited among described scope of embodiments.
As shown in Figure 2, the data acquisition system (DAS) based on source synchro system, comprises sampling controller 1, synchronizer 4, RAM controller 6, the first dual port RAM 2, the second dual port RAM 3, single port RAM5 and output unit (not shown in Fig. 2).Fig. 2 left side, the arrow of the top represents the input of the data-signal of external source synchro system, and the arrow in centre position represents the clock signal of external source synchro system, and the arrow of below represents the clock signal of local system.Those skilled in the art are to be understood that, in Fig. 2, with arrow, schematically drawn the signal transmission relation between data acquisition system (DAS) various piece, and can determine thus the signal annexation between various piece, thereby in the present embodiment, repeat no more between the input end, output terminal of various piece and how to connect.
Wherein, this sampling controller is for the data of Gather and input, and deposit the data that collect in the first dual port RAM and the second dual port RAM, the first dual port RAM is filled with signal for sending one first to this sampling controller, the second dual port RAM is filled with signal for sending one second to this sampling controller, this sampling controller receives this and first is filled with signal and the data that collect is deposited in to the second dual port RAM and export the first handshake to this synchronizer, receiving this second is filled with signal and the data that collect is deposited in to the first dual port RAM and export the second handshake to this synchronizer.
This RAM controller for when receiving the 3rd handshake from the first dual port RAM reading out data and deposit single port RAM in, when receiving the 4th handshake from the second dual port RAM reading out data and deposit single port RAM in.
Wherein, this synchronizer comprises chopped-off head trigger and final stage trigger, and this chopped-off head trigger is used for latching the first handshake and the second handshake, and this final stage trigger is used for exporting the 3rd handshake and the 4th handshake to this RAM controller.
In the present embodiment, the data width that the first dual port RAM and the second dual port RAM deposit in is 8bit, and the data width of reading is 32bit, and the clock frequency that can be applicable to thus external source synchro system is greater than in the situation of clock frequency of local system.
Although more than described embodiment of the present utility model, it will be understood by those of skill in the art that these only illustrate, protection domain of the present utility model is limited by appended claims.Those skilled in the art is not deviating under the prerequisite of principle of the present utility model and essence, can make various changes or modifications to these embodiments, but these changes and modification all fall into protection domain of the present utility model.
Claims (5)
1. the data acquisition system (DAS) based on source synchro system, is characterized in that, comprises sampling controller, synchronizer, RAM controller, the first buffer memory, the second buffer memory and single port RAM;
This sampling controller is for the data of Gather and input, and deposit the data that collect in the first buffer memory and the second buffer memory, the first buffer memory is filled with signal for sending one first to this sampling controller, the second buffer memory is filled with signal for sending one second to this sampling controller, this sampling controller receive this first be filled with signal the data that collect are deposited in to the second buffer memory and export the first handshake to this synchronizer, receive this and second be filled with signal and the data that collect deposited in to the first buffer memory and export the second handshake to this synchronizer;
This synchronizer is used for the first handshake receiving and the second handshake to be converted to respectively the 3rd handshake and the 4th handshake, and exports the 3rd handshake and the 4th handshake to this RAM controller;
This RAM controller, for fetching data and deposit single port RAM in from the first cache read when receiving the 3rd handshake, fetches data and deposits single port RAM in from the second cache read when receiving the 4th handshake.
2. data acquisition system (DAS) as claimed in claim 1, it is characterized in that, this synchronizer comprises chopped-off head trigger and final stage trigger, this chopped-off head trigger is used for latching the first handshake and the second handshake, and this final stage trigger is used for exporting the 3rd handshake and the 4th handshake to this RAM controller.
3. data acquisition system (DAS) as claimed in claim 1, is characterized in that, the data width that the first buffer memory and the second buffer memory deposit in is less than the data width of reading.
4. the data acquisition system (DAS) as described in any one in claim 1-3, is characterized in that, this first buffer memory is the first dual port RAM, and this second buffer memory is the second dual port RAM.
5. data acquisition system (DAS) as claimed in claim 4, is characterized in that, this data acquisition system (DAS) also comprises output unit, and this output unit is used for from single port RAM reading out data and exports external unit to.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420033882.7U CN203720836U (en) | 2014-01-20 | 2014-01-20 | Data acquisition system based on source synchronous system |
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| CN201420033882.7U CN203720836U (en) | 2014-01-20 | 2014-01-20 | Data acquisition system based on source synchronous system |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104794080A (en) * | 2014-01-20 | 2015-07-22 | 上海光维通信技术股份有限公司 | Data collection system based on source synchronous system |
| CN108958701A (en) * | 2017-05-22 | 2018-12-07 | 深圳市中兴微电子技术有限公司 | A kind of data transfer control method, device and storage medium |
| CN108958700A (en) * | 2017-05-22 | 2018-12-07 | 深圳市中兴微电子技术有限公司 | A kind of first in first out data buffer and data cached method |
| CN112596438A (en) * | 2020-12-14 | 2021-04-02 | 武汉第二船舶设计研究所(中国船舶重工集团公司第七一九研究所) | Real-time reliable waveform data transmission circuit between FPGA and microcontroller |
-
2014
- 2014-01-20 CN CN201420033882.7U patent/CN203720836U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104794080A (en) * | 2014-01-20 | 2015-07-22 | 上海光维通信技术股份有限公司 | Data collection system based on source synchronous system |
| CN104794080B (en) * | 2014-01-20 | 2017-11-10 | 上海光维通信技术股份有限公司 | Data collecting system based on source synchronization system |
| CN108958701A (en) * | 2017-05-22 | 2018-12-07 | 深圳市中兴微电子技术有限公司 | A kind of data transfer control method, device and storage medium |
| CN108958700A (en) * | 2017-05-22 | 2018-12-07 | 深圳市中兴微电子技术有限公司 | A kind of first in first out data buffer and data cached method |
| CN112596438A (en) * | 2020-12-14 | 2021-04-02 | 武汉第二船舶设计研究所(中国船舶重工集团公司第七一九研究所) | Real-time reliable waveform data transmission circuit between FPGA and microcontroller |
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Effective date of registration: 20151217 Address after: 201805 Shanghai City Baihe Town Qingpu District Zhao Jiang Road 919 Lane 63, room E-112 Patentee after: Shanghai Grandway Telecom Tech Co., Ltd. Patentee after: Shanghai Guangjia Instruments Co., Ltd. Address before: 201805 Shanghai City Baihe Town Qingpu District Zhao Jiang Road 919 Lane 63, room E-112 Patentee before: Shanghai Grandway Telecom Tech Co., Ltd. |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140716 Termination date: 20190120 |
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| CF01 | Termination of patent right due to non-payment of annual fee |