CN108958700A - A kind of first in first out data buffer and data cached method - Google Patents
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Abstract
本发明公开了一种先进先出数据缓存器及缓存数据的方法，包括第一缓存单元、第二缓存单元、第三缓存单元、第一控制单元、第二控制单元和切换单元；第一控制单元，用于读取第一缓存单元的数据，写入第二缓存单元；第二控制单元，用于读取第一缓存单元的数据，写入第三缓存单元；当第二缓存单元非满时，读取第三缓存单元的数据，写入第二缓存单元；切换单元，用于获取输入端口的状态、第二控制单元的读写状态以及第一缓存单元和第二缓存单元的数据存储状态；根据获取的状态，打开/关闭第一控制单元或第二控制单元。本发明通过采用多倍数据位宽的单口RAM实现第三缓存单元，通过切换单元切换数据通路，能够有效减小芯片的面积，降低芯片的成本。
The invention discloses a first-in-first-out data buffer and a method for buffering data, including a first buffer unit, a second buffer unit, a third buffer unit, a first control unit, a second control unit and a switching unit; the first control unit The unit is used to read the data of the first cache unit and write it into the second cache unit; the second control unit is used to read the data of the first cache unit and write it into the third cache unit; when the second cache unit is not full , read the data of the third cache unit and write it into the second cache unit; the switching unit is used to obtain the state of the input port, the read and write status of the second control unit, and the data storage of the first cache unit and the second cache unit State; according to the obtained state, turn on/off the first control unit or the second control unit. The invention realizes the third cache unit by adopting a single-port RAM with multiple data bit width, and switches the data path through the switching unit, which can effectively reduce the area of the chip and reduce the cost of the chip.
Description
技术领域technical field
本发明涉及数据缓存技术领域，尤其涉及一种先进先出数据缓存器及缓存数据的方法。The invention relates to the technical field of data buffering, in particular to a first-in first-out data buffer and a method for buffering data.
背景技术Background technique
先进先出(FIFO，First In First Out)数据缓存器由于具备先进先出、平衡输入输出处理速率等特性，在数字集成电路设计中有着广泛的应用，主要用来匹配不同传输速度之间的数据传输。FIFO (First In First Out) data buffer is widely used in digital integrated circuit design due to its characteristics of first-in-first-out and balanced input and output processing rates. It is mainly used to match data between different transmission speeds. transmission.
根据FIFO工作的时钟域，可以将FIFO分为同步FIFO和异步FIFO。同步FIFO的读时钟和写时钟为同一个时钟，在时钟沿来临时同时发生读写操作；异步FIFO的读写时钟不一致，读写时钟是互相独立的。According to the clock domain where FIFO works, FIFO can be divided into synchronous FIFO and asynchronous FIFO. The read clock and write clock of the synchronous FIFO are the same clock, and read and write operations occur at the same time when the clock edge comes; the read and write clocks of the asynchronous FIFO are inconsistent, and the read and write clocks are independent of each other.
目前，同步FIFO在各类芯片设计中广泛应用，现有芯片设计中通常使用寄存器或伪双端口/双端口随机存取存储器(Ramdom Access Memory，RAM)来实现同步FIFO，当存储比特较少时，采用寄存器实现在面积上有优势；当存储比特较多时，用RAM实现在面积上有优势。如图1所示，一种现有的大容量同步FIFO包括输入端口、输出端口、写控制单元、读控制单元和伪双端口RAM单元，读控制单元和写控制单元用于产生读写地址进行读写以及产生空满信号提供给外围接口。图1所示的FIFO是一个典型的同步FIFO，由于需要同时进行读写，此FIFO采用了伪双端口RAM。At present, synchronous FIFOs are widely used in various chip designs. In existing chip designs, registers or pseudo-dual-port/dual-port random access memory (Ramdom Access Memory, RAM) are usually used to implement synchronous FIFOs. When storing fewer bits , the use of registers has an advantage in area; when there are many storage bits, the use of RAM has an advantage in area. As shown in Figure 1, a kind of existing large-capacity synchronous FIFO comprises input port, output port, write control unit, read control unit and pseudo-dual-port RAM unit, and read control unit and write control unit are used for generating read-write address to carry out Read and write and generate full and empty signals to the peripheral interface. The FIFO shown in Figure 1 is a typical synchronous FIFO. Due to the need to read and write at the same time, this FIFO uses a pseudo dual-port RAM.
发明内容Contents of the invention
为了解决上述技术问题，本发明提供了一种先进先出数据缓存器及缓存数据的方法，能够降低同步FIFO的面积。In order to solve the above technical problems, the present invention provides a first-in-first-out data buffer and a method for buffering data, which can reduce the area of the synchronous FIFO.
为了达到本发明目的，本发明实施例的技术方案是这样实现的：In order to achieve the object of the present invention, the technical scheme of the embodiment of the present invention is achieved in this way:
本发明实施例提供了一种先进先出数据缓存器，包括输入端口、输出端口，还包括第一缓存单元、第二缓存单元、第三缓存单元、第一控制单元、第二控制单元和切换单元，其中：An embodiment of the present invention provides a first-in-first-out data buffer, including an input port, an output port, and a first cache unit, a second cache unit, a third cache unit, a first control unit, a second control unit, and a switch unit, where:
所述第一缓存单元，用于存储通过输入端口输入的数据；The first buffer unit is used to store data input through the input port;
所述第二缓存单元，用于存储通过输出端口输出的数据；The second buffer unit is used to store the data output through the output port;
所述第三缓存单元为数据位宽为DW*n的单口随机存取存储器，用于存储通过第二控制单元输入或输出的数据，所述n为大于或等于2的自然数，DW为先进先出数据缓存器的数据位宽；The third cache unit is a single-port random access memory with a data bit width of DW*n, which is used to store data input or output by the second control unit, where n is a natural number greater than or equal to 2, and DW is advanced The data bit width of the output data buffer;
所述第一控制单元，用于读取第一缓存单元的数据，并写入第二缓存单元中；The first control unit is used to read the data of the first cache unit and write it into the second cache unit;
所述第二控制单元，用于读取第一缓存单元的数据，并写入第三缓存单元中；当第二缓存单元的数据存储状态为非满状态时，读取第三缓存单元的数据，并写入第二缓存单元中；The second control unit is configured to read the data of the first cache unit and write it into the third cache unit; when the data storage state of the second cache unit is not full, read the data of the third cache unit , and write into the second cache unit;
所述切换单元，用于获取输入端口的状态、第二控制单元的数据读写状态以及第一缓存单元与第二缓存单元的数据存储状态；并根据获取的状态，打开第一控制单元并关闭第二控制单元，或者关闭第一控制单元并打开第二控制单元。The switching unit is used to obtain the status of the input port, the data read and write status of the second control unit, and the data storage status of the first cache unit and the second cache unit; and according to the obtained status, open the first control unit and close the the second control unit, or turn off the first control unit and turn on the second control unit.
进一步地，所述切换单元根据获取的状态，打开第一控制单元并关闭第二控制单元，或者关闭第一控制单元并打开第二控制单元，具体包括：Further, the switching unit turns on the first control unit and turns off the second control unit, or turns off the first control unit and turns on the second control unit according to the obtained state, specifically including:
所述先进先出数据缓存器上电后，打开所述第一控制单元并关闭所述第二控制单元；After the FIFO data buffer is powered on, turn on the first control unit and turn off the second control unit;
当所述第一缓存单元与所述第二缓存单元的数据存储状态均为满状态且当前输入端口有数据输入时，关闭所述第一控制单元并打开所述第二控制单元；When the data storage states of the first cache unit and the second cache unit are both full and the current input port has data input, close the first control unit and open the second control unit;
当所述第二缓存单元的数据存储状态为非满状态且所述第二控制单元的数据读写状态为空状态时，打开所述第一控制单元并关闭所述第二控制单元。When the data storage state of the second cache unit is not full and the data read/write state of the second control unit is empty, the first control unit is turned on and the second control unit is turned off.
进一步地，所述第二控制单元包括写控制单元、读写仲裁单元和读控制单元，其中，Further, the second control unit includes a write control unit, a read-write arbitration unit and a read control unit, wherein,
所述写控制单元，用于产生写信号，所述写信号用于读取所述第一缓存单元的数据，并写入所述第三缓存单元中；The write control unit is used to generate a write signal, and the write signal is used to read the data of the first cache unit and write it into the third cache unit;
所述读控制单元，用于获取所述第二缓存单元的数据存储状态，当所述第二缓存单元的数据存储状态为非满状态时，产生读信号，所述读信号用于读取所述第三缓存单元的数据，并写入所述第二缓存单元中；The read control unit is configured to obtain the data storage state of the second cache unit, and when the data storage state of the second cache unit is not full, generate a read signal, and the read signal is used to read the The data of the third cache unit is written into the second cache unit;
所述读写仲裁单元，用于对产生的读信号和写信号进行仲裁。The read-write arbitration unit is used for arbitrating the generated read signal and write signal.
进一步地，所述第一缓存单元为数据位宽为DW、存储深度为(n-1)的寄存器。Further, the first cache unit is a register with a data bit width of DW and a storage depth of (n-1).
进一步地，所述第三缓存单元为数据位宽为DW*2、存储深度为MD/2的单口随机存取存储器，所述MD为先进先出数据缓存器的存储深度；所述第一缓存单元为数据位宽为DW、存储深度为1的寄存器。Further, the third cache unit is a single-port random access memory with a data bit width of DW*2 and a storage depth of MD/2, where the MD is the storage depth of a first-in-first-out data buffer; the first cache The unit is a register with a data bit width of DW and a storage depth of 1.
进一步地，所述第二缓存单元为数据位宽为DW、存储深度为4的寄存器。Further, the second cache unit is a register with a data bit width of DW and a storage depth of 4.
本发明实施例还提供了一种缓存数据的方法，包括如下步骤：The embodiment of the present invention also provides a method for caching data, including the following steps:
先进先出数据缓存器接收输入端口写入的数据，存储至第一缓存单元；The first-in-first-out data buffer receives the data written by the input port and stores it in the first buffer unit;
先进先出数据缓存器获取输入端口的状态、第二控制单元的数据读写状态以及第一缓存单元与第二缓存单元的数据存储状态；根据获取的状态，打开第一控制单元并关闭第二控制单元，或者关闭第一控制单元并打开第二控制单元；The FIFO data buffer obtains the status of the input port, the data read and write status of the second control unit, and the data storage status of the first cache unit and the second cache unit; according to the obtained status, the first control unit is turned on and the second control unit is turned off. control unit, or turn off the first control unit and turn on the second control unit;
当打开第一控制单元并关闭第二控制单元时，先进先出数据缓存器读取第一缓存单元的数据，并写入第二缓存单元中；When the first control unit is turned on and the second control unit is closed, the FIFO data buffer reads the data of the first cache unit and writes it into the second cache unit;
当关闭第一控制单元并打开第二控制单元时，先进先出数据缓存器读取第一缓存单元的数据，并写入第三缓存单元中，所述第三缓存单元为数据位宽为DW*n的单口随机存取存储器，所述n为大于或等于2的自然数，DW为先进先出数据缓存器的数据位宽；当第二缓存单元的数据存储状态为非满状态时，读取第三缓存单元的数据，并写入第二缓存单元中；When the first control unit is closed and the second control unit is opened, the first-in-first-out data buffer reads the data of the first cache unit and writes it into the third cache unit, and the third cache unit has a data bit width of DW *n single-port random access memory, said n is a natural number greater than or equal to 2, and DW is the data bit width of the first-in-first-out data buffer; when the data storage state of the second buffer unit is a non-full state, read The data of the third cache unit is written into the second cache unit;
所述先进先出数据缓存器通过输出端口读取第二缓存单元中存储的数据。The first-in-first-out data buffer reads the data stored in the second buffer unit through the output port.
进一步地，所述根据获取的状态，打开第一控制单元并关闭第二控制单元，或者关闭第一控制单元并打开第二控制单元的步骤，具体包括：Further, the step of turning on the first control unit and turning off the second control unit, or turning off the first control unit and turning on the second control unit according to the acquired state, specifically includes:
所述先进先出数据缓存器上电后，打开所述第一控制单元并关闭所述第二控制单元；After the FIFO data buffer is powered on, turn on the first control unit and turn off the second control unit;
当所述第一缓存单元与所述第二缓存单元的数据存储状态均为满状态且输入端口有数据输入时，关闭所述第一控制单元并打开所述第二控制单元；When the data storage states of the first cache unit and the second cache unit are both full and the input port has data input, close the first control unit and open the second control unit;
当所述第二缓存单元的数据存储状态为非满状态且所述第二控制单元的数据读写状态为空状态时，打开所述第一控制单元并关闭所述第二控制单元。When the data storage state of the second cache unit is not full and the data read/write state of the second control unit is empty, the first control unit is turned on and the second control unit is turned off.
进一步地，所述第三缓存单元为数据位宽为DW*2、存储深度为MD/2的单口随机存取存储器，所述MD为先进先出数据缓存器的存储深度；所述第一缓存单元为数据位宽为DW、存储深度为1的寄存器。Further, the third cache unit is a single-port random access memory with a data bit width of DW*2 and a storage depth of MD/2, where the MD is the storage depth of a first-in-first-out data buffer; the first cache The unit is a register with a data bit width of DW and a storage depth of 1.
进一步地，所述第二缓存单元为数据位宽为DW、存储深度为4的寄存器。Further, the second cache unit is a register with a data bit width of DW and a storage depth of 4.
本发明的技术方案，具有如下有益效果：The technical scheme of the present invention has the following beneficial effects:
本发明提供的先进先出数据缓存器及缓存数据的方法，通过采用多倍数据位宽的单口RAM分时复用，并通过切换单元控制第一控制单元和第二控制单元的状态，进而切换数据传输通路，有效地减小了芯片的面积，降低了芯片的成本，提高了芯片的竞争力。The first-in-first-out data buffer and the method for caching data provided by the present invention adopt time-division multiplexing of a single-port RAM with multiple data bit widths, and control the states of the first control unit and the second control unit through the switching unit, and then switch The data transmission path effectively reduces the area of the chip, reduces the cost of the chip, and improves the competitiveness of the chip.
附图说明Description of drawings
此处所说明的附图用来提供对本发明的进一步理解，构成本申请的一部分，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：The accompanying drawings described here are used to provide a further understanding of the present invention and constitute a part of the application. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations to the present invention. In the attached picture:
图1为传统的大容量同步FIFO结构示意图；Fig. 1 is the structural schematic diagram of traditional large-capacity synchronous FIFO;
图2为本发明第一实施例的一种先进先出数据缓存器的结构示意图；FIG. 2 is a schematic structural diagram of a first-in-first-out data buffer according to the first embodiment of the present invention;
图3为本发明第二实施例的一种先进先出数据缓存器的结构示意图；3 is a schematic structural diagram of a first-in-first-out data buffer according to a second embodiment of the present invention;
图4为本发明实施例的一种缓存数据的方法的流程示意图。Fig. 4 is a schematic flowchart of a method for caching data according to an embodiment of the present invention.
具体实施方式Detailed ways
为使本发明的目的、技术方案和优点更加清楚明白，下文中将结合附图对本发明的实施例进行详细说明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。In order to make the purpose, technical solution and advantages of the present invention more clear, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.
如图2所示，根据本发明的一种先进先出数据缓存器，包括输入端口、输出端口，还包括第一缓存单元、第二缓存单元、第三缓存单元、第一控制单元、第二控制单元和切换单元，其中：As shown in Figure 2, a first-in-first-out data buffer according to the present invention includes an input port and an output port, and also includes a first cache unit, a second cache unit, a third cache unit, a first control unit, a second Control unit and switching unit, where:
所述第一缓存单元，用于存储通过输入端口输入的数据；The first buffer unit is used to store data input through the input port;
所述第二缓存单元，用于存储通过输出端口输出的数据；The second buffer unit is used to store the data output through the output port;
所述第三缓存单元为数据位宽为DW*n的单口随机存取存储器，用于存储通过第二控制单元输入或输出的数据，所述n为大于或等于2的自然数，DW为先进先出数据缓存器的数据位宽；The third cache unit is a single-port random access memory with a data bit width of DW*n, which is used to store data input or output by the second control unit, where n is a natural number greater than or equal to 2, and DW is advanced The data bit width of the output data buffer;
所述第一控制单元，用于读取第一缓存单元的数据，并写入第二缓存单元中；The first control unit is used to read the data of the first cache unit and write it into the second cache unit;
所述第二控制单元，用于读取第一缓存单元的数据，并写入第三缓存单元中；当第二缓存单元的数据存储状态为非满状态时，读取第三缓存单元的数据，并写入第二缓存单元中；The second control unit is configured to read the data of the first cache unit and write it into the third cache unit; when the data storage state of the second cache unit is not full, read the data of the third cache unit , and write into the second cache unit;
所述切换单元，用于获取输入端口的状态、第二控制单元的数据读写状态以及第一缓存单元与第二缓存单元的数据存储状态；并根据获取的状态，打开第一控制单元并关闭第二控制单元，或者关闭第一控制单元并打开第二控制单元。The switching unit is used to obtain the status of the input port, the data read and write status of the second control unit, and the data storage status of the first cache unit and the second cache unit; and according to the obtained status, open the first control unit and close the the second control unit, or turn off the first control unit and turn on the second control unit.
需要说明的是，所述第一控制单元和第二控制单元在读取第一缓存单元的数据前，先获取第一缓存单元的数据存储状态，输入端口的状态和第二缓存单元的数据存储状态，当切换单元打开第一控制单元并关闭第二控制单元(即数据传输通路为输入端口、第一缓存单元、第一控制单元、第二缓存单元、输出端口)时，若第一缓存单元的数据存储状态为非空，且第二缓存单元的数据存储状态为非满，产生读写地址和读写信号读取第一缓存单元的数据写到第二缓存单元中；当切换单元关闭第一控制单元并打开第二控制单元(即数据传输通路为输入端口、第一缓存单元、第二控制单元、第三缓存单元、第二控制单元、第二缓存单元、输出端口)时，若第一缓存单元的数据存储状态为满、输入端口有数据输入时，产生读写地址和读写信号读取第一缓存单元的数据，写入第三缓存单元中。所述第一控制单元、第二控制单元和切换单元均可以通过现有的组合和时序逻辑电路实现。It should be noted that, before reading the data of the first cache unit, the first control unit and the second control unit first obtain the data storage status of the first cache unit, the status of the input port and the data storage status of the second cache unit. state, when the switching unit turns on the first control unit and closes the second control unit (that is, the data transmission path is the input port, the first cache unit, the first control unit, the second cache unit, and the output port), if the first cache unit The data storage status of the first cache unit is non-empty, and the data storage status of the second cache unit is not full, and the read-write address and the read-write signal are generated to read the data of the first cache unit and write to the second cache unit; when the switching unit closes the second cache unit When a control unit opens the second control unit (that is, the data transmission path is the input port, the first cache unit, the second control unit, the third cache unit, the second control unit, the second cache unit, and the output port), if the first When the data storage state of a cache unit is full and the input port has data input, a read-write address and a read-write signal are generated to read the data of the first cache unit and write it into the third cache unit. The first control unit, the second control unit and the switch unit can all be realized by existing combination and sequential logic circuits.
进一步地，所述切换单元根据获取的状态，打开第一控制单元并关闭第二控制单元，或者关闭第一控制单元并打开第二控制单元，具体包括：Further, the switching unit turns on the first control unit and turns off the second control unit, or turns off the first control unit and turns on the second control unit according to the obtained state, specifically including:
所述先进先出数据缓存器上电后，打开所述第一控制单元并关闭所述第二控制单元；After the FIFO data buffer is powered on, turn on the first control unit and turn off the second control unit;
当第一缓存单元与第二缓存单元的数据存储状态均为满状态且输入端口有数据输入时，关闭第一控制单元并打开第二控制单元；When the data storage states of the first cache unit and the second cache unit are both full and the input port has data input, close the first control unit and open the second control unit;
当第二缓存单元的数据存储状态为非满状态且第二控制单元的数据读写状态为空状态时，打开第一控制单元并关闭第二控制单元。When the data storage state of the second cache unit is not full and the data read/write state of the second control unit is empty, the first control unit is turned on and the second control unit is turned off.
在本发明一实施例中，先进先出数据缓存器上电复位后，切换单元打开第一控制单元并关闭第二控制单元，从第一缓存单元中读取输入的数据，并写入第二缓存单元中，此时输出端口可能为空状态，也可能为非空状态，当第二缓存单元没有写满之前，一直通过第一控制单元读写数据；In an embodiment of the present invention, after the FIFO data buffer is powered on and reset, the switching unit turns on the first control unit and turns off the second control unit, reads the input data from the first buffer unit, and writes the second In the cache unit, the output port may be in an empty state at this time, or it may be in a non-empty state. When the second cache unit is not full, the data is read and written through the first control unit;
当第二缓存单元写满以后，新输入的数据先缓存到第一缓存单元中；When the second cache unit is full, the newly input data is first cached in the first cache unit;
如果还有数据输入，那么切换单元产生通道切换信号，关闭第一控制单元并打开第二控制单元，读取第一缓存单元的数据，并写入第三缓存单元中；If there is still data input, then the switching unit generates a channel switching signal, closes the first control unit and opens the second control unit, reads the data of the first cache unit, and writes it into the third cache unit;
获取第二缓存单元的数据存储状态，一旦第二缓存单元中有数据存储空间时，第二控制单元从第三缓存单元读出数据，并将读出的数据写入第二缓存单元中；Acquiring the data storage state of the second cache unit, once there is data storage space in the second cache unit, the second control unit reads data from the third cache unit, and writes the read data into the second cache unit;
当第三缓存单元中的数据全部读完且此时没有数据要写到第三缓存单元中时，切换单元产生通道切换信号，打开第一控制单元并关闭第二控制单元，然后持续根据存储和输入情况自动重复以上的判断和通道切换。When all the data in the third cache unit has been read and there is no data to be written into the third cache unit at this time, the switching unit generates a channel switching signal, turns on the first control unit and closes the second control unit, and then continues according to the storage and The input situation automatically repeats the above judgment and channel switching.
进一步地，参考图3，所述第二控制单元包括写控制单元、读写仲裁单元和读控制单元，其中，Further, referring to FIG. 3, the second control unit includes a write control unit, a read-write arbitration unit, and a read control unit, wherein,
写控制单元，用于产生写信号，所述写信号用于读取第一缓存单元的数据，并写入第三缓存单元中；A write control unit, configured to generate a write signal, the write signal is used to read the data of the first cache unit and write it into the third cache unit;
读控制单元，用于获取所述第二缓存单元的数据存储状态，当第二数据存储状态为非满状态时，产生读信号，所述读信号用于读取第三缓存单元的数据，并写入第二缓存单元中；A read control unit, configured to obtain the data storage state of the second cache unit, and generate a read signal when the second data storage state is not full, and the read signal is used to read the data of the third cache unit, and write into the second cache unit;
读写仲裁单元，用于对产生的读信号和写信号进行仲裁，以避免对第三缓存单元的读写冲突。The read-write arbitration unit is used for arbitrating the generated read signal and write signal, so as to avoid read-write conflicts on the third cache unit.
值得说明的是，由于单口RAM无法同时进行读写，本发明的第三缓存单元采用多倍数据位宽(1个时钟周期写/读多倍数据位宽的数据)的单口RAM分时复用，采用时间片读写数据，以位宽换取时间，解决FIFO同时需要读写的问题。另外由于单口RAM读写两部分逻辑是独立的，会产生读写冲突的问题，本发明中引入读写仲裁单元来解决读写冲突的问题。It should be noted that since the single-port RAM cannot read and write at the same time, the third cache unit of the present invention adopts the time-division multiplexing of the single-port RAM with multiple data bit widths (one clock cycle writes/reads data with multiple data bit widths). , use time slices to read and write data, exchange bit width for time, and solve the problem that FIFO needs to read and write at the same time. In addition, because the logic of the read and write parts of the single-port RAM is independent, the problem of read and write conflicts will occur. In the present invention, a read and write arbitration unit is introduced to solve the problem of read and write conflicts.
进一步地读写仲裁单元采用写优先策略。Further, the read and write arbitration unit adopts a write priority strategy.
进一步地，所述切换单元通过获取写控制单元和读控制单元的数据读写状态来获取所述第二控制单元的数据读写状态，当写控制单元的数据读写状态为满状态时，第二控制单元的数据读写状态为满状态(此时，第三缓存单元的数据存储状态也为满状态)；当读控制单元的数据读写状态为空状态时，第二控制单元的数据读写状态为空状态(此时，第三缓存单元的数据读写状态也为空状态)。Further, the switching unit acquires the data read-write status of the second control unit by acquiring the data read-write status of the write control unit and the read control unit, and when the data read-write status of the write control unit is full, the second The data read/write state of the second control unit is a full state (at this moment, the data storage state of the third cache unit is also a full state); when the data read/write state of the read control unit is an empty state, the data read/write state of the second control unit The writing state is an empty state (at this time, the data reading and writing state of the third cache unit is also an empty state).
进一步地，参考图3，所述第二缓存单元和第一控制单元、第二控制单元之间设有数据选择器，所述数据选择器用于根据第一控制单元和第二控制单元的状态，从第一控制单元或第二控制单元中选择写入第二缓存单元的数据。Further, referring to FIG. 3 , a data selector is provided between the second buffer unit, the first control unit, and the second control unit, and the data selector is used to, according to the states of the first control unit and the second control unit, Data to be written into the second cache unit is selected from the first control unit or the second control unit.
进一步地，所述第一缓存单元为数据位宽为DW、存储深度为(n-1)的寄存器。Further, the first cache unit is a register with a data bit width of DW and a storage depth of (n-1).
需要说明的是，缓存容量等于数据位宽和存储深度的乘积，所述数据位宽、存储深度分别指一次写入或读出的比特位数、最多可存储多少个数据位宽的数据量。It should be noted that the cache capacity is equal to the product of the data bit width and the storage depth. The data bit width and the storage depth respectively refer to the number of bits written or read at one time, and the maximum data amount of the data bit width that can be stored.
在本发明一具体实施例中，所述第三缓存单元为数据位宽为DW*2、存储深度为MD/2的单口随机存取存储器RAM，所述MD为先进先出数据缓存器的存储深度；第一缓存单元为数据位宽为DW、存储深度为1的寄存器。In a specific embodiment of the present invention, the third cache unit is a single-port random access memory RAM with a data bit width of DW*2 and a storage depth of MD/2, and the MD is a first-in-first-out data buffer storage Depth: the first cache unit is a register with a data bit width of DW and a storage depth of 1.
在本发明一具体实施例中，所述第二缓存单元为数据位宽为DW、存储深度为4的寄存器。In a specific embodiment of the present invention, the second cache unit is a register with a data bit width of DW and a storage depth of 4.
具体地，由于第二缓存单元的数据位宽为DW而第三缓存单元单口RAM的位宽为DW*2，因此可以保证两个时钟周期内至少有一个用于从RAM读取数据；由于第二缓存单元的存储深度为4，数据可以以1个时钟周期两个DW数据位宽的速度读出，并写到第二缓存单元中，这样在输入端无数据的情况下，可以实现数据从第三缓存单元到第二缓存单元的快速搬运，节约时间以保证通路控制单元在切换数据流通道时，先进先出数据缓存器的数据输出的连续性。Specifically, since the data bit width of the second cache unit is DW and the bit width of the single-port RAM of the third cache unit is DW*2, it can be guaranteed that at least one of the two clock cycles is used to read data from the RAM; The storage depth of the second cache unit is 4, and the data can be read at the speed of two DW data bits in one clock cycle, and written to the second cache unit, so that when there is no data at the input end, the data can be read from The fast transfer from the third buffer unit to the second buffer unit saves time and ensures the continuity of the data output of the first-in-first-out data buffer when the access control unit switches the data flow channel.
如图4所示，根据本发明的一种缓存数据的方法，包括如下步骤：As shown in Figure 4, a method for caching data according to the present invention includes the following steps:
步骤401：先进先出数据缓存器接收输入端口写入的数据，存储至第一缓存单元；Step 401: The FIFO data buffer receives the data written by the input port and stores it in the first buffer unit;
步骤402：先进先出数据缓存器获取输入端口的状态、第二控制单元的数据读写状态以及第一缓存单元与第二缓存单元的数据存储状态；Step 402: the FIFO data buffer obtains the status of the input port, the data read and write status of the second control unit, and the data storage status of the first cache unit and the second cache unit;
步骤403：根据获取的状态，打开第一控制单元并关闭第二控制单元，或者关闭第一控制单元并打开第二控制单元；Step 403: Turn on the first control unit and turn off the second control unit, or turn off the first control unit and turn on the second control unit according to the acquired state;
当打开第一控制单元并关闭第二控制单元时，先进先出数据缓存器读取第一缓存单元的数据，并写入第二缓存单元中；When the first control unit is turned on and the second control unit is closed, the FIFO data buffer reads the data of the first cache unit and writes it into the second cache unit;
当关闭第一控制单元并打开第二控制单元时，先进先出数据缓存器读取第一缓存单元的数据，并写入第三缓存单元中，所述第三缓存单元为数据位宽为DW*n的单口随机存取存储器，所述n为大于或等于2的自然数，DW为先进先出数据缓存器的数据位宽；当第二缓存单元的数据存储状态为非满状态时，读取第三缓存单元的数据，并写入第二缓存单元中；When the first control unit is closed and the second control unit is opened, the first-in-first-out data buffer reads the data of the first cache unit and writes it into the third cache unit, and the third cache unit has a data bit width of DW *n single-port random access memory, said n is a natural number greater than or equal to 2, and DW is the data bit width of the first-in-first-out data buffer; when the data storage state of the second buffer unit is a non-full state, read The data of the third cache unit is written into the second cache unit;
步骤404：先进先出数据缓存器通过输出端口读取第二缓存单元中存储的数据。Step 404: The FIFO data buffer reads the data stored in the second buffer unit through the output port.
进一步地，所述步骤403中根据获取的状态，打开第一控制单元并关闭第二控制单元，或者关闭第一控制单元并打开第二控制单元的步骤，具体包括：Further, the step of turning on the first control unit and turning off the second control unit, or turning off the first control unit and turning on the second control unit according to the acquired state in step 403, specifically includes:
所述先进先出数据缓存器上电后，打开所述第一控制单元并关闭所述第二控制单元；After the FIFO data buffer is powered on, turn on the first control unit and turn off the second control unit;
当第一缓存单元与第二缓存单元的数据存储状态均为满状态且输入端口有数据输入时，关闭第一控制单元并打开第二控制单元；When the data storage states of the first cache unit and the second cache unit are both full and the input port has data input, close the first control unit and open the second control unit;
当第二缓存单元的数据存储状态为非满状态且第二控制单元的数据读写状态为空状态时，打开第一控制单元并关闭第二控制单元。When the data storage state of the second cache unit is not full and the data read/write state of the second control unit is empty, the first control unit is turned on and the second control unit is turned off.
在本发明一实施例中，先进先出数据缓存器上电复位后，切换单元打开第一控制单元并关闭第二控制单元，从第一缓存单元中读取输入的数据，并写入第二缓存单元中，此时输出端口可能为空状态，也可能为非空状态，当第二缓存单元没有写满之前，一直通过第一控制单元读写数据；In an embodiment of the present invention, after the FIFO data buffer is powered on and reset, the switching unit turns on the first control unit and turns off the second control unit, reads the input data from the first buffer unit, and writes the second In the cache unit, the output port may be in an empty state at this time, or it may be in a non-empty state. When the second cache unit is not full, the data is read and written through the first control unit;
当第二缓存单元写满以后，新输入的数据先缓存到第一缓存单元中；When the second cache unit is full, the newly input data is first cached in the first cache unit;
如果还有数据输入，那么切换单元产生通道切换信号，关闭第一控制单元并打开第二控制单元，读取第一缓存单元的数据，并写入第三缓存单元中；If there is still data input, then the switching unit generates a channel switching signal, closes the first control unit and opens the second control unit, reads the data of the first cache unit, and writes it into the third cache unit;
获取第二缓存单元的数据存储状态，一旦第二缓存单元中有数据存储空间时，第二控制单元从第三缓存单元读出数据，并将读出的数据写入第二缓存单元中；Acquiring the data storage state of the second cache unit, once there is data storage space in the second cache unit, the second control unit reads data from the third cache unit, and writes the read data into the second cache unit;
当第三缓存单元中的数据全部读完且此时没有数据要写到第三缓存单元中时，切换单元产生通道切换信号，打开第一控制单元并关闭第二控制单元，然后持续根据存储和输入情况自动重复以上的判断和通道切换。When all the data in the third cache unit has been read and there is no data to be written into the third cache unit at this time, the switching unit generates a channel switching signal, turns on the first control unit and closes the second control unit, and then continues according to the storage and The input situation automatically repeats the above judgment and channel switching.
进一步地，所述第一缓存单元为数据位宽为DW、存储深度为(n-1)的寄存器。Further, the first cache unit is a register with a data bit width of DW and a storage depth of (n-1).
进一步地，所述第三缓存单元为数据位宽为DW*2、存储深度为MD/2的单口随机存取存储器RAM，MD为先进先出数据缓存器的存储深度；第一缓存单元为数据位宽为DW、存储深度为1的寄存器。Further, the third cache unit is a single-port random access memory RAM with a data bit width of DW*2 and a storage depth of MD/2, where MD is the storage depth of the first-in first-out data buffer; the first cache unit is the data A register with a bit width of DW and a memory depth of 1.
需要说明的是，本发明的第三缓存单元采用多倍数据位宽的单口RAM分时复用，采用时间片读写数据，以位宽换取时间，解决FIFO同时需要读写的问题，利用读写仲裁机制解决读写冲突问题。本发明的读写仲裁机制采用写优先策略。It should be noted that the third cache unit of the present invention uses a single-port RAM with multiple data bit widths for time-division multiplexing, uses time slices to read and write data, and trades bit widths for time to solve the problem that FIFOs need to be read and written at the same time. The write arbitration mechanism solves the problem of read and write conflicts. The read-write arbitration mechanism of the present invention adopts a write priority strategy.
进一步地，所述第二缓存单元为数据位宽为DW、存储深度为4的寄存器。Further, the second cache unit is a register with a data bit width of DW and a storage depth of 4.
具体地，由于第二缓存单元的数据位宽为DW而第三缓存单元单口RAM的位宽为DW*2，因此可以保证两个时钟周期内至少有一个用于从RAM读取数据；由于第二缓存单元的存储深度为4，数据可以以1个时钟周期两个DW数据位宽的速度读出，并写到第二缓存单元中，这样在输入端无数据的情况下，可以实现数据从第三缓存单元到第二缓存单元的快速搬运，节约时间以保证通路控制单元在切换数据流通道时，先进先出数据缓存器的数据输出的连续性。Specifically, since the data bit width of the second cache unit is DW and the bit width of the single-port RAM of the third cache unit is DW*2, it can be guaranteed that at least one of the two clock cycles is used to read data from the RAM; The storage depth of the second cache unit is 4, and the data can be read at the speed of two DW data bits in one clock cycle, and written to the second cache unit, so that when there is no data at the input end, the data can be read from The fast transfer from the third buffer unit to the second buffer unit saves time and ensures the continuity of the data output of the first-in-first-out data buffer when the access control unit switches the data flow channel.
根据本发明的先进先出数据缓存器，其面积相比于传统的大容量FIFO具有明显的优势，以存储深度*数据宽度为800x128的FIFO为例，第一缓存单元的存储深度*数据宽度为1*128，第二缓存单元的存储深度*数据宽度为4*128，第三缓存单元的存储深度*数据宽度为400*256。如果采用伪双端口RAM，那么面积为52145um2，如果采用本发明，那么可以用400x256的单端口RAM来解决问题，面积为22825um2，能节约56％的面积，考虑到新增加的外部逻辑的面积(1405um2)，仍然能够节省53.5％的面积，进而能够降低芯片的成本，提高芯片的竞争力。According to the first-in-first-out data buffer of the present invention, its area has obvious advantages compared to traditional large-capacity FIFOs. Taking the FIFO whose storage depth*data width is 800x128 as an example, the storage depth*data width of the first buffer unit is 1*128, the storage depth*data width of the second cache unit is 4*128, and the storage depth*data width of the third cache unit is 400*256. If a pseudo-dual-port RAM is used, the area is 52145um 2 , and if the present invention is adopted, a 400x256 single-port RAM can be used to solve the problem, and the area is 22825um 2 , which can save 56% of the area, considering the newly added external logic The area (1405um 2 ) can still save 53.5% of the area, thereby reducing the cost of the chip and improving the competitiveness of the chip.
本领域普通技术人员可以理解上述方法中的全部或部分步骤可通过程序来指令相关硬件完成，所述程序可以存储于计算机可读存储介质中，如只读存储器、磁盘或光盘等。可选地，上述实施例的全部或部分步骤也可以使用一个或多个集成电路来实现，相应地，上述实施例中的各模块/单元可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。本发明不限制于任何特定形式的硬件和软件的结合。Those skilled in the art can understand that all or part of the steps in the above method can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, a magnetic disk or an optical disk, and the like. Optionally, all or part of the steps in the above embodiments can also be implemented using one or more integrated circuits. Correspondingly, each module/unit in the above embodiments can be implemented in the form of hardware, or can be implemented in the form of software function modules. The form is realized. The present invention is not limited to any specific combination of hardware and software.
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.
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