CN108958700A - A kind of first in first out data buffer and data cached method - Google Patents
A kind of first in first out data buffer and data cached method Download PDFInfo
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Abstract
The invention discloses a kind of first in first out data buffer and data cached methods, including the first cache unit, the second cache unit, third cache unit, first control unit, the second control unit and switch unit；The second cache unit is written for reading the data of the first cache unit in first control unit；Third cache unit is written for reading the data of the first cache unit in second control unit；When the second cache unit is non-full, the data of third cache unit are read, the second cache unit is written；Switch unit, for obtaining state, the read-write state of the second control unit and the state data memory of the first cache unit and the second cache unit of input port；According to the state of acquisition, first control unit or the second control unit are opened/closed.The present invention realizes that third cache unit can effectively reduce the area of chip by switch unit switch data access by using the single port RAM of more haplotype data bit wides, reduces the cost of chip.
Description
Technical field
The present invention relates to Data cache technology field more particularly to a kind of first in first out data buffers and data cached
Method.
Background technique
First in first out (FIFO, First In First Out) data buffer is due to having first in first out, balance input
The characteristics such as processing speed are exported, are had a wide range of applications in Design of Digital Integrated Circuit, are mainly used to match different transmission speed
Data transmission between degree.
According to the clock domain that FIFO works, FIFO can be divided for synchronization fifo and asynchronous FIFO.When the reading of synchronization fifo
Clock is the same clock with clock is write, and comes interim on clock edge while read-write operation occurs；The read-write clock of asynchronous FIFO is different
It causes, read-write clock is independent of each other.
Currently, synchronization fifo is widely applied in the design of all kinds of chips, in the design of existing chip usually using register or
Pseudo-double port/dual-port random access memory (Ramdom Access Memory, RAM) realizes synchronization fifo, works as storage
When bit is less, realized using register advantageous on area；When stored bits are more, realize have on area with RAM
Advantage.As shown in Figure 1, a kind of existing large capacity synchronization fifo includes input port, output port, writes control unit, reads control
Unit and pseudo-double port ram cell processed, reads control unit and writes control unit to be written and read and produce for generating read/write address
Raw empty full signal is supplied to peripheral interface.FIFO shown in FIG. 1 is a typical synchronization fifo, due to needing while being read
It writes, this FIFO uses pseudo-double port RAM.
Summary of the invention
In order to solve the above-mentioned technical problems, the present invention provides a kind of first in first out data buffer and data cached sides
Method can reduce the area of synchronization fifo.
In order to reach the object of the invention, the technical solution of the embodiment of the present invention is achieved in that
The embodiment of the invention provides a kind of first in first out data buffers, including input port, output port, further include
First cache unit, the second cache unit, third cache unit, first control unit, the second control unit and switch unit,
In:
First cache unit, for storing the data inputted by input port；
Second cache unit, for storing the data exported by output port；
The third cache unit is the single port random access memory that data bit width is DW*n, passes through second for storing
The data of control unit input or output, the n are the natural number more than or equal to 2, and DW is first in first out data buffer
Data bit width；
The first control unit for reading the data of the first cache unit, and is written in the second cache unit；
Second control unit for reading the data of the first cache unit, and is written in third cache unit；When
When the state data memory of two cache units is non-full state, the data of third cache unit are read, and it is single that the second caching is written
In member；
The switch unit, for obtaining state, the reading and writing data state of the second control unit and of input port
The state data memory of one cache unit and the second cache unit；And according to the state of acquisition, opens first control unit and close
The second control unit is closed, or closes first control unit and opens the second control unit.
Further, the switch unit opens first control unit and closes the second control list according to the state of acquisition
Member, or close first control unit and open the second control unit, it specifically includes:
After the first in first out data buffer powers on, opens the first control unit and close the second control list
Member；
When the state data memory of first cache unit and second cache unit is full state and current defeated
When inbound port has data input, closes the first control unit and open second control unit；
When the data reading that the state data memory of second cache unit is non-full state and second control unit
When write state is dummy status, opens the first control unit and close second control unit.
Further, second control unit includes writing control unit, read-write arbitration unit and reading control unit,
In,
Described to write control unit, for generating write signal, the write signal is used to read the number of first cache unit
According to, and be written in the third cache unit；
The reading control unit, for obtaining the state data memory of second cache unit, when second caching
When the state data memory of unit is non-full state, read signal is generated, the read signal is for reading the third cache unit
Data, and be written in second cache unit；
The read-write arbitration unit, for generation read signal and write signal arbitrate.
Further, first cache unit is the register that data bit width is DW, storage depth is (n-1).
Further, the third cache unit is that the single port that data bit width is DW*2, storage depth is MD/2 is deposited at random
Access to memory, the MD are the storage depth of first in first out data buffer；First cache unit be data bit width be DW,
The register that storage depth is 1.
Further, second cache unit is the register that data bit width is DW, storage depth is 4.
The embodiment of the invention also provides a kind of data cached methods, include the following steps:
First in first out data buffer receives the data of input port write-in, stores to the first cache unit；
First in first out data buffer obtains the state of input port, the reading and writing data state of the second control unit and the
The state data memory of one cache unit and the second cache unit；According to the state of acquisition, opens first control unit and close
Second control unit, or close first control unit and open the second control unit；
When opening first control unit and closing the second control unit, first in first out data buffer reads the first caching
The data of unit, and be written in the second cache unit；
When closing first control unit and opening the second control unit, first in first out data buffer reads the first caching
The data of unit, and be written in third cache unit, the third cache unit is that the single port that data bit width is DW*n is deposited at random
Access to memory, the n are the natural number more than or equal to 2, and DW is the data bit width of first in first out data buffer；When second slow
When the state data memory of memory cell is non-full state, the data of third cache unit are read, and be written in the second cache unit；
The first in first out data buffer reads the data stored in the second cache unit by output port.
Further, the state according to acquisition opens first control unit and closes the second control unit, Huo Zheguan
The step of closing first control unit and opening the second control unit, specifically includes:
After the first in first out data buffer powers on, opens the first control unit and close the second control list
Member；
When the state data memory of first cache unit and second cache unit is full state and input terminal
When mouth has data input, closes the first control unit and open second control unit；
When the data reading that the state data memory of second cache unit is non-full state and second control unit
When write state is dummy status, opens the first control unit and close second control unit.
Further, the third cache unit is that the single port that data bit width is DW*2, storage depth is MD/2 is deposited at random
Access to memory, the MD are the storage depth of first in first out data buffer；First cache unit be data bit width be DW,
The register that storage depth is 1.
Further, second cache unit is the register that data bit width is DW, storage depth is 4.
Technical solution of the present invention has the following beneficial effects:
First in first out data buffer provided by the invention and data cached method, by using more haplotype data bit wides
Single port RAM time-sharing multiplex, and by the state of switch unit control first control unit and the second control unit, and then switch number
According to transmission channel, the area of chip is efficiently reduced, reduces the cost of chip, improves the competitiveness of chip.
Detailed description of the invention
The drawings described herein are used to provide a further understanding of the present invention, constitutes part of this application, this hair
Bright illustrative embodiments and their description are used to explain the present invention, and are not constituted improper limitations of the present invention.In the accompanying drawings:
Fig. 1 is traditional large capacity synchronization fifo structural schematic diagram；
Fig. 2 is a kind of structural schematic diagram of first in first out data buffer of first embodiment of the invention；
Fig. 3 is a kind of structural schematic diagram of first in first out data buffer of second embodiment of the invention；
Fig. 4 is the flow diagram of the data cached method of one kind of the embodiment of the present invention.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing to the present invention
Embodiment be described in detail.It should be noted that in the absence of conflict, in the embodiment and embodiment in the application
Feature can mutual any combination.
As shown in Fig. 2, a kind of first in first out data buffer according to the present invention, including input port, output port, also
It is single including the first cache unit, the second cache unit, third cache unit, first control unit, the second control unit and switching
Member, in which:
First cache unit, for storing the data inputted by input port；
Second cache unit, for storing the data exported by output port；
The third cache unit is the single port random access memory that data bit width is DW*n, passes through second for storing
The data of control unit input or output, the n are the natural number more than or equal to 2, and DW is first in first out data buffer
Data bit width；
The first control unit for reading the data of the first cache unit, and is written in the second cache unit；
Second control unit for reading the data of the first cache unit, and is written in third cache unit；When
When the state data memory of two cache units is non-full state, the data of third cache unit are read, and it is single that the second caching is written
In member；
The switch unit, for obtaining state, the reading and writing data state of the second control unit and of input port
The state data memory of one cache unit and the second cache unit；And according to the state of acquisition, opens first control unit and close
The second control unit is closed, or closes first control unit and opens the second control unit.
It should be noted that the first control unit and the second control unit are in the data for reading the first cache unit
Before, first obtain the state data memory of the first cache unit, the data storage shape of the state of input port and the second cache unit
State, when switch unit opening first control unit and (i.e. data transmission path is input port, first to the second control unit of closing
Cache unit, first control unit, the second cache unit, output port) when, if the state data memory of the first cache unit is
Non-empty, and the state data memory of the second cache unit is non-full, generation read/write address and read-write reading the first caching list
The data of member are write in the second cache unit；It closes first control unit when switch unit and opens the second control unit and (count
It is input port, the first cache unit, the second control unit, third cache unit, the second control unit, second according to transmission channel
Cache unit, output port) when, if the state data memory of the first cache unit has data input for full, input port, produce
Raw read/write address and read-write read the data of the first cache unit, are written in third cache unit.First control is single
Member, the second control unit and switch unit can be realized by existing combination and sequential logical circuit.
Further, the switch unit opens first control unit and closes the second control list according to the state of acquisition
Member, or close first control unit and open the second control unit, it specifically includes:
After the first in first out data buffer powers on, opens the first control unit and close the second control list
Member；
When the state data memory of the first cache unit and the second cache unit is full state and input port has data
When input, closes first control unit and open the second control unit；
When the reading and writing data state that the state data memory of the second cache unit is non-full state and the second control unit is
When dummy status, opens first control unit and close the second control unit.
In an embodiment of the present invention, after first in first out data buffer electrification reset, switch unit opens the first control
Unit simultaneously closes the second control unit, the data of input is read from the first cache unit, and be written in the second cache unit, this
When output port may be dummy status, it is also possible to be non-null states, when the second cache unit do not write it is full before, all the time by the
One control unit reads and writes data；
After the second cache unit is write completely, the data newly inputted are first cached in the first cache unit；
If there are also data to input, switch unit generates channel switching signal, closes first control unit and opens
Second control unit, reads the data of the first cache unit, and is written in third cache unit；
The state data memory for obtaining the second cache unit, when having data space in the second cache unit, the
Two control units read data from third cache unit, and the data of reading are written in the second cache unit；
When the data in third cache unit are all run through and do not have data to write in third cache unit at this time, cut
Change unit generate channel switching signal, open first control unit simultaneously close the second control unit, then continue according to storage and
Input condition repeats above judgement and channel switching automatically.
Further, with reference to Fig. 3, second control unit includes writing control unit, read-write arbitration unit and reading to control
Unit, wherein
Control unit is write, for generating write signal, the write signal is used to read the data of the first cache unit, and is written
In third cache unit；
Control unit is read, for obtaining the state data memory of second cache unit, when the second state data memory
When for non-full state, read signal is generated, the read signal is used to read the data of third cache unit, and it is single that the second caching is written
In member；
Read and write arbitration unit, for generation read signal and write signal arbitrate, to avoid to third cache unit
Read/write conflict.
It is worth noting that third cache unit of the invention uses more times since single port RAM can not be written and read simultaneously
The single port RAM time-sharing multiplex of data bit width (data of the more haplotype data bit wides of 1 clock cycle Writing/Reading), is read and write using timeslice
Data exchange the time for bit wide, solve the problems, such as FIFO while needing to read and write.Two parts logic is read and write additionally, due to single port RAM
Be it is independent, can lead to the problem of read/write conflict, read-write arbitration unit is introduced in the present invention to solve the problems, such as read/write conflict.
Further read-write arbitration unit, which uses, writes preference strategy.
Further, the switch unit writes the reading and writing data state of control unit and reading control unit by acquisition to obtain
The reading and writing data state for taking second control unit, when the reading and writing data state for writing control unit is full state, the second control
The reading and writing data state of unit processed is full state (at this point, the state data memory of third cache unit is also full state)；Work as reading
When the reading and writing data state of control unit is dummy status, the reading and writing data state of the second control unit is dummy status (at this point, third
The reading and writing data state of cache unit is also dummy status).
Further, it with reference to Fig. 3, is equipped between second cache unit and first control unit, the second control unit
Data selector, the data selector are used for the state according to first control unit and the second control unit, from the first control
The data of the second cache unit of selection write-in in unit or the second control unit.
Further, first cache unit is the register that data bit width is DW, storage depth is (n-1).
It should be noted that buffer memory capacity is equal to the product of data bit width and storage depth, the data bit width, storage are deep
Degree respectively refers to the number of bits of write-once or reading, can at most store the data volume of how many a data bit widths.
In an of the invention specific embodiment, the third cache unit be data bit width be DW*2, storage depth MD/
2 single port random access memory ram, the MD are the storage depth of first in first out data buffer；First cache unit is
The register that data bit width is DW, storage depth is 1.
In the of the invention specific embodiment, second cache unit be data bit width be DW, storage depth is 4 to post
Storage.
Specifically, due to the data bit width of the second cache unit is DW and the bit wide of third cache unit single port RAM is DW*
2, therefore can guarantee that at least one is used to read data from RAM in two clock cycle；Due to depositing for the second cache unit
Storing up depth is 4, and data can be read with the speed of 1 clock cycle, two DW data bit widths, and be write in the second cache unit,
In this way in the case where input terminal no data, data quickly removing from third cache unit to the second cache unit may be implemented
Fortune saves the time to guarantee access control unit in switch data circulation road, and the data of first in first out data buffer export
Continuity.
As shown in figure 4, the method that one kind according to the present invention is data cached, includes the following steps:
Step 401: first in first out data buffer receives the data of input port write-in, stores to the first cache unit；
Step 402: first in first out data buffer obtains the reading and writing data shape of the state of input port, the second control unit
The state data memory of state and the first cache unit and the second cache unit；
Step 403: according to the state of acquisition, opening first control unit and simultaneously close the second control unit, or close the
One control unit simultaneously opens the second control unit；
When opening first control unit and closing the second control unit, first in first out data buffer reads the first caching
The data of unit, and be written in the second cache unit；
When closing first control unit and opening the second control unit, first in first out data buffer reads the first caching
The data of unit, and be written in third cache unit, the third cache unit is that the single port that data bit width is DW*n is deposited at random
Access to memory, the n are the natural number more than or equal to 2, and DW is the data bit width of first in first out data buffer；When second slow
When the state data memory of memory cell is non-full state, the data of third cache unit are read, and be written in the second cache unit；
Step 404: first in first out data buffer reads the data stored in the second cache unit by output port.
Further, it according to the state of acquisition in the step 403, opens first control unit and closes the second control list
Member, or the step of closing first control unit and opening the second control unit, specifically include:
After the first in first out data buffer powers on, opens the first control unit and close the second control list
Member；
When the state data memory of the first cache unit and the second cache unit is full state and input port has data
When input, closes first control unit and open the second control unit；
When the reading and writing data state that the state data memory of the second cache unit is non-full state and the second control unit is
When dummy status, opens first control unit and close the second control unit.
In an embodiment of the present invention, after first in first out data buffer electrification reset, switch unit opens the first control
Unit simultaneously closes the second control unit, the data of input is read from the first cache unit, and be written in the second cache unit, this
When output port may be dummy status, it is also possible to be non-null states, when the second cache unit do not write it is full before, all the time by the
One control unit reads and writes data；
After the second cache unit is write completely, the data newly inputted are first cached in the first cache unit；
If there are also data to input, switch unit generates channel switching signal, closes first control unit and opens
Second control unit, reads the data of the first cache unit, and is written in third cache unit；
The state data memory for obtaining the second cache unit, when having data space in the second cache unit, the
Two control units read data from third cache unit, and the data of reading are written in the second cache unit；
When the data in third cache unit are all run through and do not have data to write in third cache unit at this time, cut
Change unit generate channel switching signal, open first control unit simultaneously close the second control unit, then continue according to storage and
Input condition repeats above judgement and channel switching automatically.
Further, first cache unit is the register that data bit width is DW, storage depth is (n-1).
Further, the third cache unit is that the single port that data bit width is DW*2, storage depth is MD/2 is deposited at random
Access to memory RAM, MD are the storage depth of first in first out data buffer；First cache unit is that data bit width is DW, stores
The register that depth is 1.
It should be noted that third cache unit of the invention uses the single port RAM time-sharing multiplex of more haplotype data bit wides, adopt
Data are read and write with timeslice, the time is exchanged for bit wide, FIFO is solved the problems, such as while needing to read and write, utilize read-write arbitration mechanism solution
Certainly read/write conflict problem.Read-write arbitration mechanism of the invention uses and writes preference strategy.
Further, second cache unit is the register that data bit width is DW, storage depth is 4.
Specifically, due to the data bit width of the second cache unit is DW and the bit wide of third cache unit single port RAM is DW*
2, therefore can guarantee that at least one is used to read data from RAM in two clock cycle；Due to depositing for the second cache unit
Storing up depth is 4, and data can be read with the speed of 1 clock cycle, two DW data bit widths, and be write in the second cache unit,
In this way in the case where input terminal no data, data quickly removing from third cache unit to the second cache unit may be implemented
Fortune saves the time to guarantee access control unit in switch data circulation road, and the data of first in first out data buffer export
Continuity.
First in first out data buffer according to the present invention, area have apparent compared to traditional high-capacity FIFO
Advantage, by taking storage depth * data width is the FIFO of 800x128 as an example, the storage depth * data width of the first cache unit is
1*128, the storage depth * data width of the second cache unit are 4*128, the storage depth * data width of third cache unit
For 400*256.If using pseudo-double port RAM, area 52145um2If can be used using the present invention
The single port RAM of 400x256 solves the problems, such as, area 22825um2, 56% area can be saved, it is contemplated that is newly increased is outer
Area (the 1405um of portion's logic2), it still is able to save 53.5% area, and then can reduce the cost of chip, improves core
The competitiveness of piece.
Those of ordinary skill in the art will appreciate that all or part of the steps in the above method can be instructed by program
Related hardware is completed, and described program can store in computer readable storage medium, such as read-only memory, disk or CD
Deng.Optionally, one or more integrated circuits also can be used to realize, accordingly in all or part of the steps of above-described embodiment
Ground, each module/unit in above-described embodiment can take the form of hardware realization, can also use the shape of software function module
Formula is realized.The present invention is not limited to the combinations of the hardware and software of any particular form.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of first in first out data buffer, including input port, output port, which is characterized in that further include the first caching
Unit, the second cache unit, third cache unit, first control unit, the second control unit and switch unit, in which:
First cache unit, for storing the data inputted by input port；
Second cache unit, for storing the data exported by output port；
The third cache unit is the single port random access memory that data bit width is DW*n, for storing through the second control
The data of unit input or output, the n are the natural number more than or equal to 2, and DW is the data of first in first out data buffer
Bit wide；
The first control unit for reading the data of the first cache unit, and is written in the second cache unit；
Second control unit for reading the data of the first cache unit, and is written in third cache unit；When second slow
When the state data memory of memory cell is non-full state, the data of third cache unit are read, and be written in the second cache unit；
The switch unit, it is slow for obtaining the state of input port, the reading and writing data state of the second control unit and first
The state data memory of memory cell and the second cache unit；And according to the state of acquisition, opens first control unit and close the
Two control units, or close first control unit and open the second control unit.
2. first in first out data buffer according to claim 1, which is characterized in that the switch unit is according to acquisition
State, opening first control unit simultaneously close the second control unit, or close first control unit and open the second control list
Member specifically includes:
After the first in first out data buffer powers on, opens the first control unit and close second control unit；
When the state data memory of first cache unit and second cache unit is full state and current input terminal
When mouth has data input, closes the first control unit and open second control unit；
When the reading and writing data shape that the state data memory of second cache unit is non-full state and second control unit
When state is dummy status, opens the first control unit and close second control unit.
3. first in first out data buffer according to claim 1, which is characterized in that second control unit includes writing
Control unit, read-write arbitration unit and reading control unit, wherein
Described to write control unit, for generating write signal, the write signal is used to read the data of first cache unit, and
It is written in the third cache unit；
The reading control unit, for obtaining the state data memory of second cache unit, when second cache unit
State data memory when being non-full state, generate read signal, the read signal is used to read the number of the third cache unit
According to, and be written in second cache unit；
The read-write arbitration unit, for generation read signal and write signal arbitrate.
4. first in first out data buffer according to claim 1, which is characterized in that first cache unit is data
The register that bit wide is DW, storage depth is (n-1).
5. first in first out data buffer according to claim 1, which is characterized in that the third cache unit is data
The single port random access memory that bit wide is DW*2, storage depth is MD/2, the MD are depositing for first in first out data buffer
Store up depth；First cache unit is the register that data bit width is DW, storage depth is 1.
6. first in first out data buffer according to claim 1, which is characterized in that second cache unit is data
The register that bit wide is DW, storage depth is 4.
7. a kind of data cached method, which comprises the steps of:
First in first out data buffer receives the data of input port write-in, stores to the first cache unit；
It is slow that first in first out data buffer obtains the state of input port, the reading and writing data state of the second control unit and first
The state data memory of memory cell and the second cache unit；According to the state of acquisition, opens first control unit and close second
Control unit, or close first control unit and open the second control unit；
When opening first control unit and closing the second control unit, first in first out data buffer reads the first cache unit
Data, and be written the second cache unit in；
When closing first control unit and opening the second control unit, first in first out data buffer reads the first cache unit
Data, and be written in third cache unit, the third cache unit is that the single port arbitrary access that data bit width is DW*n is deposited
Reservoir, the n are the natural number more than or equal to 2, and DW is the data bit width of first in first out data buffer；When the second caching is single
When the state data memory of member is non-full state, the data of third cache unit are read, and be written in the second cache unit；
The first in first out data buffer reads the data stored in the second cache unit by output port.
8. the method according to the description of claim 7 is characterized in that the state according to acquisition, opens first control unit
And the second control unit is closed, or the step of closing first control unit and opening the second control unit, it specifically includes:
After the first in first out data buffer powers on, opens the first control unit and close second control unit；
When the state data memory of first cache unit and second cache unit is full state and input port has
When data input, closes the first control unit and open second control unit；
When the reading and writing data shape that the state data memory of second cache unit is non-full state and second control unit
When state is dummy status, opens the first control unit and close second control unit.
9. the method according to the description of claim 7 is characterized in that the third cache unit is that data bit width is DW*2, deposits
The single port random access memory that depth is MD/2 is stored up, the MD is the storage depth of first in first out data buffer；Described
One cache unit is the register that data bit width is DW, storage depth is 1.
10. the method according to the description of claim 7 is characterized in that second cache unit is that data bit width is DW, stores
The register that depth is 4.
Priority Applications (1)
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