CN104461971A - Data collecting control system and method - Google Patents
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- CN104461971A CN104461971A CN201410689052.4A CN201410689052A CN104461971A CN 104461971 A CN104461971 A CN 104461971A CN 201410689052 A CN201410689052 A CN 201410689052A CN 104461971 A CN104461971 A CN 104461971A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
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Abstract
The invention provides a data collecting control system and method. The system and method are used for improving a data transmission mechanism and improving data transmission efficiency. According to the technical scheme, original data are received, and the original data are collected from a data source through a control collecting device; the original data are pre-processed through a preprocessing buffering unit; the pre-processed data are written into a synchronous FIFO unit; the data in the synchronous FIFO unit are transferred into an external single-port RAM; when the used capacity of the single-port RAM reaches preset conditions, an interrupt signal is sent to an ARM, so that the ARM reads the data in the single-port RAM, and the single-port RAM supports the ARM to directly have access to the single-port RAM through an EIM interface. By means of the technical scheme, the utilization rate of RAM resources of the system can be increased, and therefore data collecting and transmission efficiency is improved.
Description
Technical field
The present invention relates to technical field of data transmission, be specifically related to a kind of data acquisition control system and method.
Background technology
FPGA(Field Programmable Gate Array, field-programmable gate array) programmable, its storer carried can be used in the realization of the buffering of data, transmission and control protocol.ARM(Acorn RISC Machine) embedded platform can operation system, flexible in programming, is easy to realize data transmission, process, and ARM chip carries many general interface, can realize the data communication with the multiple format of external unit, multiple speed.Therefore, the two can combinationally use the core becoming data acquisition control system.
Refer to Fig. 1, the data acquisition control system of prior art comprises: PC(Personal Computer, PC) 11, ARM12, FPGA13, one group of ping-pong ram (Random Access Memory, random access memory) 14 and data source 15, particularly, FPGA13 also comprises: RAM controller 131, asynchronous FIFO (First Input First Output, first in first out) 132 and pre-service buffering 133.Wherein, connected by Ethernet interface between PC11 and ARM12, ARM12 is by EIM(External Interface Module, external interface module) interface is connected with the asynchronous FIFO 132 of FPGA13, ping-pong ram 14, data source 15 cushion 133 communicate to connect with the RAM controller 131 of FPGA13, pre-service respectively, and RAM controller 131 also cushions 133 with asynchronous FIFO 132, pre-service respectively and communicates to connect.PC11 is as human-computer interaction device.The pre-service of FPGA13 cushions the data that 133 buffer memorys gather from data source 15, and data are write one of them in ping-pong ram 14 by RAM controller 131, when writing full, ARM12 takes data away via RAM controller 131 and asynchronous FIFO 132, and another simultaneously in ping-pong ram 14 is for writing the data of subsequent acquisition.
But in technique scheme, two RAM capacity in ping-pong ram are identical, the reading rate that ARM holds is far above the acquisition rate of data source, the RAM causing being read is read sky by too early, needs to wait for that the RAM be written into writes and completely just exchanges, waste a large amount of RAM resource.
Summary of the invention
In order to solve the problem, the invention provides a kind of data acquisition control system and method, for improving data transmission mechanism, improve data transmission efficiency.By implementing technical solution of the present invention, the utilization factor of system to RAM resource can be improved, thus improve the efficiency of data acquisition and transmission.
A kind of data acquisition control method, comprising:
Receive raw data, described raw data gathers from data source by controlling collecting device;
Pre-service buffer cell carries out pre-service to described raw data;
By pretreated data write synchronization fifo unit;
Data transcription in described synchronization fifo unit is entered outside single port RAM;
When the capacity of use of described single port RAM reaches pre-conditioned, send look-at-me to ARM, make described ARM read data in described single port RAM, described single port RAM supports that described ARM is directly accessed it by EIM interface.
A kind of data acquisition control system, comprising: ARM, FPGA and single port RAM, described FPGA comprises: RAM controller, synchronization fifo unit and pre-service buffer cell,
Described ARM is connected by EIM interface with described single port RAM controller, and described RAM controller is connected with described single port RAM, described synchronization fifo unit communication, and described synchronization fifo unit and described pre-service buffer cell communicate to connect;
Described FPGA performs following operation:
Receive raw data, described raw data gathers from data source by controlling collecting device;
Described pre-service buffer cell is utilized to carry out pre-service to described raw data;
Pretreated data are write described synchronization fifo unit;
By described RAM controller, the data transcription in described synchronization fifo unit is entered outside single port RAM;
When the capacity of use of described single port RAM reaches pre-conditioned, send look-at-me to ARM, make described ARM read data in described single port RAM, described single port RAM supports that described ARM is directly accessed it by EIM interface.
The invention has the beneficial effects as follows, the data gathered write in single port RAM by FPGA, and this single port RAM supports that ARM is directly accessed it by EIM interface, when the capacity of use of this single port RAM reaches pre-conditioned, FPGA sends look-at-me to ARM, makes ARM directly read the data in single port RAM, after pending data runs through by EIM interface, ARM sends look-at-me to FPGA, repeats aforementioned data acquisition operations.Meanwhile, the synchronization fifo unit of FPGA inside plays certain data buffer storage effect.By implementing technical solution of the present invention, the utilization factor of system to RAM resource can be improved, thus improve the efficiency of data acquisition and transmission.
Accompanying drawing explanation
Fig. 1 is the data acquisition control system structural drawing of prior art;
Fig. 2 is a kind of data acquisition control system structural drawing of the embodiment of the present invention;
Fig. 3 is a kind of data acquisition control method flow diagram of the embodiment of the present invention;
Fig. 4 is the another kind of data acquisition control system structural drawing of the embodiment of the present invention;
Fig. 5 is the another kind of data acquisition control method flow diagram of the embodiment of the present invention;
Fig. 6 is the another kind of data acquisition control method flow diagram of the embodiment of the present invention.
Embodiment
Below in conjunction with the Figure of description in the present invention, be clearly and completely described the technical scheme in invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
First embodiment of the invention will be described in detail to a kind of data acquisition control system, and the data acquisition control system concrete structure described in the present embodiment refers to Fig. 2, comprising:
ARM20, FPGA21 and single port RAM22.
FPGA21 specifically comprises: RAM controller 211, synchronization fifo unit 212 and pre-service buffer cell 213.
Wherein, ARM20 is connected by EIM interface with single port RAM controller 211, and RAM controller 211 and single port RAM22, synchronization fifo unit 212 communicate to connect, and synchronization fifo unit 212 and pre-service buffer cell 213 communicate to connect.
In the present embodiment, ARM20, as data processing core, carries out the process such as computing for the data gathered native system.FPGA21 is used for realizing a series of logic control function, comprise the steering logic to external control collecting device, and raw data acquisition, pre-service and unloading is to the function of single port RAM22.
Preferably, the data acquisition control system described in the present embodiment is applied in cellanalyzer.
Second embodiment of the invention will be described in detail to a kind of data acquisition control method, and the data acquisition control method described in the present embodiment is applicable to the system described in the first embodiment, and its idiographic flow refers to Fig. 3, comprises step:
301, FPGA receives raw data.
FPGA21 connection control collecting device, controls to send its raw data gathered to FPGA21 after collecting device gathers raw data from data source.FPGA21 receives raw data, and raw data gathers from data source by controlling collecting device.
302, FPGA utilizes pre-service buffer cell to carry out pre-service to raw data.
FPGA21 utilizes pre-service buffer cell 213 pairs of raw data of its inside to carry out pre-service, and pretreated raw data can meet follow-up read-write demand.
303, FPGA is by pretreated data write synchronization fifo unit.
Pretreated data are write the synchronization fifo unit 212 of its inside by FPGA21.
304, the data in synchronization fifo unit are write outside single port RAM by FPGA.
Data transcription in synchronization fifo unit 212 enters in outside single port RAM22 by FPGA21.Wherein, single port RAM22 temporarily stores the data treating ARM20 process in a large number.
305, when the capacity of use of single port RAM reaches pre-conditioned, FPGA sends look-at-me to ARM, makes the data in ARM reading single port RAM.
The embodiment of the present invention introduces interrupt mechanism, when the capacity of use of single port RAM22 reaches pre-conditioned, is generally and reaches 100%, FPGA21 and send look-at-me to ARM20, and this look-at-me is used to indicate ARM20 and reads all data in single port RAM22.Wherein, single port RAM22 supports that in ardware feature ARM20 is directly accessed it by EIM interface.
When the capacity of use of single port RAM22 does not reach pre-conditioned, then FPGA21 continues data to write in single port RAM22.
In the present embodiment, the data gathered write in single port RAM22 by FPGA21, and this single port RAM22 supports that ARM20 is directly accessed it by EIM interface, when the capacity of use of this single port RAM22 reaches pre-conditioned, FPGA21 sends look-at-me to ARM20, makes ARM20 directly read the data in single port RAM22, after pending data runs through by EIM interface, ARM sends look-at-me to FPGA, repeats aforementioned data acquisition operations.Meanwhile, the synchronization fifo unit 212 of FPGA21 inside plays certain data buffer storage effect.By implementing technical solution of the present invention, the utilization factor of system to RAM resource can be improved, thus improve the efficiency of data acquisition and transmission.
Preferably, the data acquisition control method described in the present embodiment is applied in cellanalyzer.
Third embodiment of the invention will be described in detail to another kind of data acquisition control system, and the data acquisition control system concrete structure described in the present embodiment refers to Fig. 4, comprising:
ARM40, FPGA41, single port RAM42 and control collecting device 43.
FPGA41 specifically comprises: RAM controller 411, synchronization fifo unit 412, pre-service buffer cell 413 and control register 414.
Wherein, ARM40 is connected by EIM interface with single port RAM controller 411, RAM controller 411 and single port RAM42, synchronization fifo unit 412 communicate to connect, synchronization fifo unit 412 and pre-service buffer cell 413 communicate to connect, control register 414 is connected with ARM40 by SPI interface, and control register 414 also communicates to connect with control collecting device 43.
In the present embodiment, ARM40, as data processing core, carries out the process such as computing, also for controlling the operation of native system for the data gathered native system.FPGA41 is used for realizing a series of logic control function, comprise the steering logic to external control collecting device 43, and raw data acquisition, pre-service and unloading is to the function of single port RAM42.
Preferably, the data acquisition control system described in the present embodiment is applied in cellanalyzer.
Fourth embodiment of the invention will be described in detail to another kind of data acquisition control method, and the data acquisition control method described in the present embodiment is applicable to the system described in the 3rd embodiment, and its idiographic flow refers to Fig. 5, comprises step:
501, FPGA receives raw data.
FPGA41 connection control collecting device 43, controls to send its raw data gathered to FPGA41 after collecting device 43 gathers raw data from data source.FPGA41 receives raw data, and raw data gathers from data source by controlling collecting device 43.
502, FPGA utilizes pre-service buffer cell to carry out pre-service to raw data.
FPGA41 utilizes pre-service buffer cell 413 pairs of raw data of its inside to carry out pre-service, and pretreated raw data can meet follow-up read-write and processing demands.
503, FPGA is by pretreated data write synchronization fifo unit.
Pretreated data are write the synchronization fifo unit 412 of its inside by FPGA41.
504, the data in synchronization fifo unit are write outside single port RAM by FPGA.
Data transcription in synchronization fifo unit 412 enters in outside single port RAM42 by FPGA41.Wherein, single port RAM42 temporarily stores the data treating ARM40 process in a large number.
505, when the capacity of use of single port RAM reaches pre-conditioned, FPGA sends look-at-me to ARM, makes the data in ARM reading single port RAM.
The embodiment of the present invention introduces interrupt mechanism, when the capacity of use of single port RAM42 reaches pre-conditioned, is generally and reaches 100%, FPGA41 and send look-at-me to ARM40, and this look-at-me is used to indicate ARM40 and reads all data in single port RAM42.Wherein, single port RAM42 supports that in ardware feature ARM40 is directly accessed it by EIM interface.
When the capacity of use of single port RAM42 does not reach pre-conditioned, then FPGA41 continues data to write in single port RAM42.
506, when sending look-at-me to ARM, FPGA stops the operation data transcription in synchronization fifo unit being entered outside single port RAM.
When FPGA41 sends look-at-me to ARM40, FPGA41 stops the operation that the data transcription in synchronization fifo unit 412 is entered outside single port RAM42 by this simultaneously.This cooperation ARM40 reads away data from single port RAM42.When this step performs, synchronization fifo unit 412 plays certain data buffer storage effect, to ensure that controlling collecting device 43 continues operation.
In the present embodiment, step 505 and step 506 synchronously perform.
507, when ARM runs through the data in single port RAM, FPGA receives the look-at-me that ARM sends.
When ARM40 runs through the data in single port RAM42, ARM40 sends another look-at-me to FPGA41, and this look-at-me is used to indicate FPGA41 and recovers to write data to single port RAM42.Accordingly, FPGA41 receives the look-at-me that ARM40 sends.
508, FPGA recovers the operation data transcription in synchronization fifo unit being entered outside single port RAM.
FPGA41, after the look-at-me receiving ARM40 transmission, recovers according to the instruction of this look-at-me the operation data transcription in synchronization fifo unit 412 being entered outside single port RAM42.
In the present embodiment, the data gathered write in single port RAM42 by FPGA41, and this single port RAM42 supports that ARM40 is directly accessed it by EIM interface, when the capacity of use of this single port RAM42 reaches pre-conditioned, FPGA41 sends look-at-me to ARM40, makes ARM40 directly read the data in single port RAM42, after pending data runs through by EIM interface, ARM sends look-at-me to FPGA, repeats aforementioned data acquisition operations.Meanwhile, the synchronization fifo unit 412 of FPGA41 inside plays certain data buffer storage effect.By implementing technical solution of the present invention, the utilization factor of system to RAM resource can be improved, thus improve the efficiency of data acquisition and transmission.
Preferably, the data acquisition control method described in the present embodiment is applied in cellanalyzer.
Fifth embodiment of the invention will be described in detail to another kind of data acquisition control method, and the data acquisition control method described in the present embodiment is applicable to the system described in the 3rd embodiment, and its idiographic flow refers to Fig. 6, comprises step:
601, FPGA is by the instruction message of SPI interface ARM transmission.
The instruction message that FPGA41 is sent by ARM40 by SPI interface.Wherein, instruction message gathers raw data for controlling collecting device 43 from data source.
In embodiments of the present invention, control collecting device 43 and can comprise multiple ingredient, as comprised opertaing device and collecting device, opertaing device is the physical unit performing concrete spatial displacements, as gearshift, actuator, repeat no more here, collecting device is data acquisition facility, as analog to digital converter, operational amplifier, temperature sensor, pressure transducer, photoelectric sensor, also repeat no more here.Correspondingly, instruction message also can comprise two types, and as steering order and acquisition instructions, steering order performs concrete spatial displacements for controlling this opertaing device, and acquisition instructions is used to indicate this collecting device execution collection action.
602, FPGA utilizes this instruction message of control register buffer memory.
FPGA41, after reception instruction message, utilizes this instruction message of control register 414 buffer memory, to carry out the pre-service such as parsing to instruction message.Same as the prior art to the pretreatment operation process of instruction message described in this step, repeats no more here.
603, FPGA forwards instruction message to control collecting device, makes to control collecting device and performs data acquisition operations.
FPGA41 forwards described instruction message to control collecting device 43, makes described control collecting device 43 perform data acquisition operations.Control collecting device 43 after execution data acquisition operations, the process step that system will perform described by fourth embodiment of the invention, repeats no more here.
604, FPGA receives the status information controlling collecting device and send.
In the process step process that system performs described by fourth embodiment of the invention, FPGA43 can also receive the status information controlling collecting device 43 and send simultaneously.Wherein, status information is used to indicate the running status controlling collecting device 43.
605, FPGA sends described status information by SPI interface to ARM.
FPGA41 sends status information by SPI interface to ARM40.In the prior art, the multiplexing EIM interface of data, instruction message and status information that control collecting device gathers transmits, and this multiplexing data of collection and the various types of messages of causing cannot be transmitted simultaneously, and real-time is poor.In embodiments of the present invention, the low speed data such as instruction message, status information uses SPI interface to transmit, and belong to high-speed data from the data of data source collection, EIM interface is then used to transmit, low speed data and high-speed data use two different designated lanes to transmit respectively, compared to compound use EIM passage of the prior art, more can ensure system data acquisition and control monitoring perform simultaneously and do not interfere with each other, real-time.
Preferably, the data acquisition control method described in the present embodiment is applied in cellanalyzer.
A kind of data acquisition control system provided the embodiment of the present invention above and method are described in detail, but the explanation of above embodiment just understands structure of the present invention and core concept thereof for helping, and should not be construed as limitation of the present invention.Those skilled in the art are in the technical scope that the present invention discloses, and the change that can expect easily or replacement, all should be encompassed within protection scope of the present invention.
Claims (10)
1. a data acquisition control method, is characterized in that, comprising:
Receive raw data, described raw data gathers from data source by controlling collecting device;
Pre-service buffer cell carries out pre-service to described raw data;
By pretreated data write synchronization fifo unit;
Data transcription in described synchronization fifo unit is entered outside single port RAM;
When the capacity of use of described single port RAM reaches pre-conditioned, send look-at-me to ARM, make described ARM read data in described single port RAM, described single port RAM supports that described ARM is directly accessed it by EIM interface.
2. method according to claim 1, is characterized in that, comprises before described reception raw data:
By the instruction message that ARM described in SPI interface sends, described instruction message gathers raw data for controlling described control collecting device from data source;
Utilize instruction message described in control register buffer memory;
Forward described instruction message to described control collecting device, make described control collecting device perform data acquisition operations.
3. method according to claim 2, is characterized in that, described control collecting device comprises after performing data acquisition operations:
Receive the status information that described control collecting device sends, described status information is used to indicate the running status of described control collecting device;
Described status information is sent to described ARM by described SPI interface.
4. the method according to any one of claims 1 to 3, is characterized in that, also comprises:
When sending look-at-me to described ARM, stop described operation data transcription in described synchronization fifo unit being entered outside single port RAM.
5. method according to claim 4, is characterized in that, also comprises:
When described ARM runs through the data in described single port RAM, receive the look-at-me that described ARM sends;
Recover described operation data transcription in described synchronization fifo unit being entered outside single port RAM.
6. a data acquisition control system, comprising: ARM, FPGA and single port RAM, is characterized in that, described FPGA comprises: RAM controller, synchronization fifo unit and pre-service buffer cell,
Described ARM is connected by EIM interface with described single port RAM controller, and described RAM controller is connected with described single port RAM, described synchronization fifo unit communication, and described synchronization fifo unit and described pre-service buffer cell communicate to connect;
Described FPGA performs following operation:
Receive raw data, described raw data gathers from data source by controlling collecting device;
Described pre-service buffer cell is utilized to carry out pre-service to described raw data;
Pretreated data are write described synchronization fifo unit;
By described RAM controller, the data transcription in described synchronization fifo unit is entered outside single port RAM;
When the capacity of use of described single port RAM reaches pre-conditioned, send look-at-me to ARM, make described ARM read data in described single port RAM, described single port RAM supports that described ARM is directly accessed it by EIM interface.
7. system according to claim 6, is characterized in that, described FPGA also comprises: control register,
Described control register is connected with described ARM by SPI interface, and described control register also communicates to connect with described control collecting device;
Described FPGA also performs following operation:
By the instruction message that ARM described in SPI interface sends, described instruction message gathers raw data for controlling described control collecting device from data source;
Utilize instruction message described in described control register buffer memory;
Forward described instruction message to described control collecting device, make described control collecting device perform data acquisition operations.
8. system according to claim 7, is characterized in that, described FPGA also performs following operation:
Receive the status information that described control collecting device sends, described status information is used to indicate the running status of described control collecting device;
Described status information is sent to described ARM by described SPI interface.
9. the system, according to any one of claim 6 to 8, is characterized in that, described FPGA also performs following operation:
When sending look-at-me to described ARM, stop described operation data transcription in described synchronization fifo unit being entered outside single port RAM.
10. system according to claim 9, is characterized in that, described FPGA also performs following operation:
When described ARM runs through the data in described single port RAM, receive the look-at-me that described ARM sends;
Recover described operation data transcription in described synchronization fifo unit being entered outside single port RAM.
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| CN111177059B (en) * | 2019-12-13 | 2020-12-01 | 珠海泰坦新动力电子有限公司 | Data processing method and system based on formation and grading system |
| CN114509965A (en) * | 2021-12-29 | 2022-05-17 | 北京航天自动控制研究所 | Universal heterogeneous robot control platform under complex working conditions |
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