CN112596438A - Real-time reliable waveform data transmission circuit between FPGA and microcontroller - Google Patents
Real-time reliable waveform data transmission circuit between FPGA and microcontroller Download PDFInfo
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
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Abstract
The invention discloses a real-time reliable waveform data transmission circuit between an FPGA and a microcontroller. The circuit comprises a collision detection module, a waveform data candidate storage module, a data clock domain crossing module, a microcontroller interface module and a waveform data acquisition module. The circuit can accurately and reliably transmit the latest waveform data point refreshed in real time in the FPGA to the microcontroller after the microcontroller sends a request for reading the waveform data. On one hand, transmitted waveform data are guaranteed to be the latest acquired data of the FPGA at the current moment, on the other hand, strong real-time performance and high reliability of data transmission are achieved, and the method has a strong engineering application value.
Description
Technical Field
The invention relates to the technical field of data acquisition and communication, in particular to the field of data transmission between an FPGA (field programmable gate array) and a microcontroller.
Background
The main control board card in the control field usually adopts an architecture of an FPGA and a microcontroller, the FPGA usually realizes a series of functions such as waveform acquisition and pin expansion, and the microcontroller realizes a control algorithm and sends out a corresponding control instruction according to real-time acquisition data of the current analog-to-digital converter. This requires that the data in the FPGA be transferred to the microcontroller accurately and quickly.
The microcontroller and the FPGA usually work under two asynchronous clocks (different frequencies or same frequencies and different phases), the FPGA is responsible for continuously receiving waveform acquisition data refreshed by the analog-to-digital converter in real time, and the time when the microcontroller reads the data and the process when the FPGA acquires the data are two asynchronous processes. The measured signal in the field of power system control is usually 50Hz and integral multiple thereof, the analog-to-digital converter generally works in dozens to hundreds of kSPS, and the typical value of the acquisition delay of the analog-to-digital converter is 1us to 10us magnitude.
To achieve waveform data transmission, there are two conventional solutions. One is that after the microcontroller sends a read data request, the FPGA sends a start acquisition signal to the analog-to-digital converter, and the data can be transmitted to the microcontroller after the analog-to-digital converter acquires the data. Although the microcontroller obtains the latest acquired data, the real-time performance is in the order of 1 us-10 us due to the fact that the microcontroller needs to wait for the data acquisition process, and data cross-clock-domain reading errors easily occur.
The other scheme is that data are cached in the FPGA, the number of the caches is from 2 to thousands, and after the microcontroller sends out a reading request, the FPGA transmits the data which are collected in advance and cached to the microcontroller. Although the waveform data points may be delivered to the microcontroller in a relatively fast time, the data transmitted is not the most up-to-date data, but rather the microcontroller requests data that has been collected some time before the data time point. For example, if the sampling rate is 200kSPS, the data is at least 5us old. This affects the accuracy of the control.
Disclosure of Invention
The invention aims to provide a real-time reliable waveform data transmission circuit between an FPGA and a microcontroller, which can solve the problem of real-time property (the real-time property is 0.13us) of data transmission on one hand, and can effectively avoid the situation that data crosses a clock domain to generate errors on the other hand, thereby realizing high-reliability data transmission.
Specifically, the invention provides a real-time reliable waveform data transmission circuit between an FPGA and a microcontroller, which is characterized by comprising: the collision detection module, the candidate storage module of waveform data, the clock domain module is striden to the data, waveform data acquisition module and microcontroller interface module:
the waveform data acquisition module is used for sending a conversion starting signal to an analog-to-digital conversion module at the front end of the waveform data acquisition module, so that the analog-to-digital conversion module performs analog-to-digital conversion on a target signal based on the conversion starting signal, the waveform data acquisition module performs data reception based on the conversion starting signal and generates a data effective signal based on a data refreshing time, and generates a data broadening signal according to the data effective signal, the width of the data broadening signal is greater than that of the data effective signal, and the center of the data broadening signal is aligned with the edge of the data effective signal;
the data clock domain crossing module stores the acquired waveform data based on the data effective signal;
the collision detection module receives the data broadening signals of the waveform data acquisition module and read waveform data signals sent by the microcontroller interface module, and sends two read request signals to the data clock domain crossing module based on the read waveform data signals, wherein the first read request signal is synchronous with the read waveform data signals, and the interval time between the second read request signal and the first read request signal is longer than the effective length of the data broadening signals;
the data clock domain crossing module is used for reading data based on the two reading request signals respectively and sending the read data to the waveform data candidate storage module and storing the read data by adopting different registers;
the collision detection module detects and compares a second-time reading request signal and a data broadening signal, determines whether the second-time reading request signal and the data broadening signal are simultaneously effective, if the second-time reading request signal and the data broadening signal are simultaneously effective, the second-time reading request signal and the data broadening signal are regarded as collision, the collision detection module sends a collision signal to the waveform data candidate storage module, if no collision occurs, the waveform data candidate storage module outputs stored data read for the second time to the microcontroller interface module, and if collision occurs, the waveform data candidate storage module outputs stored data read for the first time to the microcontroller interface module;
the microcontroller interface module returns the data it receives to the microcontroller.
Preferably, the method further comprises the following steps: the FPGA-based clock comprises a clock area 1 and a clock area 2, wherein clocks of the two clock areas have different frequencies or have the same frequency and the same phase, and the FPGA and the microcontroller are respectively positioned in the two clock areas.
Preferably, the data spreading signal width satisfies the following requirements:
broadening signal effective time>N×T1And N/2 XT1>T2；
Wherein N is a positive integer, T1Is the period of 1 clock in the clock region, T2The period of the clock of clock zone 2.
Preferably, the collision detection module, the waveform data candidate storage module, the data clock domain crossing module, the waveform data acquisition module, and the microcontroller interface module are all hardware logic digital circuits that can be described by a hardware description language verilog or VHDL in an FPGA.
Preferably, the data cross-clock domain module is a storage unit which is provided with two clock interfaces and can store and read data.
Preferably, the microcontroller interface module is a hardware logic circuit capable of recognizing read and write requests of the microcontroller and receiving and transmitting data to the microcontroller.
Preferably, the FPGA is programmable hardware.
Preferably, the data formats used by the two registers are the same.
The data cross-clock domain module is a storage unit which is provided with two clock interfaces and can store and read data, such as a double-port RAM, an advanced output type buffer (FIFO) or a logic circuit which is realized by a hardware description language with similar functions.
The FPGA is programmable hardware such as a field programmable gate array and a CPLD, and the microcontroller is a singlechip, an ARM or a DSP.
The invention has the beneficial effects that: after the microcontroller sends a data reading request, the latest waveform data point collected by the analog-to-digital converter is transmitted to the microcontroller in a very short time, so that on one hand, the real-time property (the real-time property is actually measured to be 0.13us) of data transmission can be solved, on the other hand, the condition that errors occur across clock domains of data can be effectively avoided, and high-reliability data transmission is realized. The waveform data transmission mode can effectively improve the control response speed and the control accuracy and has high engineering application value.
Drawings
Fig. 1 is a block diagram of a real-time reliable waveform data transmission circuit between an FPGA and a microcontroller according to the present invention.
FIG. 2 is a timing diagram of waveform data, data valid signal, and data stretching signal according to the present invention.
FIG. 3 is a diagram of an exemplary relationship between a double read request signal and a data stretching signal issued by a collision detection module according to the present invention.
FIG. 4 is a timing diagram for the microcontroller to read waveform data in accordance with the present invention.
FIG. 5 is a schematic diagram of an error in transmitting the latest waveform data without using the present invention.
Fig. 6 is a waveform diagram obtained by performing waveform data transmission using the present invention.
Detailed Description
The following describes embodiments of the present invention with reference to the drawings.
As shown in fig. 1, the real-time reliable waveform data transmission circuit between the FPGA and the microcontroller in this embodiment includes: the device comprises a collision detection module, a waveform data candidate storage module, a data clock domain crossing module, a waveform data acquisition module and a microcontroller interface module.
The analog-to-digital conversion module is arranged at the front end of the waveform data acquisition module. The waveform data acquisition module is used for sending a start conversion signal to an analog-to-digital conversion module at the front end of the waveform data acquisition module, so that the analog-to-digital conversion module performs analog-to-digital conversion on a target signal based on the start conversion signal, the waveform data acquisition module performs data reception based on the start conversion signal and generates a data effective signal based on a data refreshing time, and generates a data stretching signal according to the data effective signal, the width of the data stretching signal is greater than that of the data effective signal, and the center of the data stretching signal is aligned with the edge of the data effective signal. The data cross-clock domain module stores the acquired waveform data based on the data valid signal.
The collision detection module receives the data broadening signal of the waveform data acquisition module and a read waveform data signal sent by the microcontroller interface module, and sends a twice read request signal to the data clock domain crossing module based on the read waveform data signal, wherein the first read request signal is synchronous with the read waveform data signal, and the interval time between the second read request signal and the first read request signal is longer than the effective length of the data broadening signal.
The data cross clock domain module respectively reads data based on two read request signals and sends the read data to the waveform data candidate storage module, different registers are adopted for storage, and the conflict detection module detects and compares the second read request signal and the data stretching signal to determine whether the second read request signal and the data stretching signal are simultaneously effective, and if the two are valid at the same time, the waveform data is considered to be in conflict, and the conflict detection module sends a conflict signal to the waveform data candidate storage module, and if no conflict occurs, the waveform data candidate storage module outputs the stored data read for the second time to the microcontroller interface module, and if a conflict occurs, the waveform data candidate storage module outputs the stored data read for the first time to the microcontroller interface module. The microcontroller interface module returns the data it receives to the microcontroller.
XC7K325T is selected for the FPGA in FIG. 1, and TMS320F28377 is selected for the microcontroller.
The data cross-clock domain module in fig. 1 adopts a dual-port RAM (read and memory) inside the FPGA, the write data port is located in a 125MHz clock domain, the read data port is located in a 100MHz clock domain, and the read/write address of the RAM is fixed to "0", so that real-time waveform data is always stored in the same address and old data is covered when the write data is valid. When the read data is valid, the data is also read from the same address.
The waveform data acquisition module of fig. 1 is a logic state machine hardware circuit that sends a start conversion signal to the analog-to-digital converter every 5us, which results in a sampling rate of 200kSPS for the analog-to-digital converter. Meanwhile, the waveform acquisition module generates a data effective signal, and the effective time of the data effective signal is T1The period is (8ns), and the refreshed waveform data points are aligned, as shown in fig. 2, and sent to the data cross-clock domain module as the enable of the write data port; the waveform acquisition module also generates a data broadening signal, and the data broadening signal width satisfies:
broadening signal effective time>N×T1And N/2 XT1>T2。
Substituting 8ns and 10ns to obtain N >2.5, where N is 3 in this embodiment, i.e. the effective width of the data stretching signal is greater than 30ns, and 40ns in this embodiment. The timing relationship of the waveform data signal, the data valid signal, and the data stretching signal is shown in fig. 2.
The clock domain crossing module stores the waveform data according to whether the value of the data valid signal is '1' (valid is enabled). The waveform data candidate storage module is composed of two registers, two waveform data points read out by the data clock domain crossing module are stored as alternatives, and one of the two waveform data points is selected to be sent to the microcontroller interface module under the control of the conflict detection module.
After receiving the read waveform data signal transmitted by the microcontroller interface module, the collision detection module sends two read request signals to the data clock domain crossing module, wherein the first read request signal is sent immediately. The time interval between the second read request signal and the first read request signal is longer than the effective length of the data stretching signal, in this embodiment, the effective length of the data stretching signal is 40ns, and here, the time interval is selected to be 60 ns. And determines whether the second read request signal is valid at the same time as the data stretching signal, in this embodiment determines whether the second read request signal is "1" at the same time as the data stretching signal, and if it is found that the second read request signal is not "1" at the same time as the data stretching signal (i.e., there is no collision), the waveform data candidate storage module selects the second read data "998" to be sent to the microcontroller interface module.
If the second read request signal and the data stretching signal are simultaneously '1' (i.e. there is a collision), and there is a possibility that the waveform data read for the second time has an error, the waveform data candidate memory module selects the '990' data read for the first time to be sent to the microcontroller interface module.
Because the data of the waveform data acquisition module is continuously refreshed in real time, the FPGA can reliably transmit the current latest data to the microcontroller within a short time when the microcontroller sends a read data request through the circuit.
Analysis and testing
1. Analysis of up-to-date waveform data
To achieve accurate control, it is necessary to ensure that the FPGA sends the waveform data acquired last time to the microcontroller (instead of being acquired in the previous time) after the microcontroller sends a read request. In the invention, the data cross-clock domain module only corresponds to a specific storage unit no matter writing or reading (in the embodiment, the address of the RAM is fixed, and only two different requests are adopted to respectively store), and the process of writing waveform data is to immediately store and refresh as long as new data is valid, so that the latest data sent to the microcontroller is ensured.
2. Waveform data transmission real-time test
The time of primary waveform data transmission is captured in the FPGA by using an online logic analyzer as shown in FIG. 4. As can be seen from the figure: the read enable (the dsp _ iord _ en signal) is asserted (representing the microcontroller issuing a read waveform data request) at 1578 th clock, and the read enable is de-asserted (representing the microcontroller reading waveform data) at 1591 th clock, (1591-. I.e. a real-time of 0.13 us.
3. Waveform data transmission reliability test
An analog-to-digital converter at the front end of the FPGA is connected with a standard sine signal, and a waveform data signal is read in a microcontroller and the read waveform data is plotted. Without the circuit of the invention, the waveform obtained by transmitting the latest acquired waveform data to the microcontroller is shown in FIG. 5; after the waveform data transmission circuit is used, the obtained waveform is read as shown in fig. 6.
The comparison shows that the waveform data transmission circuit between the FPGA and the microcontroller has no wrong data points, which shows that the reliability of waveform data transmission is strong.
According to the scheme, after the microcontroller sends a data reading request, the latest acquired data of the FPGA are transmitted to the microcontroller, on one hand, the real-time performance of data transmission (the real-time performance is actually measured to be 0.13us) can be solved, on the other hand, the condition that errors occur across clock domains of the data can be effectively avoided, and high-reliability data transmission is realized.
The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of the claims of the present invention, therefore, various changes, modifications and equivalents of the embodiments of the present invention may be made within the scope of the claims of the present invention.
Claims (7)
1. A real-time reliable waveform data transmission circuit between an FPGA and a microcontroller is characterized by comprising: the collision detection module, the candidate storage module of waveform data, the clock domain module is striden to the data, waveform data acquisition module and microcontroller interface module:
the waveform data acquisition module is used for sending a conversion starting signal to an analog-to-digital conversion module at the front end of the waveform data acquisition module, so that the analog-to-digital conversion module performs analog-to-digital conversion on a target signal based on the conversion starting signal, the waveform data acquisition module performs data reception based on the conversion starting signal and generates a data effective signal based on a data refreshing time, and generates a data broadening signal according to the data effective signal, the width of the data broadening signal is greater than that of the data effective signal, and the center of the data broadening signal is aligned with the edge of the data effective signal;
the data clock domain crossing module stores the acquired waveform data based on the data effective signal;
the collision detection module receives the data broadening signals of the waveform data acquisition module and read waveform data signals sent by the microcontroller interface module, and sends two read request signals to the data clock domain crossing module based on the read waveform data signals, wherein the first read request signal is synchronous with the read waveform data signals, and the interval time between the second read request signal and the first read request signal is longer than the effective length of the data broadening signals;
the data clock domain crossing module is used for reading data based on the two reading request signals respectively and sending the read data to the waveform data candidate storage module and storing the read data by adopting different registers;
the collision detection module detects and compares a second-time reading request signal and a data broadening signal, determines whether the second-time reading request signal and the data broadening signal are simultaneously effective, if the second-time reading request signal and the data broadening signal are simultaneously effective, the second-time reading request signal and the data broadening signal are regarded as collision, the collision detection module sends a collision signal to the waveform data candidate storage module, if no collision occurs, the waveform data candidate storage module outputs stored data read for the second time to the microcontroller interface module, and if collision occurs, the waveform data candidate storage module outputs stored data read for the first time to the microcontroller interface module;
the microcontroller interface module returns the data it receives to the microcontroller.
2. The real-time reliable waveform data transmission circuit between an FPGA and a microcontroller according to claim 1, comprising: the FPGA-based clock comprises a clock area 1 and a clock area 2, wherein clocks of the two clock areas have different frequencies or have the same frequency and the same phase, and the FPGA and the microcontroller are respectively positioned in the two clock areas.
3. The real-time reliable waveform data transmission circuit between an FPGA and a microcontroller according to claim 1, characterized in that the data stretching signal width satisfies the following requirements:
broadening signal effective time>N×T1And N/2 XT1>T2；
Wherein N is a positive integer, T1Is the period of 1 clock in the clock region, T2The period of the clock of clock zone 2.
4. The real-time reliable waveform data transmission circuit between FPGA and microcontroller according to claim 1, characterized in that the collision detection module, the waveform data candidate storage module, the data clock domain crossing module, the waveform data acquisition module and the microcontroller interface module are all hardware logic digital circuits that can be described by hardware description language verilog or VHDL in FPGA.
5. The real-time reliable waveform data transmission circuit between FPGA and microcontroller according to claim 1, characterized in that, the data cross clock domain module is a storage unit which has two clock interfaces and can store and read data.
6. The real-time reliable waveform data transmission circuit between the FPGA and the microcontroller as claimed in claim 1, wherein the microcontroller interface module is a hardware logic circuit capable of recognizing read and write requests of the microcontroller and receiving and transmitting data to the microcontroller.
7. The real-time reliable waveform data transmission circuit between an FPGA and a microcontroller as claimed in claims 1-6, wherein the FPGA is programmable hardware.
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