CN203673473U

CN203673473U - High-speed board card for eight channel transceiving serial ports on basis of FPGA

Info

Publication number: CN203673473U
Application number: CN201320809668.1U
Authority: CN
Inventors: 张鹏泉; 李羚梅; 曹晓冬; 马彪; 李柬; 范玉进; 褚孝鹏; 夏爽; 张波
Original assignee: Tianjin Optical Electrical Communication Technology Co Ltd
Current assignee: Tianjin Optical Electrical Communication Technology Co Ltd
Priority date: 2013-12-07
Filing date: 2013-12-07
Publication date: 2014-06-25
Anticipated expiration: 2023-12-07

Abstract

The utility model relates to a high-speed board card for eight channel transceiving serial ports on the basis of a FPGA. The high-speed board card comprises a PCIE connector and an FPGA chip. The FPGA chip comprises a PCIEIP core circuit, a CDMA unit, a transmission control unit and a peripheral interface unit control module. The PCIE connector is in both-way junction with the PCIEIP core circuit through eight pairs of difference serial ports used for receiving signals, eight pairs of difference serial ports used for sending the signals, a PCI-E interface used for reference of difference clock signals and a power supply, the PCIEIP core circuit is in both-way junction with the CDMA unit which is in both-way junction with the transmission control unit, and the transmission control unit is in both-way junction with a peripheral interface. An upper computer is connected through a PCI-EX8 high-speed board card on the basis of the FPGA, and signal instructions can be transmitted to peripheral equipment through the upper computer at a high speed and can also be fed back to the master control upper computer through the peripheral equipment quickly.

Description

A kind of high speed board of realizing 8 passage transmitting-receiving serial ports based on FPGA

Technical field

The utility model relates to communication, measuring and controlling equipment, particularly a kind of high speed board of realizing 8 passage transmitting-receiving serial ports based on FPGA.

Background technology

At present, along with the development of the communication technology, the communication between each circuit board of communication, measuring and controlling equipment circuit, between device is more and more, thereby requires also more and more higher to plate level communication speed.PCI express high-speed serial bus technology is to be applied to computing machine and the interconnected third generation technology of communications field peripherals.In computer realm, first generation bussing technique comprises ISA, EISA and VESA, and second generation bussing technique comprises PCI, AGP and PCI-X.The demand of the aspect such as security, restorability of the storage speed of the communication of current communication, measuring and controlling equipment circuit, memory capacity, information has had higher requirement to traditional digital data recording system.

Summary of the invention

In view of the demand that between each circuit board of communication, measuring and controlling equipment circuit, communication proposes high speed board, the utility model provides a kind of high speed board of realizing 8 passage transmitting-receiving serial ports based on FPGA.The design is directly connected the high speed board of 8 passage transmitting-receiving serial ports by FPGA, meet the requirement of PCI Express1.1 consensus standard, unidirectional maximum digit rate 2.5Gbps, and × 8 theories can be supported maximum transmission bandwidth 200MB/s × 8, i.e. 1.6GB/s.

What when PCI Express bus, adopt is low-voltage differential signal (LVDS) technology, and it is the differential signal technology of a kind of low-voltage, the little amplitude of oscillation, can realize connection point-to-point or a point-to-multipoint.Transmit data because it has adopted differential mode, so there be the common mode noise rejection ability stronger than single-ended transmission mode, also there is low-power consumption, low error rate, low crosstalking and the feature such as low radiation simultaneously.PCI-E high speed board based on FPGA, has good hardware platform adaptability; Fpga chip design should adopt the design of standard hardware descriptive language, and driver should adopt the portability of standard C language design, is suitable for the application such as networking, server and terminal high-speed transmission.

The utility model is to realize by such technical scheme: a kind of high speed board of realizing 8 passage transmitting-receiving serial ports based on FPGA, it is characterized in that: comprise PCIE connector and fpga chip, fpga chip comprises PCIE IP kernel circuit, CDMA unit, transmission control unit and peripheral interface units control module, wherein: PCIE connector is connected with host computer is two-way, PCIE connector is by 8 pairs of difference serial ports for receiving signal, for 8 pairs of difference serial ports of transmitted signal, for the PCI-E interface of reference difference clock signal and power supply respectively with two-way connection of PCIE IP kernel circuit of fpga chip inside, PCIE IP kernel circuit is connected with CDMA unit is two-way, CDMA unit is connected with transmission control unit is two-way, transmission control unit is connected with peripheral interface is two-way.

Advantage of the present utility model and beneficial effect are, all host computers such as networking, server and terminal in communication system are linked by the PCI-E X8 High-Speed-Board based on FPGA and connect, both can complete the signal instruction high-speed transfer of host computer to peripherals, also can feed back to rapidly master control host computer by peripherals.In the system with PCI Express1.1 bus communication, by adopt the utility model in main equipment, can greatly improve the communication speed of host computer and peripherals.

Accompanying drawing explanation

Fig. 1. be the overall catenation principle schematic diagram of the utility model;

Fig. 2 is PCI-E interface principle figure of the present utility model.

Embodiment

For clearer understanding invention, describe in detail in conjunction with the accompanying drawings and embodiments:

See figures.1.and.2, the high speed board of realizing 8 passage transmitting-receiving serial ports based on FPGA is for the communication between host computer and the board of communication system, host computer is connected to a FPGA by high-speed parallel port, through driving the PCI-E IP kernel circuit of FPGA inside, through CDMA unit, transmission control unit and peripheral interface units control module communicate by letter with peripheral bus realization by expansion mouthful, completes the communication function of PCI-E X8 high speed board.

Between host computer and FPGA, adopt PCI-E bus to communicate, there is the serial communication ability of 8 passages; According to the requirement of PCI Express1.1 consensus standard, the serial communication between the utility model host computer and FPGA adopts as gives a definition:

RX_P0-P7/N0-N7:8 receives signal to difference serial ports;

TX_P0-P7/N0-N7:8 is to difference serial ports transmitted signal;

REFCLK_P/N:PCI-E interface reference difference clock signal;

PERST#: power supply is ready to signal.

The PCI-E port of FPGA expansion need to be 1.2V PCML level mode by the lever selection of corresponding pin in the time of FPGA port arrangement.

Two large class registers are set in FPGA to be realized between host computer and FPGA mutual.

The major function of PCI-E connector is the physical connection realizing between high speed serialization differential interface and the general industry control platform/generic server of FPGA in PCI-E interface module, and connecting link need to meet the demand of related electric standard.

The major function of PCI-E IP kernel is to realize PCI-E protocol stack, safeguards the high speed data transfer on PCI-E link.FPGA in technical scheme adopts the EP2SGX30DF780I4N chip in the Stratix II GX of ALTERA company family chip, show with soft examining the PCI-E protocol stack that comprises Physical layer, data link layer and transport layer by the mode that consumes FPGA own resource, transmission bandwidth is PCI-E × 8, meet the regulation of " PCI Express Base Specification 1.0a or 1.1. ", its transport layer interface adopts Avalon-ST serial line interface.

CDMA is Chaining DMA(chain type DMA) abbreviation, the major function of this unit is to realize the random length exchanges data between board internal storage space and upper PC storage space by PCI-E link.The transmission direction of swap data, transport address and transmission length are formulated by upper PC or board, but the process of exchange is to be initiated by PC, is carried out by the CDMA unit in board.

The major function of transmission control unit has been the Data Transmission Controlling between PICE interface module internal memory and peripheral interface units.When data are during take peripheral interface units as target, read according to the content driven internal memory in data transmit control register, and composition sends datagram; In the time that data save as target in PCIE interface module, according to the content of resolution data message, fill in data receiver control register, and drive internal memory to write.

The major function of peripheral interface units control module, according to read write command, receives take data message as unit or sends datagram.Peripheral interface units control module is for realizing communicating by letter of FPGA and peripheral bus.

According to the above description, can realize scheme of the present utility model in conjunction with art technology.

Claims

1. realize the high speed board of 8 passage transmitting-receiving serial ports based on FPGA for one kind, it is characterized in that: comprise PCIE connector and fpga chip, fpga chip comprises PCIE IP kernel circuit, CDMA unit, transmission control unit and peripheral interface units control module, wherein: PCIE connector is connected with host computer is two-way, PCIE connector is by 8 pairs of difference serial ports for receiving signal, for 8 pairs of difference serial ports of transmitted signal, for the PCI-E interface of reference difference clock signal and power supply respectively with two-way connection of PCIE IP kernel circuit of fpga chip inside, PCIE IP kernel circuit is connected with CDMA unit is two-way, CDMA unit is connected with transmission control unit is two-way, transmission control unit is connected with peripheral interface is two-way.