CN203204997U - CAN bus interface high-resolution display screen controller based on FPGA - Google Patents

Abstract

The utility model discloses a CAN bus interface high-resolution display screen controller based on an FPGA. An external device is in signal connection with an external CAN transceiver. The external CAN transceiver is in signal connection with an external CAN controller. The external CAN controller is in signal connection with the FPGA via an SPI bus. A synchronous dynamic random access memory SDRAM is in signal connection with an SDRAM controller inside of a master core module FPGA. A serial FLASH configuration chip is in signal connection with a soft core processor inside of the master core module FPGA. A video signal output end of an LCD controller module inside of the master core module FPGA is connected with a low voltage differential signal input end of a low voltage differential signal transmission module. The low voltage differential signal transmission module sends an LVDS signal. The CAN bus interface high-resolution display screen controller is enabled to accurately control a high-resolution display screen, better resist interference in an industrial environment and conduct a data transmission in a greater distance with a lower cost.

Description

CAN bus interface sharpness screen controller based on FPGA

Technical field

The utility model belongs to a kind of displaying screen controller, particularly a kind of CAN bus interface sharpness screen controller based on FPGA.

Background technology

CAN is (the Controller Area Network of controller local area network, CAN) abbreviation, it is a kind of serial communication network that can effectively support distributed control and real-time control, belong to the fieldbus category, have that cost is low, reliability is high, antijamming capability and characteristics such as real-time, be one of most widely used fieldbus in the world.

Summary of the invention

The utility model provides a kind of CAN bus interface sharpness screen controller based on FPGA at the deficiencies in the prior art.

For realizing above purpose, the technical solution adopted in the utility model is:

A kind of CAN bus interface sharpness screen controller based on FPGA is made up of a master control nucleus module FPGA and a plurality of peripheral module.Described master control nucleus module FPGA adopts modular construction, comprises NiosII soft-core processor, on-chip memory, FIFO, sdram controller, lcd controller.Wherein, on-chip memory is connected with the NiosII soft-core processor, and the NiosII soft-core processor is connected with the sdram controller module by FIFO, and sdram controller is connected with another FIFO simultaneously, realizes the control to the lcd controller module;

Described a plurality of peripheral module comprises synchronous DRAM SDRAM, Low Voltage Differential Signal transmission LVDS module, the serial FLASH configuring chip, outside CAN transceiver, outside CAN controller, wherein, external unit is connected with outside CAN transceiver signal, outside CAN transceiver is connected with outside CAN controller signals, outside CAN controller is connected by the spi bus signal with FPGA, synchronous DRAM SDRAM is connected with sdram controller signal in the master control nucleus module FPGA, NiosII soft-core processor signal in serial FLASH configuring chip and the master control nucleus module FPGA is connected, and the VT of lcd controller module is connected with the Low Voltage Differential Signal input end that Low Voltage Differential Signal transmits the LVDS module in the master control nucleus module FPGA; Low Voltage Differential Signal transmission LVDS module sends the LVDS signal.

Beneficial effect: of the present utility modelly can in accurate control sharpness screen, with lower cost, resist the interference of industrial environment better, carry out the data transmission of farther distance.

Description of drawings

Fig. 1 is overall system block diagram of the present utility model.

Embodiment

Below in conjunction with drawings and Examples the utility model is further specified.

As shown in Figure 1, a kind of CAN bus interface sharpness screen controller based on FPGA is made up of a master control nucleus module FPGA4 and a plurality of peripheral module.Described master control nucleus module FPGA adopts modular construction, comprises NiosII soft-core processor, on-chip memory, FIFO(first in first out data buffer), the SDRAM(synchronous DRAM) controller, lcd controller.Wherein, on-chip memory is connected with the NiosII soft-core processor, and the NiosII soft-core processor is connected with the sdram controller module by FIFO, and sdram controller is connected with another FIFO simultaneously, realizes the control to the lcd controller module;

Described a plurality of peripheral module comprises synchronous DRAM SDRAM3, Low Voltage Differential Signal transmission LVDS module 6, serial FLASH configuring chip 5, outside CAN transceiver 1, outside CAN controller 2, wherein, external unit is connected with outside CAN transceiver 1 signal, outside CAN transceiver 1 is connected with outside CAN controller 2 signals, outside CAN controller 2 is connected by the spi bus signal with FPGA4, synchronous DRAM SDRAM3 is connected with sdram controller signal in the master control nucleus module FPGA4, NiosII soft-core processor signal in serial FLASH configuring chip 5 and the master control nucleus module FPGA4 is connected, and the VT of lcd controller module is connected with the Low Voltage Differential Signal input end that Low Voltage Differential Signal transmits LVDS module 6 in the master control nucleus module FPGA; Low Voltage Differential Signal transmission LVDS module sends the LVDS signal.

The utility model is that external unit sends to the CAN transceiver by the CAN bus with control command based on the groundwork flow process of the sharpness screen controller of the CAN bus interface of FPGA, then by the CAN controller, realization is connected with FPGA's, wherein the CAN controller carries out the parsing of order for the NiosII soft-core processor of FPGA inside command transfer by Serial Peripheral Interface (SPI) (spi bus), then order is converted into the data that will send, under the control of sdram controller, data cushion by FIFO, temporarily be stored among the video memory SDRAM, under the enough situation of data quantity stored (can the whole screen of complete filling), by the FIFO buffering, under the control of lcd controller, be transferred to LCD through Low Voltage Differential Signal transport module LVDS.

It is Cyclone II EP2C5 chip that fpga chip is selected the model of altera corp for use, wherein the inner NiosII soft-core processor that embeds adopts F type (type fast), under the highest system performance, medium FPGA use amount, be used for realizing operational management and the control of whole industrial displaying screen controller; It is the TJA1050 chip that the CAN transceiver is selected the model of Philips company for use; It is SJA1000 that the CAN controller is selected the model of Philips company for use; It is the EPCS4 chip that configuring chip is selected model for use, as the specialized configuration chip of FPGA, be used for to preserve the configuration information of FPGA, the trouble of avoiding FPGA to power on reconfiguring; It is the HY57V641620HG chip that SDRAM selects the model of Hynix company for use; The LVDS transmitter is used for connecting FPGA and liquid crystal display, and the advantage of low-power consumption is provided when providing High Data Rate, strong noise to suppress ability.

Claims (1)

1. based on the CAN bus interface sharpness screen controller of FPGA, comprise a master control nucleus module FPGA and a plurality of peripheral module composition;

It is characterized in that: described master control nucleus module FPGA adopts modular construction, comprises NiosII soft-core processor, on-chip memory, FIFO, sdram controller, lcd controller; Wherein, on-chip memory is connected with the NiosII soft-core processor, and the NiosII soft-core processor is connected with the sdram controller module by FIFO, and sdram controller is connected with another FIFO simultaneously, realizes the control to the lcd controller module;

Described a plurality of peripheral module comprises synchronous DRAM SDRAM, Low Voltage Differential Signal transmission LVDS module, the serial FLASH configuring chip, outside CAN transceiver, outside CAN controller, wherein, external unit is connected with outside CAN transceiver signal, outside CAN transceiver is connected with outside CAN controller signals, outside CAN controller is connected by the spi bus signal with FPGA, synchronous DRAM SDRAM is connected with sdram controller signal in the master control nucleus module FPGA, NiosII soft-core processor signal in serial FLASH configuring chip and the master control nucleus module FPGA is connected, and the VT of lcd controller module is connected with the Low Voltage Differential Signal input end that Low Voltage Differential Signal transmits the LVDS module in the master control nucleus module FPGA; Low Voltage Differential Signal transmission LVDS module sends the LVDS signal.

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