CN104380274B

CN104380274B - Apparatus and method for the link training and management of optimization

Info

Publication number: CN104380274B
Application number: CN201380021347.8A
Authority: CN
Inventors: M·瓦格; D·J·哈里曼
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2012-05-22
Filing date: 2013-05-16
Publication date: 2017-10-24
Anticipated expiration: 2033-05-16
Also published as: CN107092335A; CN104380274A; CN107092335B

Abstract

In one embodiment, aggregation protocol stack can be used in unification from the first communication protocol to the communication of the second communication protocol, to provide the data transmission across physical interconnections.This stack can be merged into following device, the device includes the protocol stack for including affairs and the first communication protocol of link layer and is couple to the protocol stack with physics (PHY) unit for the communication that equipment room of the device with being couple to the device is provided via physical link.This PHY unit can include the physical location circuit according to the second communication protocol.It is described and claimed other embodiments.

Description

Apparatus and method for the link training and management of optimization

Technical field

Embodiment is related to interconnection technique.

Background

In order to provide the communication in system between distinct device, certain type of interconnection mechanism is used.It is real depending on system Mode is applied, wide variety of such interconnection is possible.Often in order that two equipment can be communicated, they share altogether Same communication protocol

A kind of typical communication protocol for communication between devices in computer system is according to based on PCI Express rule Model basic norm version 3 .0（On November 18th, 2010 publishes）（Hereinafter referred to as PCIe^TMSpecification）Link peripheral assembly it is quick Interconnection（PCI Express^TM（PCIe^TM））Communication protocol.This communication protocol is loading/storage input/output（IO）Mutually link One example of system.The communication of the equipment room is performed with very high speed serial generally according to this agreement.When desk-top PCIe is developed under the background of computer^TMDuring communication protocol, in order to realize maximum performance in the case where not considering power efficiency Purpose, develops the various parameters on this agreement.As a result, its many features, which can not be reduced to, can be integrated into mobile system Lower-wattage solution in system.

In addition to these power problems on conventional loading/storage communication protocol, existing link management scheme is usual It is extremely complex and be related to a large amount of states, cause the lengthy process changed between execution state.It is partly due to existing link Administrative mechanism, it is developed to understand many different forms factors dictates such as connector, different system merging.One this The example of sample is according to PCIe^TMThe link management of communication protocol.

Brief description

Fig. 1 is the high-level block diagram of the protocol stack for communication protocol according to the embodiment of the present invention.

Fig. 2 is the on-chip system according to the embodiment of the present invention（SoC）Block diagram.

Fig. 3 is the block diagram of the physical location according to another embodiment of the present invention.

Fig. 4 is the block diagram for the further detail below for showing protocol stack according to embodiments of the present invention.

Fig. 5 is the state diagram for Link Training State Machine, and it can be link manager according to embodiments of the present invention Part.

Fig. 6 is the flow chart of each state for sideband mechanism according to the embodiment of the present invention.

Fig. 7 is the flow chart of the method according to the embodiment of the present invention.

Fig. 8 is the block diagram of the component according to present in the computer system of the embodiment of the present invention.

Fig. 9 is the block diagram for the instance system that embodiment can be used therewith.

Embodiment

Embodiment can provide input/output（IO）Interconnection technique, it has low-power, loading/storage architecture, and especially Suitable for the mobile device in the cell phone including smart phone, tablet PC, electronic reader, ultrabook etc. In use.

In embodiments, for give communication protocol protocol stack can from the physical location of different communication protocol or At least one physics different from the physical location for giving communication protocol（PHY）Unit is used together.Physical location includes Logical layer and physically or electrically both gas-bearing formations, physically or electrically gas-bearing formation is in interconnection（Such as link the link of two separate semiconductor tube cores） The upper reality for providing information signal, the communication of physics, two separate semiconductor tube cores can be in single integrated circuit（IC）Envelope Dress or two semiconductor elements such as being route via circuit board, trace in the separation encapsulation of coupling.In addition, the physics list Member is able to carry out the framing of packet（framing）/ solution frame（deframing）, link training and initialization are performed, and handle use In the packet for receiving or being delivered in physical interconnections from physical interconnections.

Although may have different embodiments, in one embodiment, the protocol stack may have conventional base In personal computer（PC）Communication protocol（Such as according to PCI Express normative foundations specification version 3.0（2010 11 The moon 18 was published）（Hereinafter referred to as PCIe^TMSpecification）Peripheral assembly quickly interconnect（PCI）Express^TM（PCIe^TM））Communication protocols View）, application protocol extension further version, or another such agreement, while the physical location is not based on the PCIe^TMIt is logical Believe agreement.For the purpose for realizing low-power operation, it is substantially immovable that this physical location can be specifically designed permission PCIe^TMUpper protocol stack merges with this low-power physical circuit.So, for ease of be merged into low-power operation it is portable simultaneously And it is other be not based in PC desktop, laptop, PCIe can be utilized^TMThe extensive traditional infrastructure of communication protocol.But the present invention Scope not limited to this, in one embodiment, this physical location can be by mobile platform（Such as handled according to mobile industrial Device interface（MIPI）Alliance（It is the group for mobile computing device established standardses）M-PHY specification versions 1.00.00 --- on 2 8th, 2011（The MIPI Board of approval on April 28th, 2011）（Hereinafter MIPI specifications）It is so-called M-PHY）The physical location of adaptation.However, other low-power physical locations can be used（Such as according to such as multicore Other low-power specifications that individual dice in piece encapsulation is coupled together）, or the low-power solution customized.Such as this paper institutes , term " low-power " mean be in less than conventional PC system power consumption levels, and its can apply to it is wide variety of Mobile and portable equipment.As example, " low-power " can be that the power of consumption is less than routine PCIe^TMThe physics list of physical location Member.

So, by by traditional PCIe^TMProtocol stack polymerize with different types of physical location, and what is largely reused is directed to PCIe^TMThe traditional components of exploitation can be used to be merged into mobile or other portable or low-power platform.

Embodiment can also utilize following understanding：I.e. existing loading/storage I/O technology, especially PCIe^TMWith following purpose It is designed：Maximum performance is realized in the case where power efficiency is not subject matter, and therefore will not be reduced to low-power and is answered With.By the way that conventional loading/part of storage protocol stack is combined with the physical location of low-power design, embodiment can retain PCIe^TMPerformance advantage, while being reached in equipment and platform rank in terms of power most preferably.

As such, embodiment can be the PCIe with the generally existing with big traditional infrastructure^TMThe compatible software of framework.This Outside, embodiment can also realize that direct PHY reuses mobile design PHY, such as M-PHY.In such manner, it is possible to utilize the height of transmission Imitate power/bit and turn into electromagnetic interface/radio frequency interface with open arms（EMI/RFI）Method realize low active and idle work( Rate, because PHY can be not disturb associated radio（Because the harmonic wave for PHY clock rate does not interfere typical nothing The conventional RF that line electricity solution is operated with it（For example, 1.8,1.9,2.4 gigahertzs（GHz））Or other such radio frequencies） Clock rate operation.

Embodiment can further provide for realizing the link training and administrative mechanism of optimization（LTSSM）Framework improve；It is excellent The flow control of change and retry buffering and administrative mechanism；Framework agreement for changing link operation pattern；Fast hardware is supported to set Standby state is preserved and recovered；And for the unified sideband mechanism with the optional link management with interior support.

In embodiments, PCIe^TMAffairs and data link layer can be implemented with the protocol stack of limited modification Part is in terms of and different link-speeds and asymmetric link.It is furthermore possible to also provide amendment link training and management, with including To multichannel communication, asymmetric link configuration, sideband unification and the support of dynamic bandwidth scalability.Embodiment can be carried further For being based on PCIe to existing^TMAnd based on non-PCIe^TMThe logical sum such as circuit of M-PHY logical sums circuit etc between bridge The support connect.

This layered approach causes existing software stack（For example, operating system（OS）, virtual machine manager and driver） Can in different physical layers seamless operation.Influence to the data link and transaction layer is minimized and can included Related timer is updated to update answer frequency, reset timer etc..

Therefore, each embodiment can limit PCIe^TMSome flexibilities provided in system, because some feelings of this flexibility In PCIe under condition^TMSome complexity can be created in both system and other systems.Really in this way, because both agreements are all carried Supply to realize the great flexibility inserted and broadcast ability.On the contrary, each embodiment can customize the amount of minimum design flexibility Solution, given system is integrated into because working as（For example with another integrated circuit（IC）The on-chip system of interconnection（SoC））In When, there is known and fixed configuration.Because being known in terms of the accurate configuration existed is realized, when setting for SoC and connection When standby both of which is affixed in platform, for example, the circuit board of the system is welded to, these equipment need not insert and broadcast ability, and Therefore it may not be needed PCIe^TMOr other communication protocols based on PC it is intrinsic, distinct device is seamlessly merged into It is to broadcast the larger flexibility in the system of ability with inserting.

As an example, the SoC potentially acts as the root complex implemented in the first IC（root complex）, and coupling Be connected to can be radio solution the 2nd IC, it can include one or more of multiple Wireless Telecom Equipments and set It is standby.The scope of such equipment can be from such as according to bluetooth^TMThe low power, short range communication system of specification, such as basis give Electric and EEA Eelectronic Eengineering Association（IEEE）802.11 the so-called WiFi of standard^TMThe local wireless communication of system, to such as give Cellular communication protocol（Such as 3G or 4G communication protocols）High power wireless system.

Referring now to Figure 1, showing the high-level block diagram of the protocol stack for communication protocol according to embodiments of the present invention. As shown in fig. 1, stack 100 can be semiconductor subassembly（Such as IC）The combination of interior software, firmware and hardware, for providing to institute State semiconductor equipment and the processing for another equipment room data communication being coupled with it.In the embodiment in figure 1, show and start from The high level view of high-level software 110, high-level software 110 can be performed on to fixed platform various types of soft Part.This high-level software can include operating system（OS）Software, firmware, application software etc..Will be via the transmission of interconnection 140 Data can be transmitted by each layer of protocol stack, generally be shown in Fig. 1, interconnection 140 can be by the semiconductor equipment with The given physical interconnections of another component coupling.As can be seen, this protocol stack each several part can be conventional PCIe^TMThe portion of stack 120 Point, it is possible to including transaction layer 125 and data link layer 128.Generally, transaction layer 125 be used for generation can be request or by when Between the transaction layer packet of the packet based on response that separates（TLP）, so as to allow the link to carry other business, while mesh Marking device collects the data for the response.The transaction layer further handles fiduciary flow control.Therefore, transaction layer 125 provide the interface between the process circuit and interconnection architecture of equipment, such as data link layer and physical layer.In this respect, it is described The major responsibility of transaction layer is packet（That is, transaction layer packet（TLP））Assembling and decomposition and handle it is fiduciary Flow control.

Then, data link layer 128 can sort the TLP of transaction layer generation, and ensure that the reliable of TLP is passed between two end points Send（Including processing error checking）And reply process.Therefore, link layer 128 serves as the scala media between transaction layer and physical layer Section, and provide a mean for the reliable mechanism that link exchanges TLP in two inter-modules.The side of the link layer is received by described The TLP of transaction layer assembling, application identifier is calculated and application error detection code（For example circulation recovers code（CRC））, and will repair The TLP changed submits to physical layer to transmit to external equipment across physical link.

After being handled in data link layer 128, PHY unit 130 can be transferred a packet to.Generally, PHY unit 130 Low-power PHY134 can be included, it can include logical layer and physics（Including electric）Both sublayers.In one embodiment, Packet is transferred to external equipment by the physical layer represented by PHY unit 130 for physically.The physical layer is included for transmission Prepare the transmission zone of going-out information and identified before by the information transmission of reception to link layer and prepare its receiver area Section.The symbol for being serialized and be transferred to external equipment is supplied to the transmitter.By the serialization symbol from external equipment Number the receiver is supplied to, and received signal is transformed to bit stream by receiver.The bit stream solution is serial simultaneously It is supplied to logical sub-blocks.

In one embodiment, low-power PHY134（It can be particularly developed or by the another of such as M-PHY etc The given low-power PHY of PHY adaptations）The processing to packing data can be provided to transmit along interconnection 140.As entered in Fig. 1 Seen by one step, link training and management level 132（Also referred to herein as link manager）PHY unit 130 can also be present in It is interior.In embodiments, link manager 132 can include can be according to such as PCIe^TMAnother communication protocol of agreement is implemented Certain logic and handle for example above-mentioned PCIe^TMThe routine of protocol stack and physics PHY134 interfaces with different agreement it is special There is logic.

In the embodiment in figure 1, interconnection 140 can be embodied as differential lines pair, and differential lines are to that can be two pairs of unidirectional lines. In some embodiments, multigroup differential pair can be for increase bandwidth.It should be noted that according to PCIe^TMCommunication protocol, it is desirable to Mei Gefang The number of upward differential pair is identical.However, according to each embodiment, it is different number of right to provide in each direction, this permits Perhaps operate more efficient, power lower.The stack entirely polymerizeing and link 140 can be referred to as mobile quick PCIe^TMInterconnection or link. Although in the embodiment in figure 1 with this it is high-level show, it will be appreciated that the scope of the present invention not limited to this.That is, will Understand, the view shown in Fig. 1 is only about the protocol stack and high-level software from transaction layer by physical layer, and Not shown SoC various other circuits or other semiconductor equipments including this stack.

Referring now to Figure 2, showing SoC according to embodiments of the present invention block diagram.As shown in Fig. 2 SoC200 can be used In implementing any kind of platform in various types of SoC, scope is from such as smart phone, personal digital assistant（PDA）、 Tablet PC, notebook, ultrabook^TMOr the like relatively small low-power portable equipment to can be in high-level system The SoC of the higher level of implementation.

As seen in Figure 2, SoC200 can include one or more kernels 210₀-210_n.Therefore in embodiments, There may be multinuclear SoC, the kernel can be all the homogeneity kernel with given framework, such as orderly or out-of-order processors. Or can have heterogeneous kernel, such as some relatively small low-power kernels, such as kernel with orderly framework；Have The additional kernel of presence, the additional kernel can have bigger and more complicated framework, such as unordered framework.Protocol stack realizes this The data communication between other components of system of one or more of a little kernels.As seen, this stack can include software 215, it can be higher level software（Such as OS, firmware）With the application layer software performed on one or more kernels.Separately Outside, the protocol stack includes transaction layer 220 and data link layer 230.In embodiments, these affairs and data link layer can With with such as PCIe^TMThe given communication protocol of agreement.Certainly, there may be in other embodiments such as total according to general serial Line（USB）The layer of the different agreement stack of protocol stack.Moreover, in some embodiments, can be many with existing replacement protocol stack Road is multiplexed low-power PHY circuit as described herein.

Referring still to Fig. 2, then this protocol stack can be couple to physical location 240, and physical location 240 can include energy Enough multiple physical locations that communication is provided via a plurality of interconnection.In one embodiment, the first physical location 250 can be low work( Rate PHY unit, it can correspond to the M-PHY according to MIPI specifications in one embodiment, for being provided via main interconnection 280 Communication.Furthermore it is possible to there is sideband（SB）PHY unit 244.In an illustrated embodiment, this sideband PHY unit can be via Sideband interconnection 270 provides communications, and sideband interconnection 270 can be slower than be couple to the first PHY250 main interconnection for for example 280 data rate provides the unified sideband of some side informations.In certain embodiments, each layer of the protocol stack can have Have and be couple to this SB PHY244 to realize the separation sideband of the communication interconnected along this sideband.

In addition, PHY unit 240 may further include the SB link managers 242 that can be used in controlling SB PHY244. Furthermore it is possible to there is link training and state supervisor 245, and it can be used in the protocol stack with the first communication protocol The first PHY250 with the second communication protocol is fitted to, and offer is controlled for the first PHY250 and the overall of interconnection 280.

As further seen, there may be various assemblies in the first PHY250.More specifically, there may be transmitter and Acceptor circuit（That is TX253 and RX254）.Generally, this circuit can for perform serialization operation, solution serial operation and Via the main transmission of interconnection 280 and reception data.There may be preservation state supervisor 251, and when it is in low power state When can be used for preserving configuration on the first PHY250 and other status informations.Moreover, there can be encoder 252, it is used for Line coding is for example performed according to 8b/10b agreements.

As Fig. 2 further seen by, there may be mechanical interface 258.This mechanical interface 258 can be given interconnection, For providing the communication from root complex 200, and more specifically reach via main interconnection 280/from the first PHY250's Communication.In embodiments, this mechanical connection can utilize such as ball grid array（BGA）Or the half of other surface mounts etc The pin of conductor device, or plating is connected by hole.

In addition to these Primary communication mechanism, additional communication interface can be serial using low-power（LPS）PHY unit 255, low-power is serial（LPS）PHY unit 255 is via including the separation of software layer 216, transaction layer 221 and link layer 231 Stack is coupled between kernel 210 and one or more external equipment 260a-c, and described external equipment can be such as sensor, acceleration Meter, temperature sensor, global positioning system（GPS）Circuit, compassing circuit, touch screen circuitry, keyboard circuit, mouse circuit etc. it The various low data rate ancillary equipment of class.

It should be noted that in embodiments, the interconnection 280 of sideband interconnection 270 or main both can be in SoC200 and second half Conductor assembly（Such as such as many another IC with radio solution etc）Between couple.

Again, although Fig. 2 diagram is of a relatively high rank, but can be changed.For example, multiple low-power can be provided PHY via a plurality of channel for example to realize the data communication of higher rate, wherein each channel is associated with independent PHY.Now With reference to Fig. 3, the block diagram of physical location according to another embodiment of the present invention is shown.As shown in Figure 3, physical location 300 includes Link training and state supervisor 310.This state supervisor can be with as described above, can be simultaneously logical collection, for making tool Have the first communication protocol protocol stack can with second（For example it is different）The physical location interface of communication protocol.

As seen by Fig. 3 further, link training and state supervisor 310 can be with multiple M-PHY320₀-320_nIt is logical Letter.The such PHY more than one by providing, can carry out the data communication of higher rate.Although it should be noted that shown in Fig. 3 Each M-PHY can include the logic of some numbers for enabling its individual independent communication to occur, but to these different M- The overall control of PHY communication can be via link training and state supervisor 310.Although moreover, it will be appreciated that being shown in Fig. 3 Multiple M-PHY, but in other embodiments, can have another type of multiple PHY units, and can provide other multiple Heterogeneous PHY unit.It should be noted that each M-PHY units can be used as the part of unique logic link, or in group, wherein Group is associated with single logical link.Each equipment can generally consume single logical link, but single in certain embodiments Individual physical equipment can consume multiple logical links, for example, provide proprietary link money for the difference in functionality for multifunctional module Source.

Referring now to Figure 4, being illustrated that the block diagram for the further detail below for showing protocol stack according to embodiments of the present invention.Such as Shown in Fig. 4, stack 400 includes various layers, including：Transaction layer 410, data link layer 420 and physical layer 430.As described above, energy Enough use PCIe^TMThe regular transaction of protocol stack and the revision of data link part or such stack configure these different layers, To accommodate interacting between these layers with first communication protocol and the physical layer with another communication protocol, physical layer exists Can be the M-PHY according to MIPI specifications in Fig. 4 embodiment.

As seen in Figure 4, on the transmission direction from the transmission information of protocol stack 400, in the usual combination control of transaction layer System and data path receive other circuits for example from SoC in the transmission packet assembler 412 to form TLP（Such as kernel Or other processing logics）To the arrival information of protocol stack.After transmission packet is assembled into（Transmission packet is implemented each Can be that there is such as 1 to 4096 byte in example（Or with less maximum allowable size, for example, 128 or 256）Data Bag）, the packet of assembling is supplied to stream controller 414, stream controller 414 is based on the ensuing of enqueuing transport（One or It is multiple）Number required by TLP determines whether that enough flow control credits can use, and controls packet being injected into data In link layer 420.It is more specific seen, the packet of these injections is provided to error detector and serial device 422, in a reality TLP sequence numbers and LCRC can be generated by applying error detector and serial device 422 in example.It is further seen, data link layer 420 Further comprise transmission message mechanism 426, transmission message mechanism 426 then generates the DLLP for link management function, and coupling Data link transmission controller 425 is connected to, it is to be used for flow control and data link integrality（ACK/NAK）The controller of mechanism Function；It should be noted that this can be subdivided, to implement these functions using different logical blocks.

As further seen, treated packet is supplied to and retries buffering 424, retried buffering 424 and preserve every Individual TLP copy is until by components respond on the link opposite side, it is noted that this in practice can utilize and be buffered in stack more Top（In the assembler 412 or top）To implement, and they can be stored in corresponding entry, until being chosen use In being transferred to physical layer 430 via data/message selector 428.Generally, above-mentioned affairs and data link layer can be according to routines PCIe^TMProtocol stack circuit operation, some of which modification will be further described below.

Conversely on physical layer 430, much more modification to some logic modules of this layer（For example according to PCIe^TMAssociation As view stack modification）Can occur and for providing the actual physics part to the physical location with another communication protocol Interface.As can be seen, the packet of arrival can be applied to frame generator 432, it increases physical layer frame symbol and is institute Packet delta frame is stated, and the byte being supplied in bandwidth/location mapper 434, its shifted data path is with life Calibration into the requirement for outside transmission can be used for holding so as to adjust wide data path if necessary, and then be couple to Line link is trained and jump is sorted training aids and jump sequence device 436.As can be seen, frame generator 432, training aids/sequence Device 436 and data/sequence selector 438 can all be couple to physical layer transmission controller 435, physical layer transmission controller 435 be the Transceiver section of LTSSM and interrelated logic.Frame 436 is to be used to generate physical layer transmission（Such as training set（TS）And jump Jump sequence collection）Logic.So, the packet of framing can be chosen and be supplied to physical circuit, to perform coding, serialization Driven with the serialization signal of the packet corresponding to processing to physical interconnections.In one embodiment, it can be sent out in frame Give birth to the mapping of signature between execution different communication protocol in device 432.

As can be seen, a plurality of individual channels or passage can be provided to this physical interconnections.In an illustrated embodiment, often Individual physical channel or passage can include the independent PHY unit transmission circuit 445 of its own₀-445_j, in one embodiment its Each can be the part of the M-PHY units according to MIPI specifications.It is as described herein, different from transmitter and the number of receiver The PCIe of mesh matching^TM, there may be different number of transmitter and receiver.Therefore as can be seen, each energy of transmission circuit 445 It is enough include being used for being encoded according to 8b/10b the encoder encoded to symbol, the serializer encoded symbol serialization and The driver driven signals into physical interconnections.As further seen, each passage or channel can be with logic units 440₀-440_jAssociated, it can be the logic circuit according to the MIPI specifications for being used for M-PHY, for therefore via corresponding logical Road manages physical communication.

It should be noted that these multiple passages can be configured as with different speed operations, and embodiment can include difference Such passage of number.Furthermore it is possible to which there is different number of passage and channel speed upwards in transmission and recipient.Therefore, Although the operation of the given control of logic unit 440 PHY445 respective channel, it is to be understood that physical layer transmission controller 435 It can be used for control to transmit via the Global Information of physical interconnections.It should be noted that in some cases, some unusual basic functions Performed by the Different Logic associated with each passage；, can be with for channel allocation can be given to the situation more than single link Multiple LTSSM examples are provided；For the link of training, exist in each component of control both transceiver and receiver-side single Individual LTSSM.This overall control can include Power Control, link-speeds control, link width control, initialization etc..

Referring still to Fig. 4, the arrival information received via physical interconnections can be similarly by physical layer 430, Data-Link Road floor 420 and transaction layer 410 are transmitted via the reception mechanism of these floor.In the embodiment illustrated in figure 4, each PHY unit It may further include receiving circuit, i.e. receiving circuit 455₀-455_k, its receiving circuit 455 in an illustrated embodiment₀-455_k Can exist for each passage of physical link.It should be noted that in this embodiment, acceptor circuit 455 and transmitter electricity The number on road 445 is different.As can be seen, this physical circuit can be including carrying out the input buffering of information for receiving, to this Information carries out solving serial deserializer and can be used for the decoder that decoding encodes the symbol of transmission with 8b/10b.Such as enter one Step is seen, and each passage or channel can be with logic units 450₀-450_kIt is associated, logic unit 450₀-450_kIt can be root According to given specification（MIPI specifications for example for M-PHY）Logic circuit, for therefore manage via respective channel physics Communication.

The symbol decoded can be then supplied to the logical gate of physical layer 430, it can include elasticity as can be seen Buffering 460, wherein the elastic buffer accommodates the clock difference between this component and another component on the link；It should be noted that Its position can be shifted into for example under 8b/10b decoders in each embodiment, or with passage deskew buffering group Close, and store the solution code sign of arrival.Then, the information can be provided to width/location mapper 462, be carried by there The passage deskew buffering 464 of across the plurality of passages execution deskew of supply, and for multichannel situation, buffering 464 can be located The difference of interchannel signal skew is managed to realign byte.Then, frame processing can be provided to via the information of deskew Device 466, it can eliminate frame present in arrival information.As can be seen, physical layer receives controller 465 and can be couple to and control Elastic buffer 460 processed, mapper 462, deskew buffering 464 and Frame Handler 466.

Referring still to Fig. 4, the packet of recovery can be supplied to reception message mechanism 478 and error detector, sequence Detector and link level are retried（LLR）Requester 475.This circuit can perform error correction inspection to the packet of arrival, For example by performing CRC check and operating, perform sequence inspection and ask to retry the packet progress link level of garbled-reception. Receive both message mechanism 478 and error detector/requester 475 and may be in the control that data link receives controller 480 Under system.

Referring still to Fig. 4, therefore the packet handled in unit 475 can be supplied to transaction layer 410, and more specifically Ground is supplied to stream controller 485, and it performs flow control to be supplied to packet interpreter 495 to these packets.Number The explanation to the packet is performed according to bag interpreter 495, and forwards them to selected destination, such as given kernel Or other logic circuits of the receiver.Although in Fig. 4 embodiment with this it is high-level show, it is to be understood that the present invention Scope not limited to this.

It should be noted that PHY440 can be used and by the PCIe for transmission^TMThe identical 8b/10b codings supported.It is described 8b/10b encoding schemes provide the additional character for being different from being used for representing the data symbol of character.These additional characters can be used for PCIe^TMVarious link management mechanism described in the physical layer chapters and sections of specification.M-PHY is described in MIPI M-PHY specifications Use to additional additional character.Embodiment can provide PCIe^TMWith the mapping between MIPI M-PHY symbols.

With reference now to table 1, PCIe according to an embodiment of the invention is shown^TMSymbol to M-PHY symbols exemplary Mapping.Therefore, the mapping of this additional character for representing the protocol stack according to an embodiment of the invention for being used to polymerize.

Table 1

The 8b/10b decodings rule is with being directed to PCIe^TMIt is identical that specification is defined.The sole exception of 8b/10b rules is to work as When detecting TAIL OF BURST, this is the particular sequence for violating 8b/10b rules.According to each embodiment, physical layer 430 can Any wrong notice met with during TAIL OF BURST is provided to data link layer 420.

In one embodiment, the framing of symbol and can be such as PCIe applied to passage^TMDefined in specification, count simultaneously Can be with PCIe according to scrambling^TMIt is identical defined in specification.It is however to be noted that not upsetting according to the communication of MIPI specifications The data symbol transmitted in the PREPARE stages.

On link initialization and training, link manager can be provided can lead to including one or more as discussed above The configuration and initialization of the link of the channel in road, to normal data transmit support, to recovering from link error when State Transferring Support and restarted by the port of low power state.

In order to realize this generic operation, following physical and the related feature of link can be known in advance（For example initialize Before）：PHY parameters（E.g., including initial link circuit speed and support speed；And initial link circuit width and the link of support Width）.

In one embodiment, training can include various operations.This generic operation can include：With the link-speeds of configuration Lock, locked per channel symbol with the width initialization link, per channel bit, passage polarity and the passage for multichannel link To passage deskew.So, training is it can be found that passage polarity, and performs adjustment accordingly.It is however to be noted that according to the present invention The link training of embodiment can not include link data rates and width negotiation, link-speeds and width are degenerated.Conversely as above It is described, once initialization link, two entities all know initial link circuit width and speed in advance, and therefore, it is possible to avoid and consult Associated time and calculation cost.

PCIe^TMOrdered set can be used in following modification：TS1 and TS2 ordered sets are used to facilitate IP to reuse, but ignore described Train many fields of ordered set.Moreover, without using Fast Training sequence.Electrical idle ordered set can be retained（EIOS）With side Just IP is reused, as jump OS like that, but jump OS frequency can for according to PCIe^TMThe friction speed of specification.Also Note, data flow ordered set and symbol can with according to PCIe^TMSpecification it is identical.

Following event is transmitted to facilitate link training and management：（1）In the presence of it can be used to refer to the remote port in link On there is active PHY；And（2）Configuration prepares, its be triggered with indicate to complete PHY parameter configurations and the PHY with The configuration file put prepares operation.In one embodiment, it is that category information can be according to embodiments of the present invention via unified side Band signal is transmitted.

For the purpose of control electrical idle situation, PHY, which has, to be used to indicate that transmitter just enters electrical idle state In TAIL OF BURST sequences.In one embodiment, the sideband channel can be used for signal transmission quitting electric sky It is not busy.It should be noted that this instruction can suppress to break mechanism plus PHY.Can using the OPENS sequences of symbol as EIOS transmit with Instruction enters electrical idle state.

In certain embodiments, undefined Fast Training sequence（FTS）.On the contrary, PHY can use specific physics sequence Row for being exited from shutdown/sleep state to that can be used for, lock, symbol is locked and passage dashing forward to passage deskew by addressing bits Hair-like state.A small amount of FTS can be defined as to the symbol sebolic addressing for robustness.The beginning of data flow ordered set can basis PCIe^TMSpecification, as recovering link error.

On link data rates, in embodiments, the original data rate of the link initialization can be predetermined Data rate.Can occur to change from the data rate of this initial link circuit speed by undergoing recovery state.Embodiment can To support asymmetric link data rate, wherein allowing data rate in opposite direction different.

In one embodiment, the link width supported can be according to PCIe^TMThose in specification.In addition, as above institute State, because the link width is predetermined, embodiment can not be supported for consulting the agreement of link width, and therefore may be used To simplify link training.Certainly, embodiment can provide support for the asymmetric link width in opposite direction.Meanwhile, for It is known that the initial link circuit width and original data rate of each direction configuration of link, which can shift to an earlier date before training starts,.

On the physical port of the PHY unit, do not require that xN ports form xN（Wherein N can be 32,16,12,8,4, 2 and 1）The ability of any link width is optional between the ability of link and x1 links, and xN ports formation N and 1.This The example of behavior includes x16 ports, and it can be only configured to unique link, but the link width can be configured as x12, X8, x4, x2 and x16 and x1 requirement width.So, seek using protocol stack facilities and equipments according to embodiments of the present invention Designer can connect the port of these inter-modules in the way of allowing two different components to meet above-mentioned requirements.If inter-module Port connected in the way of not meeting the desired use as defined in the port of component description/tables of data, then behavior is undefined.

In addition, not disabling the ability that a port is divided into two or more links.If such support to be suitable to give Design, then the port can be configured as supporting specific width during the training period.The example of this behavior will be can Configure the x16 ports of two x8 links, 4 x4 links or 16 x1 links.

When using 8b/10b codings, such as PCIe^TMUnambiguously passage to passage deskew mechanism in specification is in training The COM symbol of the ordered set received during sequence or SKP ordered sets, because the simultaneous transmission on all passages of the link of configuration Ordered set.The MK0 symbols transmitted during HS-BURST synchronizing sequence can be used for passage-passage deskew.

Sketched, link training and state supervisor can be configured as performing various operations, wrapped above with reference to Fig. 4 Include PCIe^TMThe upper strata of protocol stack is adapted to lower floor's PHY unit of different agreement.In addition, this link manager can be configured And manage single or multiple passages, it is possible to including to following every support：Symmetric links bandwidth, with PCIe^TMAffairs and The compatibility of the state machine of data link layer, link training, optional symmetric links stopped status and to the side for robust communication The control of band signal.Therefore, embodiment is provided implements PCIe using limited modification^TMAffairs and data link layer are in terms of and not Same link-speeds and asymmetric link.In addition, using link manager according to embodiments of the present invention, can realize to leading to more Support, asymmetric link configuration, sideband unification and the dynamic bandwidth scaling in road, while further realizing different communication protocol layer Between bridge joint.

Referring now to Figure 5, showing the state diagram 500 for Link Training State Machine, it can be according to of the invention real Apply the part of the link manager of example.As shown in Figure 5, link training can start from detection state 510.This state is upper Occur during reset, and suitable for upstream and downstream port.After the completion of reset, the passage of all configurations can be changed to given State, i.e. HIBERN8 states, every one end of the link can use sideband channel for example via PRESENCE in the state Signal signals.It should be noted that in this detection state, high impedance signal, i.e. DIF-Z letters can be driven on all passages Number.

Therefore, when signal is sent and receives PRESENCE events, control is transferred to configuration status by detection state 510 520, and drive on the passage of all configurations this high impedance.In configuration status 520, PHY parameters can be configured, and once Completed on all collocation channels that the link is each held, then for example can indicate to configure ready signal using sideband interconnection （CFG-RDY）, while maintaining high impedance on all passages.

Therefore instruction is prepared once being interconnected via sideband and sending and receive this configuration, control is just transferred to stopped status 530.I.e. in this L0.STALL state, PHY is changed to STALL states, and continues to drive high resistant on all collocation channels It is anti-.As can be seen, whether can be used for transmitting or receiving depending on data, control can be transferred to active state L1（State 530）、 Low power state（L1 states 540）, deep low power state（L1.OFF states 545）Or return to configuration status 520.

Therefore, in STALL states, negative drive signal DIF-N can be transmitted on the passage of all configurations.Then, when When being guided by starter, BURST sequences can be started.Therefore, in transmission MARKER0（MK0）After symbol, control is transferred to active State 530.

In one embodiment, receiver can detect the exiting from STALL states on the passage of all configurations, and root According to such as MIPI regulation enforcements bit lock and symbol lock.In the embodiment with multichannel link, this MK0 symbol can be used In setting up passage to passage deskew.

Low power state is directed on the contrary, working as（That is L1 states 540）When, the passages of all configurations can change to SLEEP states.Then when being directed to deeper low power state（That is L1.OFF states 545）When, the passages of all configurations can be with Change to HIBERN8 states.Finally, when being vectored back to configuration status, similarly, the Channel-shifted of all configurations is extremely HIBERN8 states.

Referring still to Fig. 5, transmitted for alive data, therefore control be transferred to active state 550.Especially, this is chain Road and transaction layer begin to use data link layer packets（DLLP）The state of information is exchanged with TLP.In such manner, it is possible to occur effectively Load transmission, and at the end of such transmission, TAIL OF BURST symbols can be transmitted.

As can be seen, control can be back to STALL states 530, to recovery state 560 by the transmission of this active state（Example As in response to receiver mistake, or when being directed in another manner）Or to deeper low-power（For example, L2）State 570.

In order to return to the stopped status, transmitter can send EIOS sequences, back on the passage of all configurations It is that TAIL of BURST are indicated.

If mistake occurs or guided in another manner, control can also be transferred to recovery state 560.Herein, change extremely Recover to cause the passage of all configurations to enter STALL states in the two directions.In order to realize this, can mutually it be connected in sideband GO TO STALL signals are sent, and the transmitter of this signal being capable of wait-for-response.When this stopping signal has been sent and connect Time receiving, as described sideband mutually connect the GO TO STALL of reception and indicate indicated, control is communicated back to STALL states 530. It is noted that therefore this recovery state sets up the agreement to coordinate while entering in STALL states using sideband.

On low power state L1 and L1.OFF, operate according to state 540 and 545.Especially, control from STALL states L1 low power states 540 are transferred to, enable to PHY being placed in SLEEP states., can be all in this state Negative drive signal, i.e. DIF-N signals are driven on the passage of configuration.When being directed to exit the state, control transmission is back to STALL states, for example, mutually connect signal in sideband and send PRESENCE signals.

Also as can be seen, when meeting all L1.OFF conditions, deeper low state L1.OFF can be entered.In an implementation In example, these conditions can include complete power gating or turn off the power of PHY unit.In this deeper low power state In, PHY can be placed in HIBERN8 states, and high impedance signal is driven on the passage of all configurations.In order to exit this One state, controls transmission to be back to STALL states via DIF-N is driven on the passage of all configurations.

Further as seen in Figure 5, there may be additivity, i.e. further deeper low power state（L2） 570, when preparing to turn off power, the further deeper low power state can be entered from active state（L2）570.One In individual embodiment, this state can be with PCIe^TMThat of specification is identical.

With reference now to table 2, show according to PCIe^TMThe LTSSM states of specification and corresponding M- according to embodiments of the present invention Mapping between PHY states.

Table 2

LTSSM states	M-PHY states	Details
			Detection, poll	SAVE	Pass through the State Transferring of the sub- states of SAVE
Configuration	BURST	BURST（PREP、SYNC）Sub- state
			Recover	BURST/SLEEP/STALL	BURST states are may be at, but will be changed by SLEEP/STALL to BURST
L0	BURST（Pay(useful) load）	BURST patterns and exchange affairs
			L0s	STALL	STALL states
L1	SLEEP	SLEEP states
			L1.OFF	HIBERN8	HIBERN8
L2	UNPOWERED	UNPOWERED states
			Disabling	DISABLED	DISABLED states
Loopback	Attonity	When entering loopback from configuration, link-speeds can change
			Hot reset	INLINE RESET	INLINE RESET states

Above with reference to described in Fig. 2, embodiment provides a kind of system that can be used in supporting in link management and optional band One sideband mechanism.By this way, using side-band circuits and interconnection, link management and control can be independently of for main interconnection The more high speed of physical layer（And bigger power consumption）Circuit and occur.Further by this way, as the PHY associated with main interconnection When the part of unit is de-energized, this sideband channel can be used, realizes that power consumption is reduced.Moreover, before main interconnection is trained energy Enough unify sideband mechanism using this, and can also be used when master mutually connects failure.

Yet further, unify sideband mechanism via this, single interconnection in each direction, such as difference can be deposited Line pair, so as to reduce number of pins and realize the new ability of increase.Embodiment can also realize faster, more robust clock/power door Control, and this link can be used to eliminate in such as PCIe^TMAmbiguity in the normal protocol of sideband mechanism etc.

But the scope of the present invention not limited to this, in different embodiments, sideband interconnection（For example, Fig. 2 sideband interconnection 270） The two-way one way signal collection of mongline bidirectional sideband signals, two-wire can be implemented as, signal transmitter system in weathering zone（Such as use In low powder pulsed width modulated（PWM）M-PHY in pattern is available）Or be embodied as sending mechanism with interior high speed signal, Such as physical layer ordered set or DLLP.

As example rather than for purposes of limitation, various physical layer methods can be supported.When being interconnected using sideband, First method can be to provide the mongline bidirectional sideband signals of minimum number of pins.In certain embodiments, can be existing This signal, such as PERST#, WAKE# or CLKREQ signal are multiplexed on sideband.Second method can be that two-wire is two-way One way signal collection, it can be simpler and more efficient in a way compared to single line method, but cost is additional pins.Energy Enough this embodiments of multichannel subdivision on existing sideband, such as the PERST# of host device and for device Host CLKREQ#（In this example, existing sense is maintained, simplifies double mode embodiment）.The third method can be with It is signal transmitter system in weathering zone, such as M-PHY LS PWM modes, it reduces number of pins relative to sideband mechanism, and can Still to support similar low power level.Because this operator scheme and high speed operation mutual exclusion, it can be with such as thing Manage the high speed in-band mechanisms combination of layer ordered set or DLLP etc.Although this method is not low-power, it is maximised With the general character of existing High-speed I/O.When being combined with the transmission of low speed inband signaling, this method can provide good low-power solution Certainly scheme.

In order to realize the one or more in these configurations in a given system, using the teaching of the invention it is possible to provide semantic layer, it can be used in The implication of information exchanged above physical layer and strategic layer is determined, the implication can be used in understanding the dynamic of equipment/platform rank Work/reaction.In one embodiment, these layers may reside in SB PHY units.

By providing layered approach, embodiment allows that sideband ability can be included（Because simplicity and/or low-power are grasped Make, it can be preferred in some embodiments）And with interior（It can be for other embodiment it is preferred, for example Avoid additional need for number of pins）Both different physical layer embodiments.

In one embodiment, for example multiple sideband signals can be disposed for via unified sideband via semantic layer Mechanism（Or in-band mechanisms）The single packet of communication.In one embodiment, table 3 below shows in one embodiment Each signal that there may be.In shown table, the logical direction of signal is shown by arrow, wherein upward arrow be defined as to Main frame（For example, root complex）Direction, and lower arrow is defined as to equipment（For example, ancillary equipment, such as wireless electrolytic Certainly scheme）Direction.

Table 3

Equipment presence ↑

Power is good ↓

Power-off ↓

Reference clock is good ↓

Basis reset ↓

Configuration preparation ↑ ↓

Preparation training ↑ ↓

Start training ↑ ↓

L1pg requests ↑ ↓

L1pg refusals ↑ ↓

L1pg mandates ↑ ↓

OBFF CPU are active ↓

OBFF DMA↓

The OBFF free time ↓

Wake up ↑

The response reception shaken hands ↑ ↓.

Referring now to Figure 6, showing the flow chart of each state for sideband mechanism according to embodiments of the present invention.Such as Shown in Fig. 6, these each states can be on root complex（For example, host computer control is operated）.State diagram 600 can be provided Control via the main frame to each state.As can be seen, operation starts from pre-boot state 610, in a state can There is signal in transmission.It is noted that it is this exist signal can be operated as mentioned above for link management it is described as.Then, control Boot state 620 is transferred to, various signals, i.e. power good signal, reset signal, reference clock can be transmitted in a state Status signal and preparation training signal.It should be noted that all these signals can be transmitted via single packet, wherein these signals In each can correspond to the designator or field of the packet（For example, 1 bit indicator of packet）.

Referring still to Fig. 6, control passes next to active state 630, and wherein system may be at active state（Example Such as, S0）, corresponding device（For example, upstream device can be active device state（For example, D0）And link may be at active State, shutdown or low power state（For example, L0, L0s or L1）.As can be seen, in this state, various letters can be transmitted Number, including OBFF signals, clock request signal, reference clock state, request L0 signals and preparation training signal.

Next, for example performing after above-mentioned signal transmission, control can be transferred to low power state 640.As can be seen, exist In this low power state 640, the system may be at active state, while equipment may be at the low work(of relatively low delay Rate state（For example, D3 is warm）.In addition, the link may be at given low power state（For example, L2 or L3）.Such as at these Seen in state, wake-up signal, reset signal and power can be included via the signal of unified sideband data bag transmission good Signal.

When the system enters deeper low power state, the second low power state 650 can be entered（For example, when described When system is in S0 states and the equipment and is in D3 cold states and the link and is similarly in L2 or L3 states.Such as It is seen, identical can be transmitted and wake up, reset and power good signal.It is also seen in figure 6, in deeper low power state 660（For example, system low power state S3）With equipment low power state（For example, D3 is cold）And identical link low power state Identical signal can occur in L2 and L3.Though it is shown that this specific set of side information of transmission, it is to be understood that of the invention Scope not limited to this.

Embodiment thus provides hierarchy, with respect to flexibility tension simplicity and low latency Ductility.In this way it is possible to existing sideband signals and additional sideband signals are replaced with fewer number of signal, and The following extension of sideband mechanism is realized in the case where not increasing more pins.

Referring now to Figure 7, showing a kind of flow chart of method according to embodiments of the present invention.As shown in Figure 7, method 700 can be used for transmitting data via the protocol stack of polymerization, and the protocol stack of the polymerization includes the upper strata and not of communication protocol The lower floor of same communication protocol, such as physical layer.In shown example, it is assumed that the protocol stack polymerizeing as described above, that is, have There is PCIe^TMThe upper affairs and data link layer and different specification of agreement（Such as MIPI specifications）Physical layer.It is, of course, also possible to deposit In the additional logic for enabling the two communication protocols to be polymerized to single protocol stack, such as above for Fig. 4 logics discussed and Circuit.

As seen in Figure 7, method 700 can start from receiving the first affairs in the protocol stack of the first communication protocol （Frame 710）.For example, the various logic of the root complex of kernel, other enforcement engines etc. are sought to send information to another set It is standby.Therefore, this information can be transferred to transaction layer.As can be seen, control is transferred to frame 720, and wherein affairs can be processed And it is supplied to the PHY of the second communication protocol logical gate.This processing can include what is discussed above for Fig. 4 flow Various operations, wherein can occur to receive data, perform the various operations such as flow control, link operation, packaging operation.In addition, energy It is enough to occur to provide various operations of the data link layer packets to PHY.Next, control is transferred to frame 730, wherein can be This first affairs is converted into the second form affairs in PHY logical gate.For example, being able to carry out any conversion of symbol （When needing）.In addition, can be performed with therefore the affairs are converted into the form for transmitting on said link Various conversion operations.Therefore, control can be transferred to frame 740, wherein can via link by this second form affairs from PHY is sent to equipment.As example, the second form affairs can be the serialized data after line coding, serialization etc..Although In Fig. 7 embodiment with this it is high-level show, it is to be understood that the scope of the present invention not limited to this.

Referring now to Figure 8, showing a kind of block diagram of component present in computer system according to embodiments of the present invention. As shown in Figure 8, system 800 can include many different components.These components can be implemented as IC, its part, discrete Electronic equipment or be fitted to such as computer system motherboard or insertion card etc circuit board other modules, or be embodied as with Other mode merges the component in the cabinet of computer system.It is furthermore noted that Fig. 8 block diagram is intended to show that computer system The high level view of many components.However, it is to be understood that there may be add-on assemble in some embodiments, and in addition, The different arrangements of shown component can occur in other embodiment.

As seen in Figure 8, processor 810（It can be the low power multi-core processor of such as ultralow voltage processor Slot）The Main Processor Unit and central hub communicated for the various assemblies with the system can be served as.This processor SoC can be implemented as.In one embodiment, processor 810 can be based on Intel^®Framework Core^TMProcessor（It is all The such processor of i3, i5, i7 or another that can be such as obtained from California Santa Clara Intel company）.However, it is to be understood that Can be alternatively in the presence of micro- can such as being set from the senior of California Sunnyvale in such as other embodiments of apple A5 processors Standby company（AMD）The other low-power processors obtained, the design based on ARM from ARM companies Pty Ltd or MIPS Technologies Inc. or their design based on MIPS for obtaining permission person or adopter from California Sunnyvale.

Processor 810 can be communicated with system storage 815, and system storage 815 can be deposited in embodiment by multiple Storage device is implemented to provide the system storage of specified rate.As example, the memory can be according to combined electronics assembly work Cheng Huiyi（JEDEC）Based on low-power double data rate（LPDDR）Design, such as according to JEDEC JESD 209-2E's Current LPDDR2 standards（In April, 2009 publishes）, or make LPDDR3, will provide to LPDDR2 extension to increase bandwidth LPDDR standards of future generation.As example, there may be 2/4/8 GB（GB）System storage, and can via one or Multiple memory interconnection are couple to processor 810.In various embodiments, individual memory devices can have different envelopes Type is filled, such as single die is encapsulated（SDP）, dual-die encapsulation（DDP）Or four die packages（QDP）.These equipment are in some realities Applying can be soldered directly on motherboard in example to provide low profile solution, and in other embodiments, the equipment energy One or more memory modules are enough configured to, it then can be couple to motherboard by given connector.

In order to provide information（Data, using, one or more operating systems etc.）Lasting storage, massage storage 820 can also be couple to processor 810.In embodiments, in order to realize thinner and lighter system design, and in order to change Enter system responsiveness, this massage storage can be implemented via SSD.However, in other embodiments, massage storage can be with Mainly use hard disk drive（HDD）To implement, wherein small amount SSD memory serves as SSD caches and closed so as to realize The non-volatile memories of background state and other this type of informations during machine event, occur to enable when restarting system activity Fast powering-up.It also shows that flash memory device 822 can be couple to processor 810, such as via SPI in Fig. 8 （SPI）.This flash memory device can be provided including basic input/output software（BIOS）And other firmwares of the system is The non-volatile memories of system software.

There may be various input/output in system 800（IO）Equipment.Display is particularly illustrated in Fig. 8 embodiment 824, it can be the High Resolution LCD or LED panel configured in the cap of cabinet.This display pannel can also be provided Touch-screen 825, such as external adapter on the display pannel to cause interacting via user and this touch-screen, user Input can be supplied to system to realize desired operation, such as on presentation of information, message reference.In one embodiment In, display 824 can be couple to processor 810 via the display interconnection that can be implemented as high performance graphicses interconnection.Touch Processor 810 can be couple to via another interconnection by touching screen 825, and it can be I in one embodiment²C is interconnected.As in Fig. 8 It is further illustrated, except touch-screen 825, can also occurs by user's input of touch manner via touch pad 830, touch pad 830 can be only fitted in the cabinet, and can also be couple to and the identical I of touch-screen 825²C is interconnected.

Calculated and other purposes for perceiving, various sensors may reside in the system, and can be by different way It is coupled to processor 810.Some inertia and environmental sensor can pass through sensor hub 840（For example via I²C is mutual Even）It is couple to processor 810.In fig. 8 in shown embodiment, these sensors can include accelerometer 841, environment light sensation Device（ALS）842nd, compass 843 and gyroscope 844.In one embodiment, other environmental sensors can include one or more Heat sensor 846, it can be via System Management Bus（SMBus）Bus is couple to processor 810.It is also to be understood that according to this The embodiment of invention, one or more sensors can be couple to processor 810 via LPS links.

Also seen in Fig. 8, various ancillary equipment can also be via low pin count（LPC）Interconnection is couple to processor 810. In shown embodiment, various assemblies can be coupled to by embedded controller 835.These components can include keyboard 836 （For example, being coupled to via PS2 interfaces）, fan 837 and heat sensor 839.In certain embodiments, touch pad 830 can be with EC835 is couple to via PS2 interfaces.In addition, safe processor（Such as according to trust computing group（TCG）TPM specification versions 1.2（On October 2nd, 2003）Such as credible platform module（TPM）838）Processing can also be couple to via this LPC interconnection Device 810.

System 800 can be with various modes and peripheral communications including wireless mode.Shown embodiment in fig. 8 In, there are various wireless modules, each of which can correspond to the radio configured for particular wireless communication protocols.It is a kind of For short distance（Such as near field）The mode of interior radio communication can be via near-field communication（NFC）Unit 845, in one embodiment In, near-field communication（NFC）Unit 845 can communicate via SMBus with processor 810.It should be noted that via this NFC unit 845, the equipment being closely adjacent to each other can communicate.For example, by the way that two equipment of close relation are adapted to together and information is realized （Such as identification information, payment information, data of view data etc.）Transmission, user can enable system 800 with it is another （For example）Portable equipment（The smart phone of such as user）Communication.NFC system can also be used to perform wireless power transmission.

As seen by further in fig. 8, additional radio-cell can include other short-distance radio engines, include WLAN Unit 850 and bluetooth unit 852.Using WLAN unit 850, it can realize according to given electric and EEA Eelectronic Eengineering Association （IEEE）The Wi-Fi communications of 802.11 standards, while via bluetooth unit 852, can occur the short distance via Bluetooth protocol Communication.These units can be via such as USB link or Universal Asynchronous Receive transmitter（UART）Link leads to processor 810 Letter.Or these units can be interconnected via interconnection via the low-power of all polymerization PCIe/MIPI as described herein interconnection or Such as serial date transfer/output（SDIO）Another such agreement of standard is couple to processor 810.Of course, it is possible at one Or the actual physics connection on multiple insertion cards between these ancillary equipment for configuring can be by being fitted to the NGFF connections of motherboard The mode of device.

In addition, wireless wide-area communication（For example according to honeycomb or other wireless wide-area agreements）Can be via can then couple To subscriber identification's module（SIM）857 WWAN units 856 occur.In addition, in order to realize the reception of positional information and use, There can also be GPS module 855.It should be noted that in fig. 8 in shown embodiment, WWAN units 856 and such as camera module 854 integrated capture device can be via given usb protocol（Such as USB2.0 or 3.0 links）, or UART or I²C agreements are led to Letter.The actual physics connection of these units is again able to the NGFF connections for blocking via NGFF is inserted and being fitted to and being configured on motherboard Device.

In order to provide audio input and output, audio process can be via digital signal processor（DSP）860 implement, It can be via high definition audio（HAD）Link is couple to processor 810.Similarly, DSP860 can with integrated encoder/ Decoder（CODEC）And amplifier 862 communicates, integrated encoder/decoder（CODEC）And amplifier 862 can then be coupled To the output loudspeaker 863 that can implement in cabinet.Similarly, amplifier and CODEC862 can be coupled to from microphone 865 receive audio input, and microphone 865 can implement defeated to provide high quality audio in embodiment via double array microphones Enter to realize that the voice activation to various operations in system is controlled.It is furthermore noted that audio output can from amplifier/ COEDC862, which is provided, arrives earphone jack 864.

Therefore, it is possible to use embodiment in many varying environments.Referring now to Figure 9, show can be together with embodiment The instance system 900 used.As can be seen, system 900 can be smart phone or other wireless communicators.Such as Fig. 9 block diagram Shown in, system 900 can include BBP 910, and it can handle Base-Band Processing task and application processing Polycaryon processor.Therefore, BBP 910 is able to carry out the various signal transactings on communication, and performs for institute State the calculating operation of equipment.Then, BBP 910 can be couple to user interface/display 920, user interface/display Device 920 can be realized by touch-screen display in certain embodiments.In addition, BBP 910 can be couple to memory System, it includes nonvolatile memory in the embodiment in fig. 9（That is flash memory 930）And system storage（I.e. dynamic random is deposited Access to memory（DRAM）935）.As further seen, BBP 910 can be further coupled to capture device 940, all If the image capture device of record video and/or rest image.

In order to realize the transmission and reception of communication, various circuits can be coupled between BBP 910 and antenna 980. Especially, there may be radio frequency（RF）Transceiver 970 and WLAN（WLAN）Transceiver 975.In general, RF transceivers 970 can be used for according to such as according to CDMA（CDMA）, global system for mobile communications（GSM）, Long Term Evolution（LTE）Or its The given wireless communication protocol of such as 3G or 4G wireless communication protocols of its agreement receives and transmitted wireless data and called. The other radio communications for such as receiving or transmitting radio signal, such as AM/FM, or HA Global Positioning Satellite can also be provided （GPS）Signal.In addition, via WLAN transceiver 975, additionally it is possible to realize local area radio signal, such as marked according to Bluetooth Accurate or IEEE802.11 standards（Such as IEEE802.11a/b/g/n）.It should be noted that BBP 910 and transceiver 970 and Link between one or both of 975 can be interconnected via combining and mapping PCIe interconnection and low-power（Such as MIPI is mutual Even）Function low-power polymerization interconnection.Although in Fig. 9 embodiment with this it is high-level show, it will be appreciated that the present invention Scope not limited to this.

Embodiment can be used in many different types of systems.For example, in one embodiment, communication equipment can be by It is arranged as performing various methods and technology as described herein.Certainly, the scope of the present invention is not limited to communication equipment, and conversely Ground, other embodiments can be related to other types of devices for process instruction, or one or more machine readable medias, including The equipment is caused to perform the finger of one or more methods and technology as described herein in response to being performed on the computing device Order.

Embodiment can be with code implementation, it is possible to be stored on non-transitory storage medium, non-transitory storage medium With it is being stored thereon, can be used in System Programming to perform the instruction of the instruction.The storage medium can include, But it is not limited to：Any type of disk, including floppy disk, CD, solid-state drive（SSD）, compact disk read-only storage（CD- ROM）, rewritable compact disk（CD-RW）, and magneto-optic disk；Semiconductor equipment, such as read-only storage（ROM）, arbitrary access deposits Reservoir（RAM）（Such as dynamic random access memory（DRAM）, static RAM（SRAM））, erasable programmable Read-only storage（EPROM）, flash memory, Electrically Erasable Read Only Memory（EEPROM）；Magnetically or optically block or suitable for storage electricity Any other type media of sub-instructions.

Although describing the present invention on a limited number of embodiment, it will be appreciated by those skilled in the art that by it Lai Many modifications and variations.Appended claim is intended to cover fall into true spirit and scope of the present invention all and such repaiied Change and change.

Claims

1. a kind of device for link training and management, including：

Quickly interconnected for peripheral assembly^TM（PCIe^TM）The protocol stack of communication protocol, the protocol stack includes transaction layer and link Layer；And

Physics（PHY）Unit, is couple to the protocol stack to provide described device via physical link and be couple to described device Equipment room communication, the physical location has low power communication agreement, and including according to the low power communication agreement Physical location circuit and the logical layer by the protocol stack and the physical location circuit interface, the logical layer include performing institute State the Link Training State Machine of the link training of physical link, and including by the PCIe^TMFirst additional character of communication protocol It is mapped to the mapping logic of the second additional character of the low power communication agreement.

2. device as claimed in claim 1, wherein, the physical link have from described device to the equipment with from described Equipment to the asymmetric width of described device, and the physical link can be configured to from described device to the equipment with from institute Equipment is stated to the asymmetric frequency operation of described device.

3. device as claimed in claim 1, wherein the Link Training State Machine with the equipment in the case where not consulting In advance by physical link from the reset initialization of described device to initial link circuit width and frequency.

4. device as claimed in claim 3, wherein the Link Training State Machine with the equipment in the case where not consulting Cause change in the link width of the physical link.

5. device as claimed in claim 1, further comprises described device is coupled with the equipment room and physics chain The sideband channel of road separation, the sideband channel includes the serial chain with the second physical location separated with the physical location Road, and there is signal first and be transferred to the equipment in wherein described second physical location, and receive second from the equipment There is signal, the Link Training State Machine has signal and configure described in response to receiving second in the second physical location Physical link.

6. a kind of method for link training and management, including：

It is being couple to via physical link in the first integrated circuit of the second integrated circuit, in response to first integrated circuit Upper electricity, perform includes the physics of physical location circuit with low power communication agreement（PHY）The Link Training State Machine of unit Detection state, the physical location is couple to for including transaction layer and the peripheral assembly of link layer is quickly interconnected^TM （PCIe^TM）The protocol stack of communication protocol；

After the detection state is performed, in first integrated circuit, the configuration shape of the Link Training State Machine is performed State, including configuration ready signal is sent to described via the sideband link coupled between first and second described integrated circuit Two integrated circuits；And

In first integrated circuit, match somebody with somebody in response to receiving second from second integrated circuit via the sideband link Ready signal is put, the stopped status of Link Training State Machine is performed, wherein during the stopped status, the physical location exists Difference n-signal is driven on the physical link.

7. method as claimed in claim 6, further comprises：Start burst sequences in the stopped status, to be transformed into In the active state of the Link Training State Machine.

8. method as claimed in claim 7, further comprises：In the active state, by pay(useful) load from described first Integrated circuit is sent to second integrated circuit, and transmits the afterbody of burst afterwards to be transformed into the shutdown shape State.

9. method as claimed in claim 6, further comprises：From the stopped status is transformed into the first low power state, And the difference n-signal is driven on the physical link in first low power state.

10. method as claimed in claim 9, further comprises：In response to integrated from described second via the sideband link Circuit, which is received, has signal, and the stopped status is transformed into from first low power state.

11. method as claimed in claim 9, further comprises：When meeting one group of predetermined condition, turn from the stopped status The second low power state is changed to, second low power state is less than first low power state, and low described second Difference high impedance signal is driven in power rating on the physical link.

12. method as claimed in claim 7, further comprises：In response to receiver mistake, it is transformed into from the active state Recovery state.

13. method as claimed in claim 6, further comprises：

Via the sideband channel second integrated circuit is sent to by enabling signal is shut down；And

Described stop is transformed into response to receiving shutdown indication signal from second integrated circuit via the sideband link Machine state.

14. method as claimed in claim 7, further comprises：In response to what is received in physical location from the protocol stack Communicate and be transformed into off-position from the active state.

15. a kind of system for link training and management, including：

Polycaryon processor, including multiple kernels and realize the communication between the polycaryon processor and ancillary equipment via physical link Protocol stack, the protocol stack includes：

Quickly interconnected according to peripheral assembly^TM（PCIe^TM）The transaction layer of communication protocol；

According to the PCIe^TMThe data link layer of communication protocol；And

According to low power communication agreement including physical layer transmission controller and physics（PHY）The physical layer of unit transmission circuit, Wherein described physical layer transmission controller is fitted to the physical location transmission circuit with PCIe^TMThe transaction layer of communication protocol And data link layer, the physical layer further comprises the Link Training State Machine for performing the link training of the physical link, And including by the PCIe^TMFirst additional character of communication protocol is mapped to the second additional character of the low power communication agreement Mapping logic；And

It is couple to the ancillary equipment of the polycaryon processor.

16. system as claimed in claim 15, wherein the Link Training State Machine：In response to the upper of the polycaryon processor Electricity, performs the configuration status of the Link Training State Machine after perform detection state, including via in the polycaryon processor The sideband link send configuration ready signal coupled between the ancillary equipment gives the ancillary equipment；And in response to via institute Sideband link is stated to receive the second configuration ready signal from the ancillary equipment and perform the shutdown of the Link Training State Machine State, wherein during the stopped status, the physical location transmission circuit drives difference N to believe on the physical link Number.

17. system as claimed in claim 16, wherein the Link Training State Machine starts burst in the stopped status Sequence to be transformed into the active state of the Link Training State Machine, and in the active state by pay(useful) load from described Polycaryon processor is sent to the ancillary equipment, and transmits the afterbody of burst afterwards to change to the stopped status.

18. system as claimed in claim 17, wherein the Link Training State Machine opens shutdown via the sideband link Dynamic signal is sent to the ancillary equipment, and in response to receiving shutdown from the ancillary equipment via the sideband link Indication signal and change to the stopped status.

19. system as claimed in claim 15, wherein the ancillary equipment includes multi radio integrated circuit.

20. a kind of equipment for link training and management, including：

For being couple to via physical link in the first integrated circuit of the second integrated circuit, in response to the described first integrated electricity The upper electricity on road, perform includes the physics of physical location circuit with low power communication agreement（PHY）The link training shape of unit The device of the detection state of state machine, the physical location is couple to for including transaction layer and the peripheral assembly of link layer is quickly mutual Even^TM（PCIe^TM）The protocol stack of communication protocol；

For after the detection state is performed, in first integrated circuit, matching somebody with somebody for the Link Training State Machine is performed Configuration state device, including for via the sideband link coupled between first and second described integrated circuit configuration ready signal It is sent to the device of second integrated circuit；And

For in first integrated circuit, in response to receiving from second integrated circuit via the sideband link Two configuration ready signals, perform the device of the stopped status of Link Training State Machine, wherein during the stopped status, it is described Physical location drives difference n-signal on the physical link.

21. equipment as claimed in claim 20, further comprises：For starting burst sequences in the stopped status, with It is transformed into the device in the active state of the Link Training State Machine.

22. equipment as claimed in claim 21, further comprises：For in the active state, by pay(useful) load from institute State the first integrated circuit and be sent to second integrated circuit, and transmit the afterbody of burst afterwards to be transformed into described stop The device of machine state.

23. equipment as claimed in claim 20, further comprises：For being transformed into the first low-power shape from the stopped status In state, and the device of the difference n-signal is driven in first low power state on the physical link.

24. equipment as claimed in claim 23, further comprises：For in response to via the sideband link from described second Integrated circuit, which is received, has signal, and the device of the stopped status is transformed into from first low power state.

25. equipment as claimed in claim 23, further comprises：For when meeting one group of predetermined condition, being shut down from described State Transferring drives difference high to the second low power state, and in second low power state on the physical link The device of impedance signal, second low power state is less than first low power state.

26. equipment as claimed in claim 21, further comprises：For in response to receiver mistake, from the active state It is transformed into the device of recovery state.

27. equipment as claimed in claim 20, further comprises：

Device for shutdown enabling signal to be sent to second integrated circuit via the sideband channel；And

For being transformed into institute in response to receiving shutdown indication signal from second integrated circuit via the sideband link State the device of stopped status.

28. equipment as claimed in claim 21, further comprises：For in response to being connect in physical location from the protocol stack The communication of receipts and the device that off-position is transformed into from the active state.

29. a kind of machine readable media, with the instruction being stored thereon, causes computing device to hold when executed Method of the row according to any one of claim 6-14.