CN203553167U - Airtight encapsulation structure of Hall hybrid integrated circuit - Google Patents
Airtight encapsulation structure of Hall hybrid integrated circuit Download PDFInfo
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- CN203553167U CN203553167U CN201320345525.XU CN201320345525U CN203553167U CN 203553167 U CN203553167 U CN 203553167U CN 201320345525 U CN201320345525 U CN 201320345525U CN 203553167 U CN203553167 U CN 203553167U
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- hall
- mounting groove
- integrated circuit
- hybrid integrated
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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Abstract
The utility model provides an airtight encapsulation structure of Hall hybrid integrated circuit, which comprises a ceramic housing having a mounting groove, a Hall element and a CMOS conditioning circuit encapsulated in the mounting groove, and a gold-plated cover of the mounting groove coated on the outer edge of the mounting groove for airtight encapsulation, wherein the Hall element by a gold wire is connected with the ceramic housing, the conditioning circuit by an aluminium-silicon wire is connected with the ceramic housing, and the ceramic housing provided with a printed wire therein is connected with the Hall element, the CMOS conditioning circuit and a plurality of pins extending out the ceramic housing. The utility model provides a compact structure of encapsulation structure that is a small size (3.8mm*5.4mm81.7mm) which is 76% of the traditional single-chip Hall integrated circuit airtight encapsulation housing volume, ensuring the implementation of the airtight encapsulation of the Hall hybrid integrated circuit.
Description
Technical field
The utility model relates to Hall hybrid integrated circuit design field, in particular to a kind of air-tight packaging structure of Hall hybrid integrated circuit of high radiation preventing.
Background technology
Hall integrated circuit is a kind of magneto-dependent sensor, and the Hall effect principle of take is its working foundation, with them, can detect magnetic field and variation thereof, can in the various occasions relevant with magnetic field, use.By Hall integrated circuit, by physical quantity such as the power of many non-electricity, non-magnetic, moment, pressure, stress, position, displacement, speed, acceleration, angle, angular speed, revolution, rotating speed etc., be transformed into electric weight to detect and control; Equally also can carry out to electric weight such as electric current, voltage, power measurement and the control of full isolation.
A kind of high radiation preventing Hall hybrid integrated circuit with independent intellectual property right designs the Hall hybrid integrated circuit that becomes a kind of high radiation preventing by the CMOS modulate circuit chip package of the Hall element chip of arsenide gallium monocrystal material and silicon single crystal material in same air-tight packaging structure, there are many advantages: sound construction, volume is little, lightweight, the life-span is long, easy for installation, power consumption is little, radioresistance, vibration resistance, pollution or the corrosion of not being afraid of dust, greasy dirt, steam and salt fog etc.Be mainly used on the Aeronautics and Astronautics device of China, on control device in the control appliance of nuclear blast environment, high radiation environment, these fields are very high to the requirement of the stability of Hall integrated circuit, reliability, long-life and high radiation preventing ability (comprising anti-neutron radiation and anti-60Co γ-rays source ionising radiation accumulated dose).
Utility model content
The utility model object is to provide a kind of encapsulating structure of improved Hall hybrid integrated circuit, and compact conformation, volume is little and have good stability and reliability.Full foot the needs of air-tight packaging structure of high radiation preventing Hall hybrid integrated circuit.
For reaching above-mentioned purpose, the technical scheme that the utility model adopts is as follows:
The encapsulating structure of Hall hybrid integrated circuit, comprise a ceramic package with mounting groove, be packaged in Hall element and the CMOS modulate circuit in described mounting groove and cover at the outward flange of described mounting groove and for the gold-plated cover plate of mounting groove described in air-tight packaging, wherein said Hall element is connected with ceramic package by a spun gold, described modulate circuit is connected with the outer Sales of pottery by Si-Al wire, and the outer Sales of described pottery inside is laid with printed circuit cable and connects Hall element, CMOS modulate circuit and a plurality of pin stretching out outside ceramic package.
Further, described Hall element and CMOS modulate circuit are all encapsulated in mounting groove with chip form.
Further, described Hall element, CMOS modulate circuit are also connected with a plurality of pressure welding point, pressure welding point also with the printed circuit cable of ceramic Sales inside with described in the pin that stretches out outside ceramic package be connected.The design Ji Full foot that this inner lead connects the interconnective needs of two chips, make again that outer Sales volume is little, compact conformation.
Further, thickness H and width D that described three ends stretch out the pin outside ceramic package are respectively 0.15mm and 0.5mm, and the distance between adjacent pin center is 1.27mm.
Further, it is characterized in that, described ceramic package length is 5.4mm, and width is 3.8mm, and thickness is 1.4mm, in described mounting groove, is two-stage stepped construction, and the height H 1 of wherein closing on described gold-plated cover plate one-level is 0.5mm, and the height H 2 of another grade is 0.4mm.
Further, the maximum length in described mounting groove is of a size of 2.8mm, and greatest width dimension is 2.2mm.
Further, described gold-plated cover plate is fixed on by golden tin solder on the outward flange of described mounting groove and carries out air-tight packaging.
From above the technical solution of the utility model, the volume of compact conformation, the volume little (3.8mm * 5.4mm * 1.7mm) of the encapsulating structure of the utility model Hall hybrid integrated circuit and more traditional air-tight packaging structure (4.5mm * 6mm * 1.7mm) has had and has significantly been reduced to 76% of traditional volume, has guaranteed the realization of Hall hybrid integrated circuit air-tight packaging.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the encapsulating structure of the utility model preferred embodiment.
Fig. 2 be in Fig. 1 encapsulating structure at the structural representation of other direction.
Fig. 3 is the outer Sales dimensional drawing of encapsulating structure in Fig. 1, and unit is mm.
The inside printed circuit cable schematic diagram of Fig. 4 encapsulating structure.
Embodiment
In order more to understand technology contents of the present utility model, especially exemplified by specific embodiment and coordinate appended graphic being described as follows.
As shown in Figure 1 and Figure 2, according to preferred embodiment of the present utility model, the encapsulating structure of Hall hybrid integrated circuit comprises a ceramic package 1 with mounting groove, be packaged in mounting groove Hall element 3 and modulate circuit 4 and cover at the outward flange of described mounting groove and for sealing the metal cover board 6 of described mounting groove, Hall element 3 is connected with CMOS modulate circuit 4, in the present embodiment, Hall element 3 and modulate circuit 4 are chip form and are encapsulated in mounting groove.Hall element chip Bian that Hall element chip 3 is preferably arsenide gallium monocrystal material complete the connection of chip and the outer Sales of pottery by spun gold 2 ultrasonic bonding techniques, modulate circuit 4 is preferably the CMOS modulate circuit chip of silicon single crystal material, and Bian completes the connection of chip and the outer Sales of pottery by Si-Al wire 5 ultrasonic bonding techniques.The outer Sales of described pottery inside is laid with printed circuit cable 8 for connecting Hall element, CMOS modulate circuit and a plurality of pin (a, b, c) stretching out outside ceramic package.The design Ji Full foot that this inner lead connects the interconnective needs of two chips, make again that outer Sales volume is little, compact conformation.The design of the technique lead-out wire 9 in Fig. 4 has guaranteed the requirement of the craft of gilding of inner printed circuit cable and pressure welding point.
With reference to figure 3, the other end of pin stretches out outside ceramic package 1.The thickness h of pin and width d are respectively 0.15mm and 0.5mm.Distance between adjacent pin center is 1.27mm.
In the present embodiment, the Hall element 3 of arsenide gallium monocrystal material and the CMOS modulate circuit 4 of silicon single crystal material are all encapsulated in mounting groove with chip form: first with silver slurry distributor, import conducting resinl point is dropped on mounting groove base, with vacuum cups, two kinds of chips are arranged on relevant position respectively, then adopt precuring (100 ℃ ± 5 ℃, 0.5h, N2) and rear (200 ℃ ± 5 ℃, 2h, the N2) technique of solidifying to be cured.
Described gold-plated cover plate 6 is fixed on by golden tin solder 7 on the outward flange of described mounting groove and carries out air-tight packaging.
Shown in figure 3, the length of ceramic package 1 is 5.4mm, and width is 3.8mm, and thickness is 1.4mm, in described mounting groove, is two-stage stepped construction, and the height H 1 of wherein closing on that one-level of metal cover board 6 is 0.5mm, and the height H 2 of another grade is 0.4mm.Maximum length in mounting groove is of a size of 2.8mm, and greatest width dimension is 2.2mm.
Shown in figure 4, Hall element 3, CMOS modulate circuit 4 are also connected with a plurality of pressure welding point 10, pressure welding point 10 also with the printed circuit cable 8 of ceramic Sales inside with described in the pin that stretches out outside ceramic package be connected.In figure, 11 is the ceramic bottom of outer Sales cartridge chip, and 12 is outer Sales pressure welding point ceramic layer, and 13 is exit pin pad.
In sum, the compact conformation of the encapsulating structure of Hall hybrid integrated circuit provided by the invention, the volume of the outer Sales (4.5mm * 6mm * 1.7mm) of volume little (3.8mm * 5.4mm * 1.7mm) and more traditional air-tight packaging has had significantly and has reduced, and has guaranteed the realization of Hall hybrid integrated circuit air-tight packaging.
Although the utility model discloses as above with preferred embodiment, so it is not in order to limit the utility model.Under the utility model, in technical field, have and conventionally know the knowledgeable, within not departing from spirit and scope of the present utility model, when being used for a variety of modifications and variations.Therefore, protection range of the present utility model is when being as the criterion depending on claims person of defining.
Claims (6)
1. the air-tight packaging structure of a Hall hybrid integrated circuit, it is characterized in that, comprise that one has the ceramic package of mounting groove, be packaged in Hall element and CMOS modulate circuit in described mounting groove, and cover at the outward flange of described mounting groove and for the gold-plated cover plate of mounting groove described in air-tight packaging, wherein said Hall element is connected with ceramic package by a spun gold, described modulate circuit is connected with the outer Sales of pottery by Si-Al wire, the outer Sales of described pottery inside is laid with printed circuit cable and connects Hall element, CMOS modulate circuit and a plurality of pin stretching out outside ceramic package.
2. the air-tight packaging structure of Hall hybrid integrated circuit according to claim 1, is characterized in that, described Hall element and CMOS modulate circuit are all encapsulated in mounting groove with chip form.
3. the air-tight packaging structure of Hall hybrid integrated circuit according to claim 1, it is characterized in that, described Hall element, CMOS modulate circuit are also connected with a plurality of pressure welding point, pressure welding point also with the printed circuit cable of ceramic Sales inside with described in the pin that stretches out outside ceramic package be connected.
4. the air-tight packaging structure of Hall hybrid integrated circuit according to claim 3, it is characterized in that, thickness H and width D that described three ends stretch out the pin outside ceramic package are respectively 0.15mm and 0.5mm, and the distance between adjacent pin center is 1.27mm.
5. according to the air-tight packaging structure of the Hall hybrid integrated circuit described in any one in claim 1～4, it is characterized in that, described ceramic package length is 5.4mm, width is 3.8mm, thickness is 1.4mm, in described mounting groove, be two-stage stepped construction, the height H 1 of wherein closing on described gold-plated cover plate one-level is 0.5mm, and the height H 2 of another grade is 0.4mm.
6. the air-tight packaging structure of Hall hybrid integrated circuit according to claim 5, is characterized in that, the maximum length in described mounting groove is of a size of 2.8mm, and greatest width dimension is 2.2mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320345525.XU CN203553167U (en) | 2013-06-14 | 2013-06-14 | Airtight encapsulation structure of Hall hybrid integrated circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320345525.XU CN203553167U (en) | 2013-06-14 | 2013-06-14 | Airtight encapsulation structure of Hall hybrid integrated circuit |
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| CN203553167U true CN203553167U (en) | 2014-04-16 |
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| CN201320345525.XU Expired - Lifetime CN203553167U (en) | 2013-06-14 | 2013-06-14 | Airtight encapsulation structure of Hall hybrid integrated circuit |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106229301A (en) * | 2016-08-01 | 2016-12-14 | 中国电子科技集团公司第五十八研究所 | A kind of air-tightness surface attaching type digital isolator encapsulating structure |
| CN107316937A (en) * | 2017-06-28 | 2017-11-03 | 吉林省贝林电子技术有限责任公司 | A kind of preparation method of automobile sensor chip |
| CN108447845A (en) * | 2018-05-21 | 2018-08-24 | 臻驱科技（上海）有限公司 | A kind of power semiconductor modular substrate and power semiconductor modular |
| CN115666210A (en) * | 2022-12-12 | 2023-01-31 | 南京中旭电子科技有限公司 | Ceramic air-tight packaged high-sensitivity Hall element and packaging device thereof |
-
2013
- 2013-06-14 CN CN201320345525.XU patent/CN203553167U/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106229301A (en) * | 2016-08-01 | 2016-12-14 | 中国电子科技集团公司第五十八研究所 | A kind of air-tightness surface attaching type digital isolator encapsulating structure |
| CN106229301B (en) * | 2016-08-01 | 2018-10-30 | 中国电子科技集团公司第五十八研究所 | A kind of air-tightness surface attaching type digital isolator encapsulating structure |
| CN107316937A (en) * | 2017-06-28 | 2017-11-03 | 吉林省贝林电子技术有限责任公司 | A kind of preparation method of automobile sensor chip |
| CN108447845A (en) * | 2018-05-21 | 2018-08-24 | 臻驱科技（上海）有限公司 | A kind of power semiconductor modular substrate and power semiconductor modular |
| CN115666210A (en) * | 2022-12-12 | 2023-01-31 | 南京中旭电子科技有限公司 | Ceramic air-tight packaged high-sensitivity Hall element and packaging device thereof |
| CN115666210B (en) * | 2022-12-12 | 2023-04-07 | 南京中旭电子科技有限公司 | Ceramic air-tight packaged high-sensitivity Hall element and packaging device thereof |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
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Granted publication date: 20140416 |