CN203339153U - Multi-chip packaging structure - Google Patents
Multi-chip packaging structure Download PDFInfo
- Publication number
- CN203339153U CN203339153U CN2013203724472U CN201320372447U CN203339153U CN 203339153 U CN203339153 U CN 203339153U CN 2013203724472 U CN2013203724472 U CN 2013203724472U CN 201320372447 U CN201320372447 U CN 201320372447U CN 203339153 U CN203339153 U CN 203339153U
- Authority
- CN
- China
- Prior art keywords
- chip
- iron
- nickel alloy
- chips
- packaging structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Sampling And Sample Adjustment (AREA)
Abstract
The utility model discloses a multi-chip packaging structure. The packaging structure is characterized by comprising an iron-nickel alloy frame, at least two layers of chips, a plurality of wires and insulating resin. The iron-nickel alloy frame includes a plurality of pins, two sinking parts and a carrier platform between the two sinking parts. The top of the sinking part is connected with the pins, and the bottom of the sinking part is connected with the carrier platform. The frame is made of iron-nickel alloy for the reason that the expansion coefficients of iron and nickel are similar to that of the chip. The at least two layers of chips are stacked on the carrier platform. The plurality of wires are electrically connected between the chips and between the chips and the iron-nickel alloy frame. The wires are gold wires, and are used for electric connection of the chips by the routing-welding combination technology. The packaging space of the packaging structure is filled with the insulating resin. According to the utility model, the carrier platform of the frame is subjected to sinking process, forming a groove structure, such that the packaging structure is capable of packaging four layers of chips, having the advantages of large capacity, good chip smoothness and no gas residual in the cavity.
Description
Technical field
The utility model belongs to the semiconductor packaging field, is specifically related to a kind of structure that can carry out multi-chip package by changing support Design.
Background technology
In existing encapsulating products, because down-lead bracket does not reach requirement for the restriction of the microscope carrier design of supporting chip, the technological ability of welding chip, generally can only hold 1-2 layer chip, otherwise chip too much may cause chip to leak outside in whole encapsulation cavity, affect the reliability of product, such product chips number of plies is low, and capacity is little.
Summary of the invention
The purpose of this utility model is to provide a kind of multichip packaging structure.
For realizing above-mentioned utility model purpose, the utility model has adopted following technical scheme:
A kind of multichip packaging structure, is characterized in that, comprising:
One iron-nickel alloy support, have a plurality of pins, two sedimentations part and two subsidence part microscope carrier between dividing; The upper end of described sedimentation part is connected with this pin, and the lower end of described sedimentation part is connected with this microscope carrier; The support that adopts the iron-nickel alloy material is because the coefficient of expansion and the chip of iron nickel are close.Described iron-nickel alloy support 5 adopts the compression molding techniques one-shot forming.
Layers of chips at least, stacked-up configuration is on described microscope carrier;
Multiple conducting wires, be electrically connected between chip and chip, between chip and iron-nickel alloy support; Wire is gold thread, adopts routing to carry out the electric connection of chip in conjunction with solder technology.
The insulating resin of filling in the encapsulated space of encapsulating structure.
The support that adopts the iron-nickel alloy material is because the coefficient of expansion and the chip of iron nickel are close.
Further, described chip and chip or chip and iron-nickel alloy support adhesive tape bonding.
Further, comprise four layers of chip, described four layers of chip stagger successively and are superimposed on the microscope carrier of described copper stent.
The technological process of manufacturing above-mentioned multichip packaging structure is as follows:
Chip grinds and synthesize-> pin forming of cutting-> chip-stacked-> gold thread welding-> resin.
At first chip is ground to the thickness that encapsulation needs; and cut into discrete component; then four layers of chip stack of staggering successively; the welding gold thread; connect chip and chip; chip and support electronic circuit, inner each device of the synthetic whole cavity protection of resin, pin forming is so that client is welded on PCB circuit version.During encapsulation, need special requirement to open vacuum and utilize tool control support steady, will under high pressure-temperature, toast and get rid of the gas in cavity simultaneously.
The utility model advantage:
The support microscope carrier of multichip packaging structure described in the utility model forms groove structure through the processing of subsidence process, can carry out four layers of chip package, and capacity is large, and the chip planarization is strong, and cavity is interior without gas residue.
The accompanying drawing explanation
The profile that Fig. 1 is the utility model multichip packaging structure.
Wherein, the 1, first chip; 2, the second chip; 3, the 3rd chip; 4, four-core sheet; 5, iron-nickel alloy support; 6, gold thread; 7, insulating resin; 51, microscope carrier; 52, sedimentation part; 53, pin.
Embodiment
Below in conjunction with accompanying drawing and a preferred embodiment, the technical solution of the utility model is further described.
Embodiment:
As shown in Figure 1: a kind of multichip packaging structure, comprise an iron-nickel alloy support 5, there is the microscope carrier 51 between a plurality of pin 53, two sedimentation parts 52 and two sedimentation parts 52; The upper end of described sedimentation part 52 is connected with this pin 53, and the lower end of described sedimentation part 52 is connected with this microscope carrier 51; Described iron-nickel alloy support 5 adopts the compression molding techniques one-shot forming; The support that adopts the iron-nickel alloy material is because the coefficient of expansion and the chip of iron nickel are close.
Four layers of chip, the stacked-up configuration that staggers successively, on described microscope carrier 51, is the first chip 1, the second chip 2, the 3rd chip 3, four-core sheet 4 from the bottom up successively;
Multiple conducting wires is gold thread 6, is electrically connected between chip and chip, between chip and iron-nickel alloy support; Wire is gold thread, adopts routing to carry out the electric connection of chip in conjunction with solder technology.Concrete gold thread syndeton is that 4 dozens of gold threads of four-core sheet are electrically connected at the 3rd chip 3, the 3rd 3 dozens of chips gold thread is electrically connected at the second chip 2, the second 2 dozens of chips gold thread is electrically connected at 1 dozen of gold thread of the first chip 1, the first chip and is electrically connected at iron-nickel alloy support 5.
Also comprise the insulating resin 7 of filling in the encapsulated space of encapsulating structure.
Described chip and chip or chip and iron-nickel alloy support adhesive tape bonding.
It is to be noted; as described above is only in order to explain the preferred embodiment of the utility model; not attempt is done any formal restriction to the utility model according to this; be with; all any modification or changes that the relevant the utility model of doing under identical utility model spirit is arranged, all must be included in the category that the utility model is intended to protection.
Claims (3)
1. a multichip packaging structure, is characterized in that, comprising:
One iron-nickel alloy support, have a plurality of pins, two sedimentations part and two subsidence part microscope carrier between dividing; The upper end of described sedimentation part is connected with this pin, and the lower end of described sedimentation part is connected with this microscope carrier;
Layers of chips at least, stacked-up configuration is on described microscope carrier;
Multiple conducting wires, be electrically connected between chip and chip, between chip and iron-nickel alloy support;
The insulating resin of filling in the encapsulated space of encapsulating structure.
2. multichip packaging structure according to claim 1, is characterized in that, described chip and chip or chip and iron-nickel alloy support adhesive tape bonding.
3. multichip packaging structure according to claim 2, is characterized in that, comprises four layers of chip, and described four layers of chip stagger successively and are superimposed on the microscope carrier of described copper stent.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013203724472U CN203339153U (en) | 2013-06-26 | 2013-06-26 | Multi-chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013203724472U CN203339153U (en) | 2013-06-26 | 2013-06-26 | Multi-chip packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203339153U true CN203339153U (en) | 2013-12-11 |
Family
ID=49707815
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013203724472U Expired - Fee Related CN203339153U (en) | 2013-06-26 | 2013-06-26 | Multi-chip packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203339153U (en) |
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2013
- 2013-06-26 CN CN2013203724472U patent/CN203339153U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131211 Termination date: 20210626 |