CN203325953U - Double-face high-efficiency heterojunction battery containing intrinsic layers - Google Patents
Double-face high-efficiency heterojunction battery containing intrinsic layers Download PDFInfo
- Publication number
- CN203325953U CN203325953U CN2013203445633U CN201320344563U CN203325953U CN 203325953 U CN203325953 U CN 203325953U CN 2013203445633 U CN2013203445633 U CN 2013203445633U CN 201320344563 U CN201320344563 U CN 201320344563U CN 203325953 U CN203325953 U CN 203325953U
- Authority
- CN
- China
- Prior art keywords
- layer
- double
- intrinsic
- intrinsic layer
- solar cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/548—Amorphous silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Photovoltaic Devices (AREA)
Abstract
The utility model discloses a double-face high-efficiency heterojunction battery containing intrinsic layers. The structure of the double-face high-efficiency heterojunction battery containing the intrinsic layers includes a back electrode, a first ITO layer, an amorphous N+ layer, a first intrinsic layer, a first suede layer, an N-type monocrystalline silicon substrate, a second suede layer, a quantum dot structure silicon nitride layer, a second intrinsic layer, an amorphous P layer, a second ITO layer and a positive electrode. The double-face high-efficiency heterojunction battery containing the intrinsic layers is simple in structure. The intrinsic layers can realize a good inactivation effect in reducing interface states and dangling bonds, so that open-circuit voltage and short-circuit current can be increased and the conversion efficiency is high.
Description
Technical field
The utility model relates to a kind of solar cell, particularly relates to a kind of double-side efficient hetero-junction solar cell containing intrinsic layer, belongs to technical field of solar cell manufacturing.
Background technology
The universal greatest problem of solar battery technology is that cost is high and photoelectric conversion efficiency battery is low.Chinese patent literature CN103022020A " high efficiency amorphous silicon and Copper Indium Gallium Selenide are folded structure solar cell technology ", and Chinese patent literature CN102856421A " a kind of novel three-junction thin film solar cell ", two inventions are all by the stacked sunlight absorbing wavelength scope of expanding of battery structure, reach the purpose that improves transformation efficiency.But the laminated cell cost is higher, variety of issue easily appears between layers.Once punch-through occur between layers, whole battery will be scrapped.
Research is found, quantum-dot structure makes the motion of Charge carrier all be subject to strong restrictions on three-dimensional, have obvious quantum size effect, this causes the electronic band structure of semiconductor silicon to change, and particularly band gap presents regular the variation with the quantum spot size.In highdensity quantum point group, the quantum dot that size is little can absorb the sunlight of high-energy scope, so the change in size of quantum dot just can change the absorbing wavelength of light, the whole matching degree of raising and solar spectrum.
The utility model content
The double-side efficient hetero-junction solar cell containing intrinsic layer that provides a kind of transformation efficiency high is provided the purpose of this utility model.
For solving the problems of the technologies described above, the technical solution of the utility model is such, a kind of double-side efficient hetero-junction solar cell containing intrinsic layer, it is characterized in that: this battery structure from bottom to top comprises back electrode, an ITO layer, amorphous N+ layer, the first intrinsic layer, the first matte layer, n type single crystal silicon substrate, the second matte layer, quantum-dot structure silicon nitride layer, the second intrinsic layer, amorphous P layer, the 2nd ITO layer and positive electrode successively.
Preferably, described the first intrinsic layer and the second intrinsic layer thickness are 10nm.
Preferably, the thickness of described quantum-dot structure silicon nitride layer is 10nm.
In a specific embodiment of the present utility model, described the first matte layer and the second matte layer are the pyramid suede structure.
Preferably, described pyramid suede structure height is 4～6 μ m.
Preferably, a described ITO layer and the 2nd ITO layer thickness are 100nm.
The advantage of technical scheme provided by the utility model is, the battery of this structure, and it is simple in structure, and intrinsic layer can play good passivation, reduces interfacial state and dangling bonds, thereby improves open circuit voltage and short circuit current, and conversion efficiency is high.Its preparation method is simple, can produce on line and realize at traditional heterojunction.Conversion efficiency is high, thereby has reduced cost.
The accompanying drawing explanation
Fig. 1 is the utility model structural representation.
Embodiment
Below in conjunction with embodiment, the utility model is described in further detail, but not as to restriction of the present utility model.
As shown in Figure 1, this battery structure from bottom to top comprises back electrode 1, an ITO layer 2, amorphous N+ layer 3, the first intrinsic layer 4, the first matte layer 5, n type single crystal silicon substrate 6, the second matte layer 7, quantum-dot structure silicon nitride layer 8, the second intrinsic layer 9, amorphous P layer 10, the 2nd ITO layer 11 and positive electrode 12 to cell piece structure of the present utility model successively.
The preparation method of embodiment 1 cell piece is:
(a) prepare the pyramid suede structure on the n type single crystal silicon substrate, chemical solvent used is NaOH, making herbs into wool additive TCS and deionized water, volume ratio NaOH:TCS: deionized water=5.3:15:156.13, the n type single crystal silicon substrate is placed in the complete chemical solvent of configuration and keeps 20 minutes in 80 ℃ of waters bath with thermostatic control, form pyramidal average height between 4um, obtain the n type single crystal silicon substrate, the n type single crystal silicon substrate is used to washed with de-ionized water 3 minutes, take out, use N
2Dry up 10 minutes;
(b) using plasma strengthens the silicon nitride film that chemical vapour deposition technique contains the silicon quantum dot structure in an on-chip side preparation, and the gas flow passed into is NH
3=800sccm, SiH
4=1000sccm, substrate temperature: 180～200 ℃, the radio-frequency power of plasma is 55W, and chamber pressure is 1 * 10
-2Torr, the thickness of quantum-dot structure silicon nitride layer is 10nm;
(c) using plasma strengthen chemical vapour deposition technique respectively cell piece just, the back side plating passivation layer, i.e. the first intrinsic layer and the second intrinsic layer.Each gas flow wherein passed into is: PH3/H2=6100sccm; SiH4=2000sccm; H2=7000sccm; Pressure is 0.9Torr, and power is 4500W, and temperature is 220 ℃, and the first intrinsic layer and the second intrinsic layer thickness are 10nm;
(d) using plasma enhancing chemical vapour deposition technique deposits P type amorphous silicon membrane on the second intrinsic layer, and the gas flow passed into is: B2H6/H2=20sccm; SiH4=1500sccm; H2=7000sccm; Pressure is 1Torr, and power is 2000W, and temperature is 210 ℃.；
(e) using plasma enhancing chemical vapour deposition technique plates amorphous N+ layer on the first intrinsic layer.Each gas flow wherein passed into is: PH3/H2=6100sccm; SiH4=2000sccm; H2=7000sccm; Pressure is 0.9Torr, and power is 4500W, and temperature is 232 ℃.
(f) adopt magnetron sputtering technique cell piece just, the back side plates an ITO layer and the 2nd ITO layer, the ITO layer thickness is 100nm;
(g) adopt screen printing technique cell piece just, the back side stamps silver electrode.
The preparation method of embodiment 2 cell pieces is:
(a) prepare the pyramid suede structure on the n type single crystal silicon substrate, chemical solvent used is NaOH, making herbs into wool additive TCS and deionized water, volume ratio NaOH:TCS: deionized water=5.3:15:156.13, the n type single crystal silicon substrate is placed in the complete chemical solvent of configuration and keeps 20 minutes in 80 ℃ of waters bath with thermostatic control, form pyramidal average height between 5um, obtain the n type single crystal silicon substrate, the n type single crystal silicon substrate is used to washed with de-ionized water 3 minutes, take out, use N
2Dry up 10 minutes;
(b) using plasma strengthens the silicon nitride film that chemical vapour deposition technique contains the silicon quantum dot structure in an on-chip side preparation, and the gas flow passed into is NH
3=800sccm, SiH
4=1000sccm, substrate temperature: 180～200 ℃, the radio-frequency power of plasma is 55W, and chamber pressure is 1 * 10
-2Torr, the thickness of quantum-dot structure silicon nitride layer is 10nm;
(c) using plasma strengthen chemical vapour deposition technique respectively cell piece just, the back side plating passivation layer, i.e. the first intrinsic layer and the second intrinsic layer.Each gas flow wherein passed into is: PH3/H2=6100sccm; SiH4=2000sccm; H2=7000sccm; Pressure is 0.9Torr, and power is 4500W, and temperature is 220 ℃, and the first intrinsic layer and the second intrinsic layer thickness are 10nm;
(d) using plasma enhancing chemical vapour deposition technique deposits P type amorphous silicon membrane on the second intrinsic layer, and the gas flow passed into is: B2H6/H2=20sccm; SiH4=1500sccm; H2=7000sccm; Pressure is 1Torr, and power is 2000W, and temperature is 210 ℃.；
(e) using plasma enhancing chemical vapour deposition technique plates amorphous N+ layer on the first intrinsic layer.Each gas flow wherein passed into is: PH3/H2=6100sccm; SiH4=2000sccm; H2=7000sccm; Pressure is 0.9Torr, and power is 4500W, and temperature is 232 ℃.
(f) adopt magnetron sputtering technique cell piece just, the back side plates an ITO layer and the 2nd ITO layer, the ITO layer thickness is 100nm;
(g) adopt screen printing technique cell piece just, the back side stamps silver electrode.
The preparation method of embodiment 3 cell pieces is:
(a) prepare the pyramid suede structure on the n type single crystal silicon substrate, chemical solvent used is NaOH, making herbs into wool additive TCS and deionized water, volume ratio NaOH:TCS: deionized water=5.3:15:156.13, the n type single crystal silicon substrate is placed in the complete chemical solvent of configuration and keeps 20 minutes in 80 ℃ of waters bath with thermostatic control, form pyramidal average height between 46um, obtain the n type single crystal silicon substrate, the n type single crystal silicon substrate is used to washed with de-ionized water 3 minutes, take out, use N
2Dry up 10 minutes;
(b) using plasma strengthens the silicon nitride film that chemical vapour deposition technique contains the silicon quantum dot structure in an on-chip side preparation, and the gas flow passed into is NH
3=800sccm, SiH
4=1000sccm, substrate temperature: 180～200 ℃, the radio-frequency power of plasma is 55W, and chamber pressure is 1 * 10
-2Torr, the thickness of quantum-dot structure silicon nitride layer is 10nm;
(c) using plasma strengthen chemical vapour deposition technique respectively cell piece just, the back side plating passivation layer, i.e. the first intrinsic layer and the second intrinsic layer.Each gas flow wherein passed into is: PH3/H2=6100sccm; SiH4=2000sccm; H2=7000sccm; Pressure is 0.9Torr, and power is 4500W, and temperature is 220 ℃, and the first intrinsic layer and the second intrinsic layer thickness are 10nm;
(d) using plasma enhancing chemical vapour deposition technique deposits P type amorphous silicon membrane on the second intrinsic layer, and the gas flow passed into is: B2H6/H2=20sccm; SiH4=1500sccm; H2=7000sccm; Pressure is 1Torr, and power is 2000W, and temperature is 210 ℃.；
(e) using plasma enhancing chemical vapour deposition technique plates amorphous N+ layer on the first intrinsic layer.Each gas flow wherein passed into is: PH3/H2=6100sccm; SiH4=2000sccm; H2=7000sccm; Pressure is 0.9Torr, and power is 4500W, and temperature is 232 ℃.
(f) adopt magnetron sputtering technique cell piece just, the back side plates an ITO layer and the 2nd ITO layer, the ITO layer thickness is 100nm;
(g) adopt screen printing technique cell piece just, the back side stamps silver electrode.
Claims (6)
1. the double-side efficient hetero-junction solar cell containing intrinsic layer, it is characterized in that: this battery structure from bottom to top comprises back electrode (1), an ITO layer (2), amorphous N+ layer (3), the first intrinsic layer (4), the first matte layer (5), n type single crystal silicon substrate (6), the second matte layer (7), quantum-dot structure silicon nitride layer (8), the second intrinsic layer (9), amorphous P layer (10), the 2nd ITO layer (11) and positive electrode (12) successively.
2. the double-side efficient hetero-junction solar cell containing intrinsic layer according to claim 1, described the first intrinsic layer (4) and the second intrinsic layer (9) thickness are 10nm.
3. the double-side efficient hetero-junction solar cell containing intrinsic layer according to claim 1, it is characterized in that: the thickness of described quantum-dot structure silicon nitride layer (8) is 10nm.
4. the double-side efficient hetero-junction solar cell containing intrinsic layer according to claim 1, it is characterized in that: described the first matte layer (5) and the second matte layer (7) are the pyramid suede structure.
5. the double-side efficient hetero-junction solar cell containing intrinsic layer according to claim 4, it is characterized in that: described pyramid suede structure height is 4～6 μ m.
6. the double-side efficient hetero-junction solar cell containing intrinsic layer according to claim 1, it is characterized in that: a described ITO layer (2) and the 2nd ITO layer (11) thickness are 100nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013203445633U CN203325953U (en) | 2013-06-14 | 2013-06-14 | Double-face high-efficiency heterojunction battery containing intrinsic layers |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013203445633U CN203325953U (en) | 2013-06-14 | 2013-06-14 | Double-face high-efficiency heterojunction battery containing intrinsic layers |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203325953U true CN203325953U (en) | 2013-12-04 |
Family
ID=49665259
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013203445633U Expired - Fee Related CN203325953U (en) | 2013-06-14 | 2013-06-14 | Double-face high-efficiency heterojunction battery containing intrinsic layers |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203325953U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108155265A (en) * | 2016-12-02 | 2018-06-12 | 财团法人金属工业研究发展中心 | Silicon-Based Heterojunction Solar Cell |
-
2013
- 2013-06-14 CN CN2013203445633U patent/CN203325953U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108155265A (en) * | 2016-12-02 | 2018-06-12 | 财团法人金属工业研究发展中心 | Silicon-Based Heterojunction Solar Cell |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103000741A (en) | Black heterogeneous crystalline cell and manufacture method thereof | |
| CN102738291B (en) | Silicon-based heterojunction double-side solar cell and preparation method thereof | |
| CN101866961A (en) | Light trapping structure for thin film silicon/crystalline silicon heterojunction solar battery | |
| CN101447518A (en) | Ant-apex contact heterojunction solar battery and preparation method thereof | |
| CN102403376B (en) | n-i-p heterojunction solar cell with silicon quantum dot and preparation method thereof | |
| CN103383975A (en) | Two-sided passivation efficient heterojunction battery and manufacturing method thereof | |
| CN102299206A (en) | Heterojunction solar cell and manufacturing method thereof | |
| JP2012186415A (en) | Manufacturing method of photoelectric conversion element, photoelectric conversion element, and tandem-type photoelectric conversion element | |
| CN102280500B (en) | Silicon quantum dot solar energy cell based on a heterojunction structure and preparation method thereof | |
| CN109449227A (en) | Silicon/crystalline silicon heterojunction solar battery electrode structure of lamination intrinsic layer and preparation method thereof | |
| CN113013277A (en) | Laminated solar cell and preparation method thereof | |
| CN103258919B (en) | Amorphous silicon and polysilicon membrane interface passivation and prepare the method for SPA structure HIT battery | |
| CN101510568A (en) | Amorphous silicon/dye sensitization laminated film solar battery and preparation method thereof | |
| CN103219413A (en) | Grapheme radial heterojunction solar cell and preparation method thereof | |
| CN103094378A (en) | Solar cell containing variable In component InGaN/GaN multilayer quantum well structure | |
| CN201323204Y (en) | Antapex contact heterojunction solar battery | |
| CN203325953U (en) | Double-face high-efficiency heterojunction battery containing intrinsic layers | |
| CN102931249A (en) | Cadmium selenide transparent thin film solar battery with graphene | |
| WO2023103409A1 (en) | Solar cell and preparation method therefor | |
| CN102157594B (en) | Superlattice quantum well solar battery and preparation method thereof | |
| CN214505521U (en) | Laminated solar cell | |
| CN203325921U (en) | N-type high-efficiency heterojunction battery | |
| CN103594536A (en) | Multi-junction multi-lamination silicon-based thin-film solar cell and manufacturing technology thereof | |
| CN203850312U (en) | Heterojunction solar cell with selective emitter | |
| CN103346195A (en) | Double-surface efficient heterojunction battery containing intrinsic layers and manufacturing method of double-surface efficient heterojunction battery |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131204 Termination date: 20160614 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |