CN203325921U - N-type high-efficiency heterojunction battery - Google Patents
N-type high-efficiency heterojunction battery Download PDFInfo
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- CN203325921U CN203325921U CN2013203369165U CN201320336916U CN203325921U CN 203325921 U CN203325921 U CN 203325921U CN 2013203369165 U CN2013203369165 U CN 2013203369165U CN 201320336916 U CN201320336916 U CN 201320336916U CN 203325921 U CN203325921 U CN 203325921U
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Abstract
The utility model discloses an N-type high-efficiency heterojunction battery comprises back electrodes, a first ITO layer, a first pile face layer, an N-type monocrystalline silicon chip, a second pile face layer, a quantum dot structure silicon nitride layer, an amorphous P layer, a second ITO layer and positive electrodes, wherein the back electrodes, the first ITO layer, the first pile face layer, the N-type monocrystalline silicon chip, the second pile face layer, the quantum dot structure silicon nitride layer, the amorphous P layer, the second ITO layer and the positive electrodes are all orderly arranged in a top-down manner. The N-type high-efficiency heterojunction battery of the utility model is characterized by simple structure, spectrum response range between 200 nm to 1400 nm, high open-circuit voltage, large short circuit current, and high conversion efficiency.
Description
Technical field
The utility model relates to a kind of solar cell, particularly relates to the efficient hetero-junction solar cell of a kind of N-type, belongs to technical field of solar cell manufacturing.
Background technology
Cost is high, and the photoelectric conversion efficiency of battery is low is the subject matter that hinders the solar battery technology popularization and application always.The key factor that affects the photoelectric conversion efficiency of solar cell is mainly that solar cell is narrower to the spectral absorption scope of sunlight, and the near infrared light that usually in solar spectrum, accounts for half left and right can't be used effectively.
Chinese patent literature CN103022020A " high efficiency amorphous silicon and Copper Indium Gallium Selenide are folded structure solar cell technology ", and Chinese patent literature CN102856421A " a kind of novel three-junction thin film solar cell ", two inventions are all by the stacked sunlight absorbing wavelength scope of expanding of battery structure, reach the purpose that improves transformation efficiency.But the laminated cell cost is higher, variety of issue easily appears between layers.Once punch-through occur between layers, whole battery will be scrapped.
Research is found, quantum-dot structure makes the motion of Charge carrier all be subject to strong restrictions on three-dimensional, have obvious quantum size effect, this causes the electronic band structure of semiconductor silicon to change, and particularly band gap presents regular the variation with the quantum spot size.In highdensity quantum point group, the quantum dot that size is little can absorb the sunlight of high-energy scope, so the change in size of quantum dot just can change the absorbing wavelength of light, the whole matching degree of raising and solar spectrum.
The utility model content
The purpose of this utility model is to provide a kind of sunlight wave absorption region wide, the efficient hetero-junction solar cell of the N-type that transformation efficiency is high.
For solving the problems of the technologies described above, the technical solution of the utility model is such, the efficient hetero-junction solar cell of a kind of N-type is characterized in that: this battery structure from bottom to top comprises back electrode, an ITO layer, the first matte layer, n type single crystal silicon substrate, the second matte layer, quantum-dot structure silicon nitride layer, amorphous P layer, the 2nd ITO layer and positive electrode successively.
Preferably, the thickness of described quantum-dot structure silicon nitride layer is 5～7nm.
In a specific embodiment of the present utility model, described the first matte layer and the second matte layer are the pyramid suede structure.
Preferably, described pyramid suede structure height is 4～6 μ m.
Preferably, a described ITO layer and the 2nd ITO layer thickness are 100nm.
The advantage of technical scheme provided by the utility model is, the battery of this structure, and it is simple in structure, and spectral response range is between 200nm～1400nm, and open circuit voltage is higher, and short circuit current is larger, and conversion efficiency is high.Its preparation method is simple, can produce on line and realize at traditional heterojunction.Conversion efficiency is high, thereby has reduced cost.
The accompanying drawing explanation
Fig. 1 is the utility model structural representation.
Embodiment
Below in conjunction with embodiment, the utility model is described in further detail, but not as to restriction of the present utility model.
As shown in Figure 1, this battery structure from bottom to top comprises back electrode 1, an ITO layer 2, the first matte layer 3, n type single crystal silicon substrate 4, the second matte layer 5, quantum-dot structure silicon nitride layer 6, amorphous P layer 7, the 2nd ITO layer 8 and positive electrode 9 to cell piece structure of the present utility model successively.
The preparation method of embodiment 1 cell piece is:
(a) prepare the pyramid suede structure on the n type single crystal silicon substrate, chemical solvent used is NaOH, making herbs into wool additive TCS and deionized water, volume ratio NaOH:TCS: deionized water=5.3:15:156.13, the n type single crystal silicon substrate is placed in the complete chemical solvent of configuration and keeps 20 minutes in 80 ℃ of waters bath with thermostatic control, form pyramidal average height between 4um, obtain the n type single crystal silicon substrate;
(b) using plasma strengthens the silicon nitride film that chemical vapour deposition technique contains the silicon quantum dot structure in an on-chip side preparation, and the gas flow passed into is NH
3: 800sccm, SiH
4: 1000sccm, substrate temperature: 180～200 ℃, the radio-frequency power of plasma is 55W, and chamber pressure is 1 * 10-2Torr, and the thickness of quantum-dot structure silicon nitride layer is 5nm;
(c) using plasma enhancing chemical vapour deposition technique deposits P type amorphous silicon membrane on silicon nitride film, and the gas flow passed into is: SiH
4: 800sccm, B
2H
6/ H
2: 4600sccm, H
2: 5100sccm, CH
4: 500sccm, radio-frequency power 3000W, substrate temperature is between 190 ℃;
(d) adopt magnetron sputtering technique cell piece just, the back side plates an ITO layer and the 2nd ITO layer;
(e) adopt screen printing technique cell piece just, the back side stamps silver electrode.
The preparation method of embodiment 2 cell pieces is:
(a) prepare the pyramid suede structure on the n type single crystal silicon substrate, chemical solvent used is NaOH, making herbs into wool additive TCS and deionized water, volume ratio NaOH:TCS: deionized water=5.3:15:156.13, the n type single crystal silicon substrate is placed in the complete chemical solvent of configuration and keeps 20 minutes in 80 ℃ of waters bath with thermostatic control, form pyramidal average height between 5um, obtain the n type single crystal silicon substrate;
(b) using plasma strengthens the silicon nitride film that chemical vapour deposition technique contains the silicon quantum dot structure in an on-chip side preparation, and the gas flow passed into is NH
3: 800sccm, SiH
4: 1000sccm, substrate temperature: 180～200 ℃, the radio-frequency power of plasma is 55W, and chamber pressure is 1 * 10-2Torr, and the thickness of quantum-dot structure silicon nitride layer is 6nm;
(c) using plasma enhancing chemical vapour deposition technique deposits P type amorphous silicon membrane on silicon nitride film, and the gas flow passed into is: SiH
4: 800sccm, B
2H
6/ H
2: 4600sccm, H
2: 5100sccm, CH
4: 500sccm, radio-frequency power 3000W, substrate temperature is between 200 ℃;
(d) adopt magnetron sputtering technique cell piece just, the back side plates an ITO layer and the 2nd ITO layer;
(e) adopt screen printing technique cell piece just, the back side stamps silver electrode.
The preparation method of embodiment 3 cell pieces is:
(a) prepare the pyramid suede structure on the n type single crystal silicon substrate, chemical solvent used is NaOH, making herbs into wool additive TCS and deionized water, volume ratio NaOH:TCS: deionized water=5.3:15:156.13, the n type single crystal silicon substrate is placed in the complete chemical solvent of configuration and keeps 20 minutes in 80 ℃ of waters bath with thermostatic control, form pyramidal average height between 46um, obtain the n type single crystal silicon substrate;
(b) using plasma strengthens the silicon nitride film that chemical vapour deposition technique contains the silicon quantum dot structure in an on-chip side preparation, and the gas flow passed into is NH
3: 800sccm, SiH
4: 1000sccm, substrate temperature: 180～200 ℃, the radio-frequency power of plasma is 55W, and chamber pressure is 1 * 10-2Torr, and the thickness of quantum-dot structure silicon nitride layer is 7nm;
(c) using plasma enhancing chemical vapour deposition technique deposits P type amorphous silicon membrane on silicon nitride film, and the gas flow passed into is: SiH
4: 800sccm, B
2H
6/ H
2: 4600sccm, H
2: 5100sccm, CH
4: 500sccm, radio-frequency power 3000W, substrate temperature is between 210 ℃;
(d) adopt magnetron sputtering technique cell piece just, the back side plates an ITO layer and the 2nd ITO layer;
(e) adopt screen printing technique cell piece just, the back side stamps silver electrode.
Claims (5)
1. the efficient hetero-junction solar cell of N-type, it is characterized in that: this battery structure from bottom to top comprises back electrode (1), an ITO layer (2), the first matte layer (3), n type single crystal silicon substrate (4), the second matte layer (5), quantum-dot structure silicon nitride layer (6), amorphous P layer (7), the 2nd ITO layer (8) and positive electrode (9) successively.
2. the efficient hetero-junction solar cell of N-type according to claim 1, it is characterized in that: the thickness of described quantum-dot structure silicon nitride layer (6) is 5～7nm.
3. the efficient hetero-junction solar cell of N-type according to claim 1, it is characterized in that: described the first matte layer (3) and the second matte layer (5) are the pyramid suede structure.
4. the efficient hetero-junction solar cell of N-type according to claim 3, it is characterized in that: described pyramid suede structure height is 4～6 μ m.
5. the efficient hetero-junction solar cell of N-type according to claim 1, it is characterized in that: a described ITO layer (2) and the 2nd ITO layer (8) thickness are 100nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013203369165U CN203325921U (en) | 2013-06-09 | 2013-06-09 | N-type high-efficiency heterojunction battery |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2013203369165U CN203325921U (en) | 2013-06-09 | 2013-06-09 | N-type high-efficiency heterojunction battery |
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| Publication Number | Publication Date |
|---|---|
| CN203325921U true CN203325921U (en) | 2013-12-04 |
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| CN2013203369165U Expired - Fee Related CN203325921U (en) | 2013-06-09 | 2013-06-09 | N-type high-efficiency heterojunction battery |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103337530A (en) * | 2013-06-09 | 2013-10-02 | 国电光伏有限公司 | N-shaped efficient heterojunction battery and manufacturing method thereof |
-
2013
- 2013-06-09 CN CN2013203369165U patent/CN203325921U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103337530A (en) * | 2013-06-09 | 2013-10-02 | 国电光伏有限公司 | N-shaped efficient heterojunction battery and manufacturing method thereof |
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| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131204 Termination date: 20160609 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |