CN203289480U - A multipath interface and E1 protocol converter - Google Patents
A multipath interface and E1 protocol converter Download PDFInfo
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- CN203289480U CN203289480U CN201320338142XU CN201320338142U CN203289480U CN 203289480 U CN203289480 U CN 203289480U CN 201320338142X U CN201320338142X U CN 201320338142XU CN 201320338142 U CN201320338142 U CN 201320338142U CN 203289480 U CN203289480 U CN 203289480U
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- protocol converter
- programmable logic
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Abstract
The utility model discloses a multipath interface and E1 protocol converter comprising a complex programmable logic device CPLD, a field-programmable gate array FPGA, a microprocessor, multifunctional interface chips, and an E1 line interface chip. Bidirectional conduction is achieved between the field-programmable gate array FPGA and the complex programmable logic device CPLD, and between the field-programmable gate array FPGA and the E1 line interface chip. Bidirectional conduction is achieved between the multifunctional interface chips and the complex programmable logic device CPLD. Bidirectional conduction is achieved between the microprocessor and the complex programmable logic device CPLD. Unidirectional conduction is achieved between the microprocessor and the complex programmable logic device CPLD. By the above structure, the multipath interface and E1 protocol converter is equipped with a multifunctional multiprotocol interface interface and is easy to control.
Description
Technical field
The utility model relates to the communications field, is specifically related to multichannel interface and E1 protocol converter.
Background technology
Along with the sustainable development of computer technology and the communication technology, people constantly increase high bandwidth requirements, and the application of the high speed communication networks such as access DDN (Digital Data Network) net, frame relay network is also more and more general.E1 is the transmission standard that China's telecommunication transmission net primary group uses, and speed is 2.048 Mb/s.Realize the mutual conversion of multichannel interface and E1 agreement, can be connected to simultaneously E1 circuit at a high speed to plurality of devices.Protocol converter can make to be on communication network and adopt the main frame of different upper-layer protocols still to work in coordination, and completes various Distributed Application.Also there is no the protocol converter based on FPGA (Field Programmable Gate Array) and microprocessor Design in prior art.Interface chip on the existing protocol transducer is single, and can not form multi-functional protocol interface interface and support RS232, RS449, EIA530, EIA-530-A, V.35, V.36, X.21 agreement, control more complicated.
The utility model content
The utility model has overcome the deficiencies in the prior art, and multichannel interface and E1 protocol converter are provided, and is provided with multi-functional multi-protocol interface interface, controls simpler.
for solving above-mentioned technical problem, the utility model is by the following technical solutions: multichannel interface and E1 protocol converter, comprise complex programmable logic device (CPLD), on-site programmable gate array FPGA, microprocessor, versatile interface chip and E1 line interface chip, described on-site programmable gate array FPGA and complex programmable logic device (CPLD) and the equal two-way admittance of E1 line interface chip, described versatile interface chip and complex programmable logic device (CPLD) two-way admittance, described microprocessor and complex programmable logic device (CPLD) two-way admittance, microprocessor and on-site programmable gate array FPGA one-way conduction.
Further, described versatile interface chip comprises versatile interface chip A and versatile interface chip B.
Further, the model of described versatile interface chip A is LTC1546.
Further, the model of described versatile interface chip B is LTC1544.
Further, described microprocessor while and data storage RAM and Data Buffer Memory Flash diconnected.
Further, the model of described E1 line interface chip is XRT82D20.
Compared with prior art, the beneficial effects of the utility model are:
1, versatile interface chip A LTC1546 and versatile interface chip B LTC1544, both combinations, form Full Featured multi-protocol interface interface, supports RS232, RS449, EIA530, EIA-530-A, V.35, V.36, X.21 agreement, the selection of agreement can be undertaken by software fully, uses more convenient.
2, complex programmable logic device (CPLD), support the multiple interfaces level, is used for completing V.35, and RS 449, RS 232 data transmit-receives.
Description of drawings
Fig. 1 is theory diagram of the present utility model.
Embodiment
Below in conjunction with accompanying drawing, the utility model is further elaborated, embodiment of the present utility model is not limited to this.
Embodiment:
As shown in Figure 1, the utility model comprises complex programmable logic device (CPLD), on-site programmable gate array FPGA, microprocessor, versatile interface chip and E1 line interface chip, and the model of E1 line interface chip is XRT82D20.The on-site programmable gate array FPGA of the present embodiment and complex programmable logic device (CPLD) and E1 line interface chip equal two-way admittance, versatile interface chip and complex programmable logic device (CPLD) two-way admittance.The microprocessor of the present embodiment and complex programmable logic device (CPLD) two-way admittance, microprocessor and on-site programmable gate array FPGA one-way conduction, microprocessor while and data storage RAM and Data Buffer Memory Flash diconnected.The versatile interface chip of the present embodiment comprises versatile interface chip A and versatile interface chip B, and the model of versatile interface chip A is LTC1546, and the model of versatile interface chip B is LTC1544.The model of complex programmable logic device (CPLD) wherein is EPM7256 AETCl44-7, and the model of on-site programmable gate array FPGA is EP3C25F324C8, and the model of microprocessor is MPC875.
Versatile interface chip A LTC1546 and versatile interface chip B LTC1544 combination, form Full Featured multi-protocol interface interface, supports RS232, RS449, EIA530, EIA-530-A, V.35, V.36, X.21 agreement, the selection of agreement can be undertaken by software fully, and is easy to use.Because versatile interface chip A LTC1546 and versatile interface chip B LTC1544 interface level are 5 V, on-site programmable gate array FPGA is not supported such interface voltage, uses CPLD to make interface circuit here.
Just can realize this utility model as mentioned above.
Claims (6)
1. multichannel interface and E1 protocol converter, it is characterized in that: comprise complex programmable logic device (CPLD), on-site programmable gate array FPGA, microprocessor, versatile interface chip and E1 line interface chip, described on-site programmable gate array FPGA and complex programmable logic device (CPLD) and the equal two-way admittance of E1 line interface chip, described versatile interface chip and complex programmable logic device (CPLD) two-way admittance, described microprocessor and complex programmable logic device (CPLD) two-way admittance, microprocessor and on-site programmable gate array FPGA one-way conduction.
2. multichannel interface according to claim 1 and E1 protocol converter, it is characterized in that: described versatile interface chip comprises versatile interface chip A and versatile interface chip B.
3. multichannel interface according to claim 2 and E1 protocol converter, it is characterized in that: the model of described versatile interface chip A is LTC1546.
4. multichannel interface according to claim 2 and E1 protocol converter, it is characterized in that: the model of described versatile interface chip B is LTC1544.
5. multichannel interface according to claim 1 and E1 protocol converter, is characterized in that: described microprocessor while and data storage RAM and Data Buffer Memory Flash diconnected.
6. multichannel interface according to claim 1 and E1 protocol converter, it is characterized in that: the model of described E1 line interface chip is XRT82D20.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320338142XU CN203289480U (en) | 2013-06-14 | 2013-06-14 | A multipath interface and E1 protocol converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320338142XU CN203289480U (en) | 2013-06-14 | 2013-06-14 | A multipath interface and E1 protocol converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203289480U true CN203289480U (en) | 2013-11-13 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320338142XU Expired - Fee Related CN203289480U (en) | 2013-06-14 | 2013-06-14 | A multipath interface and E1 protocol converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203289480U (en) |
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2013
- 2013-06-14 CN CN201320338142XU patent/CN203289480U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131113 Termination date: 20140614 |
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| EXPY | Termination of patent right or utility model |