CN202334008U

CN202334008U - Multi-network-port high-speed data transmission architecture

Info

Publication number: CN202334008U
Application number: CN2011205281959U
Authority: CN
Inventors: 刘海涛; 屈国旺; 陈洪雨; 陈贺; 吕燕石; 王强; 刘志明; 张虎祥
Original assignee: TIANJIN KELIN ELECTRIC CO Ltd
Current assignee: TIANJIN KELIN ELECTRIC CO Ltd
Priority date: 2011-12-15
Filing date: 2011-12-15
Publication date: 2012-07-11
Anticipated expiration: 2021-12-15

Abstract

The utility model provides a multi-network-port high-speed data transmission architecture, which comprises a central processing unit (CPU), a field programmable gate array (FPGA) unit and a network chip, wherein the CPU is connected with the FPGA unit through a data line, an address line and a control signal line; and the FPGA unit is connected with the network chip through the data line and the control signal line. The multi-network-port high-speed data transmission architecture has the advantages that: by adoption of an advanced reduced instruction set computer (RISC) machine (ARM)7 singlechip with main frequency of less than 100 M, requirements of a system can be met, and the cost of equipment is reduced; an error of a transmission interval of two adjacent packets is less than 1 microsecond, and the performance of the equipment is improved; every when a channel of Ethernet is expanded, the requirements for the system are greatly reduced, and hardware which is employed according to the scheme can be used for data transmission of 12 channels of Ethernet; and each network is completely independent.

Description

Multi-netmouth high speed data transfer framework

Technical field

The utility model belongs to intelligent grid sampled value transmission field, is applicable to that especially process layer and the wall at intelligent substation need transmit sampled value, needs the data transmission architecture of the situation of output multi-channel sampling value signal.

Background technology

Country is greatly developing intelligent grid at present; Its significant characteristics are exactly that sampled value is transmitting digitized; In some concrete application, need individual equipment output multi-channel sampling value signal; The every frame of regulation sends interval error and is no more than 10 microseconds in the standard, and the data of all transmissions all have temporal information, and this just has very high requirement to processing performance.

Present most of solution is a multiprocessors parallel processing, and perhaps the monolithic high-performance processor is through external bus expansion multichannel network interface card.These ways have not only increased equipment cost, also the program of equipment are brought the requirement of a lot of harshnesses, implement difficult, even if realize the also bad assurance of stability of back operation.

Also have sub-fraction to adopt exchange chip to realize the multichannel transmission in addition, send though this way can realize the physics multichannel, the content that many physical interfaces send is identical, and this way can only satisfy a very little part to be used, and does not possess versatility.

Sampled value transmission in the intelligent grid is commonly the IEC61850-9-2 form based on Ethernet; It is 4000 times/second that this message sends frequency; And require the transmission interval error of every frame to be not more than 10 microseconds, if equipment needs the multichannel Ethernet to send, 100M can't satisfy so harsh requirement with interior single-chip microcomputer so; Even if with platforms such as High Performance DSP or ARM9, it is also limited to stay the resource of doing other data processing.

Summary of the invention

The purpose of the utility model is to solve as above problem, and a kind of Multi-netmouth high speed data transfer framework is provided.

The technical scheme that the utility model adopts is: Multi-netmouth high speed data transfer framework; Comprise CPU element, FPGA unit and network chip; Said CPU element links to each other with said FPGA unit with control signal wire through data wire, address wire respectively, and said FPGA unit links to each other with said network chip with control signal wire through data wire.

Further, the dominant frequency of said CPU element is 10M-100M.

Further, said CPU element is ARM7.

Further, the quantity of said network chip is 1-12.

Advantage and the good effect that the utlity model has are: this programme employing monolithic 100M with regard to the feasible system requirement, has reduced equipment cost with interior ARM7; The transmission interval error that makes adjacent two bags has improved equipment performance less than 1 microsecond; Every expansion one road Ethernet significantly reduces the requirement of system, and the used hardware of this programme can satisfy 12 road Ethernet datas and send; Each complete network is independent.

Description of drawings

Fig. 1 is the system block diagram of the utility model.

Embodiment

As shown in Figure 1; The utility model comprises that dominant frequency is ARM7 CPU element, FPGA unit and the network chip of 60M; Said CPU element links to each other with said FPGA unit with control signal wire through data wire, address wire respectively, and said FPGA unit links to each other with control signal wire and 12 said network chips are parallel through data wire.

CPU element is responsible for gathering and handling the sampled value data; It is one or more packets of unit that data are processed into the ethernet frame; And having certain cushion space, CPU element is given FPGA unit through data wire with ethernet frame according to the parameter of configuration; FPGA unit internal needle all has a time counter to each physics Ethernet interface; Can trigger once new Frame blanking time and send when reaching to send, its with the buffering area of CPU element interface in find the packet that will send, send data to network chip through the data wire between FPGA unit and the ethernet controller.

When all-network interface transmission data are identical; CPU element has only a kind of for the Frame of FPGA unit; Inform that through address wire and control signal wire FPGA cell data bag needs all physical interfaces and hairdo to transmit, this moment, all physics Ethernet interface Counter Values were same value, and gave each network chip through data wire with concurrent form; This moment, the all-network interface was launched transmission simultaneously, was 0 error basically.

When needs send several kinds of different pieces of informations; CPU element is given FPGA the unit with several kinds of different Frames respectively; And inform that through address wire and control signal wire which or which network chip the current kind Frame in FPGA unit need send through; The time counter value of sending the identical network interface of data is also identical, and the FPGA unit sends corresponding network chip to through the bus concurrency formula with network chip, and different types of Frame sends to corresponding network chip successively; Send between the identical network interface of data content this moment is 0 error; Sending between the content various network interface has certain error, the time error of various network interface in 1 microsecond, basic 0 error of identical network interface.

More than the embodiment of the utility model is specified, but said content is merely the preferred embodiment of the utility model, can not be considered to be used to limit the practical range of the utility model.All equalizations of doing according to the utility model application range change and improve etc., all should still belong within the patent covering scope of the utility model.

Claims

1. Multi-netmouth high speed data transfer framework; Comprise CPU element, FPGA unit and network chip; It is characterized in that: said CPU element links to each other with said FPGA unit with control signal wire through data wire, address wire respectively, and said FPGA unit links to each other with said network chip with control signal wire through data wire.

2. Multi-netmouth high speed data transfer framework according to claim 1 is characterized in that: the dominant frequency of said CPU element is 10M-100M.

3. Multi-netmouth high speed data transfer framework according to claim 2 is characterized in that: said CPU element is ARM7.

4. Multi-netmouth high speed data transfer framework according to claim 1 is characterized in that: the quantity of said network chip is 1-12.