CN203289481U - An interface and E1 protocol converter containing an indicating function - Google Patents
An interface and E1 protocol converter containing an indicating function Download PDFInfo
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- CN203289481U CN203289481U CN2013203381684U CN201320338168U CN203289481U CN 203289481 U CN203289481 U CN 203289481U CN 2013203381684 U CN2013203381684 U CN 2013203381684U CN 201320338168 U CN201320338168 U CN 201320338168U CN 203289481 U CN203289481 U CN 203289481U
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- interface
- logic device
- programmable logic
- complex programmable
- protocol converter
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Abstract
The utility model discloses an interface and E1 protocol converter containing an indicating function. The interface and E1 protocol converter comprises a complex programmable logic device CPLD, a field-programmable gate array FPGA, a microprocessor, multiple interface chips, and indication lamps. The interface chips comprise multifunctional interface chips and an E1 line interface chip. Multiple multifunctional interface chips are provided and bidirectional conduction is achieved between the multiple multifunctional interface chips and the complex programmable logic device CPLD. Bidirectional conduction is achieved between the E1 line interface chip and the field-programmable gate array FPGA. Bidirectional conduction is achieved between the microprocessor and the complex programmable logic device CPLD. Unidirectional conduction is achieved between the microprocessor and the field-programmable gate array FPGA. The indicating lamps are connected with the complex programmable logic device CPLD. By the above structure, the interface and E1 protocol converter is capable of timely reflecting the operating cases of various data time slots in the complex programmable logic device CPLD in order to make corresponding adjustment to make the complex programmable logic device CPLD in the optimum operating state.
Description
Technical field
The utility model relates to the communications field, is specifically related to have interface and the E1 protocol converter of indicative function.
Background technology
Along with the sustainable development of computer technology and the communication technology, people constantly increase high bandwidth requirements, and the application of the high speed communication networks such as access DDN (Digital Data Network) net, frame relay network is also more and more general.E1 is the transmission standard that China's telecommunication transmission net primary group uses, and speed is 2.048 Mb/s.Realize the mutual conversion of multichannel interface and E1 agreement, can be connected to simultaneously E1 circuit at a high speed to plurality of devices.Protocol converter can make to be on communication network and adopt the main frame of different upper-layer protocols still to work in coordination, and completes various Distributed Application.Have more data slot in CPLD inside, the variation of any one data slot service condition all can affect the normal operation of CPLD, affects the operation of multi-protocol interface interface and E1 line interface.
The utility model content
The utility model has overcome the deficiencies in the prior art, interface and E1 protocol converter with indicative function are provided, be provided with special indicator light upper, ruuning situation in order to inner each data slot of timely reflection complex programmable logic device (CPLD),, to make corresponding adjustment, make it be in best operating state.
For solving above-mentioned technical problem, the utility model is by the following technical solutions: interface and E1 protocol converter with indicative function, comprise complex programmable logic device (CPLD), on-site programmable gate array FPGA, microprocessor, a plurality of interface chip and indicator light, described interface chip comprises versatile interface chip and E1 line interface chip, versatile interface chip wherein has a plurality of, all with the complex programmable logic device (CPLD) two-way admittance, E1 interface chip on-site programmable gate array FPGA two-way admittance; Described microprocessor and complex programmable logic device (CPLD) two-way admittance, microprocessor and on-site programmable gate array FPGA one-way conduction; Described indicator light is connected with complex programmable logic device (CPLD).
Further, described indicator light is LED light, and number is 30.
Further, described versatile interface chip model is LTC1546 or LTC1544, the versatile interface chip cross-distribution of two kinds of models.
Further, be connected with data storage RAM and the Data Buffer Memory Flash of two-way admittance on described microprocessor.
Further, described complex programmable logic device (CPLD) carries out unidirectional the connection with keyboard.
Further, described keyboard is four to take advantage of the quadruple linkage dish.
Compared with prior art, the beneficial effects of the utility model are:
1, the utility model is connected with a plurality of LED light on complex programmable logic device (CPLD), with the bright of indicator light with secretly indicate the service condition of 30 data time slots, in time find the service condition of data slot, then it is adjusted, thus the smooth and easy work of assurance multi-protocol interface interface and circuit chip.
2, adopt 4 * 4 keyboards, being used for receiving slot distributes that input is set is more convenient.
3, versatile interface chip LTC1546, LTC1544, both combinations, form Full Featured multi-protocol interface interface, support RS232, RS449, EIA530, EIA-530-A, V.35, V.36, agreement X.21, the selection of agreement can be undertaken by software fully.
Description of drawings
Fig. 1 is theory diagram of the present utility model.
Embodiment
Below in conjunction with accompanying drawing, the utility model is further elaborated, embodiment of the present utility model is not limited to this.
Embodiment:
As shown in Figure 1, the utility model comprises complex programmable logic device (CPLD), on-site programmable gate array FPGA, microprocessor, a plurality of interface chip and indicator light, indicator light is LED light, number is 30, is connected with data storage RAM and the Data Buffer Memory Flash of two-way admittance on microprocessor.Complex programmable logic device (CPLD) wherein carries out unidirectional the connection with keyboard, and keyboard is four to take advantage of the quadruple linkage dish.The interface chip of the present embodiment comprises versatile interface chip and E1 line interface chip, versatile interface chip wherein has a plurality of, all with the complex programmable logic device (CPLD) two-way admittance, E1 interface chip on-site programmable gate array FPGA two-way admittance, versatile interface chip model is LTC1546 or LTC1544, the versatile interface chip cross-distribution of two kinds of models.The microprocessor of the present embodiment and complex programmable logic device (CPLD) two-way admittance, microprocessor and on-site programmable gate array FPGA one-way conduction; Described indicator light is connected with complex programmable logic device (CPLD).
LED light is installed on complex programmable logic device (CPLD), totally 30, is used to refer to the service condition of 30 data time slots.When the LED lamp is lighted, represent that this time slot uses; , when the LED lamp does not work, represent that this time slot is for idle.Judgement is more convenient, guarantees the normal operation at multi-protocol interface interface.
Just can realize this utility model as mentioned above.
Claims (6)
1. the interface and the E1 protocol converter that have indicative function, it is characterized in that: comprise complex programmable logic device (CPLD), on-site programmable gate array FPGA, microprocessor, a plurality of interface chip and indicator light, described interface chip comprises versatile interface chip and E1 line interface chip, versatile interface chip wherein has a plurality of, all with the complex programmable logic device (CPLD) two-way admittance, E1 interface chip on-site programmable gate array FPGA two-way admittance; Described microprocessor and complex programmable logic device (CPLD) two-way admittance, microprocessor and on-site programmable gate array FPGA one-way conduction; Described indicator light is connected with complex programmable logic device (CPLD).
2. interface and the E1 protocol converter with indicative function according to claim 1, it is characterized in that: described indicator light is LED light, number is 30.
3. interface and the E1 protocol converter with indicative function according to claim 1, it is characterized in that: described versatile interface chip model is LTC1546 or LTC1544, the versatile interface chip cross-distribution of two kinds of models.
4. interface and the E1 protocol converter with indicative function according to claim 1, is characterized in that: the data storage RAM and the Data Buffer Memory Flash that are connected with two-way admittance on described microprocessor.
5. described interface and the E1 protocol converter with indicative function of according to claim 1-4 any one, it is characterized in that: described complex programmable logic device (CPLD) carries out unidirectional the connection with keyboard.
6. interface and the E1 protocol converter with indicative function according to claim 5 is characterized in that: described keyboard is four to take advantage of the quadruple linkage dish.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013203381684U CN203289481U (en) | 2013-06-14 | 2013-06-14 | An interface and E1 protocol converter containing an indicating function |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013203381684U CN203289481U (en) | 2013-06-14 | 2013-06-14 | An interface and E1 protocol converter containing an indicating function |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203289481U true CN203289481U (en) | 2013-11-13 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013203381684U Expired - Fee Related CN203289481U (en) | 2013-06-14 | 2013-06-14 | An interface and E1 protocol converter containing an indicating function |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203289481U (en) |
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2013
- 2013-06-14 CN CN2013203381684U patent/CN203289481U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131113 Termination date: 20140614 |
|
| EXPY | Termination of patent right or utility model |