CN103312712A - E1 protocol converter provided with multiple interfaces - Google Patents
E1 protocol converter provided with multiple interfaces Download PDFInfo
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- CN103312712A CN103312712A CN2013102335132A CN201310233513A CN103312712A CN 103312712 A CN103312712 A CN 103312712A CN 2013102335132 A CN2013102335132 A CN 2013102335132A CN 201310233513 A CN201310233513 A CN 201310233513A CN 103312712 A CN103312712 A CN 103312712A
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Abstract
The invention discloses an E1 protocol converter provided with multiple interfaces. The E1 protocol converter comprises a CPLD (complex programmable logic device), an FPGA (field programmable gate array), a microprocessor, multi-function interface chips and an E1-line interface chip. The CPLD, the FPGA and the E1-line interface chip are bilaterally conducted, the multi-function interface chips and the CPLD are bilaterally conducted, the microprocessor and the CPLD are bilaterally conducted, and the microprocessor and the FPGA are unilaterally conducted. By the arrangement of a multi-function multi-protocol interface, controlling is simpler.
Description
Technical field
The present invention relates to the communications field, be specifically related to be provided with the E1 protocol converter of multichannel interface.
Background technology
Along with the sustainable development of computer technology and the communication technology, people constantly increase high bandwidth requirements, and the application of the high speed communication networks such as access DDN (Digital Data Network) net, frame relay network is also more and more general.E1 is the transmission standard that China's telecommunication transmission net primary group uses, and speed is 2.048 Mb/s.Realize the mutual conversion of multichannel interface and E1 agreement, can be connected to simultaneously E1 circuit at a high speed to plurality of devices.Protocol converter can make to be in and adopt the main frame of different upper-layer protocols still to work in coordination on the communication network, finishes various Distributed Application.Also there is not the protocol converter based on FPGA (Field Programmable Gate Array) and microprocessor Design in the prior art.Interface chip on the existing protocol transducer is single, and can not form multi-functional protocol interface interface and support RS232, RS449, EIA530, EIA-530-A, V.35, V.36, X.21 agreement is controlled more complicated.
Summary of the invention
The present invention has overcome the deficiencies in the prior art, and the E1 that is provided with multichannel interface protocol converter is provided, and is provided with multi-functional multi-protocol interface interface, controls simpler.
For solving above-mentioned technical problem, the present invention is by the following technical solutions: the E1 protocol converter that is provided with the multichannel interface, comprise complex programmable logic device (CPLD), on-site programmable gate array FPGA, microprocessor, versatile interface chip and E1 line interface chip, described on-site programmable gate array FPGA and complex programmable logic device (CPLD) and the equal two-way admittance of E1 line interface chip, described versatile interface chip and complex programmable logic device (CPLD) two-way admittance, described microprocessor and complex programmable logic device (CPLD) two-way admittance, microprocessor and on-site programmable gate array FPGA one-way conduction.
Further, described versatile interface chip comprises versatile interface chip A and versatile interface chip B.
Further, the model of described versatile interface chip A is LTC1546.
Further, the model of described versatile interface chip B is LTC1544.
Further, described microprocessor while and data storage RAM and Data Buffer Memory Flash diconnected.
Further, the model of described E1 line interface chip is XRT82D20.
Compared with prior art, the invention has the beneficial effects as follows:
1, versatile interface chip A LTC1546 and versatile interface chip B LTC1544, the two combination consists of Full Featured multi-protocol interface interface, supports RS232, RS449, EIA530, EIA-530-A, V.35, V.36, X.21 agreement, the selection of agreement can be undertaken by software fully, uses more convenient.
2, complex programmable logic device (CPLD) is supported the multiple interfaces level, is used for finishing V.35, and RS 449, RS 232 data transmit-receives.
Description of drawings
Fig. 1 is theory diagram of the present invention.
Embodiment
The present invention is further elaborated below in conjunction with accompanying drawing, and embodiments of the invention are not limited to this.
Embodiment:
As shown in Figure 1, the present invention includes complex programmable logic device (CPLD), on-site programmable gate array FPGA, microprocessor, versatile interface chip and E1 line interface chip, the model of E1 line interface chip is XRT82D20.The on-site programmable gate array FPGA of the present embodiment and complex programmable logic device (CPLD) and E1 line interface chip equal two-way admittance, versatile interface chip and complex programmable logic device (CPLD) two-way admittance.The microprocessor of the present embodiment and complex programmable logic device (CPLD) two-way admittance, microprocessor and on-site programmable gate array FPGA one-way conduction, microprocessor while and data storage RAM and Data Buffer Memory Flash diconnected.The versatile interface chip of the present embodiment comprises versatile interface chip A and versatile interface chip B, and the model of versatile interface chip A is LTC1546, and the model of versatile interface chip B is LTC1544.The model of complex programmable logic device (CPLD) wherein is EPM7256 AETCl44-7, and the model of on-site programmable gate array FPGA is EP3C25F324C8, and the model of microprocessor is MPC875.
Versatile interface chip A LTC1546 and versatile interface chip B LTC1544 combination consist of Full Featured multi-protocol interface interface, support RS232, RS449, EIA530, EIA-530-A, V.35, V.36, X.21 agreement, the selection of agreement can be undertaken by software fully, and is easy to use.Because versatile interface chip A LTC1546 and versatile interface chip B LTC1544 interface level are 5 V, on-site programmable gate array FPGA is not supported such interface voltage, uses CPLD to make interface circuit here.
Just can realize this invention as mentioned above.
Claims (6)
1. be provided with the E1 protocol converter of multichannel interface, it is characterized in that: comprise complex programmable logic device (CPLD), on-site programmable gate array FPGA, microprocessor, versatile interface chip and E1 line interface chip, described on-site programmable gate array FPGA and complex programmable logic device (CPLD) and the equal two-way admittance of E1 line interface chip, described versatile interface chip and complex programmable logic device (CPLD) two-way admittance, described microprocessor and complex programmable logic device (CPLD) two-way admittance, microprocessor and on-site programmable gate array FPGA one-way conduction.
2. the E1 protocol converter that is provided with the multichannel interface according to claim 1, it is characterized in that: described versatile interface chip comprises versatile interface chip A and versatile interface chip B.
3. the E1 protocol converter that is provided with the multichannel interface according to claim 2, it is characterized in that: the model of described versatile interface chip A is LTC1546.
4. the E1 protocol converter that is provided with the multichannel interface according to claim 2, it is characterized in that: the model of described versatile interface chip B is LTC1544.
5. the E1 protocol converter that is provided with the multichannel interface according to claim 1 is characterized in that: described microprocessor while and data storage RAM and Data Buffer Memory Flash diconnected.
6. the E1 protocol converter that is provided with the multichannel interface according to claim 1, it is characterized in that: the model of described E1 line interface chip is XRT82D20.
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CN2013102335132A CN103312712A (en) | 2013-06-14 | 2013-06-14 | E1 protocol converter provided with multiple interfaces |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104753958A (en) * | 2015-04-17 | 2015-07-01 | 深圳市英威腾电气股份有限公司 | Card and method for converting communication protocols |
Citations (5)
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US6526340B1 (en) * | 1999-12-21 | 2003-02-25 | Spx Corporation | Multi-vehicle communication interface |
US7019558B1 (en) * | 2004-07-14 | 2006-03-28 | Xilinx, Inc. | Conversion of configuration data to match communication protocol |
CN202696645U (en) * | 2012-08-14 | 2013-01-23 | 成都思迈科技发展有限责任公司 | Modularized and channelized Ethernet gateway |
CN202696655U (en) * | 2012-08-13 | 2013-01-23 | 成都思迈科技发展有限责任公司 | Multi-interface to E1 protocol converter |
CN202696642U (en) * | 2012-08-13 | 2013-01-23 | 成都思迈科技发展有限责任公司 | Switching type remote bridge |
-
2013
- 2013-06-14 CN CN2013102335132A patent/CN103312712A/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6526340B1 (en) * | 1999-12-21 | 2003-02-25 | Spx Corporation | Multi-vehicle communication interface |
US7019558B1 (en) * | 2004-07-14 | 2006-03-28 | Xilinx, Inc. | Conversion of configuration data to match communication protocol |
CN202696655U (en) * | 2012-08-13 | 2013-01-23 | 成都思迈科技发展有限责任公司 | Multi-interface to E1 protocol converter |
CN202696642U (en) * | 2012-08-13 | 2013-01-23 | 成都思迈科技发展有限责任公司 | Switching type remote bridge |
CN202696645U (en) * | 2012-08-14 | 2013-01-23 | 成都思迈科技发展有限责任公司 | Modularized and channelized Ethernet gateway |
Non-Patent Citations (1)
Title |
---|
余发洪、刘皖、王占峰: "多路接口与E1协议转换器涉及与实现", 《现代电子技术》, vol. 34, no. 9, 1 May 2011 (2011-05-01), pages 79 - 72 * |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104753958A (en) * | 2015-04-17 | 2015-07-01 | 深圳市英威腾电气股份有限公司 | Card and method for converting communication protocols |
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Application publication date: 20130918 |