CN202696655U - Multi-interface to E1 protocol converter - Google Patents
Multi-interface to E1 protocol converter Download PDFInfo
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- CN202696655U CN202696655U CN 201220398723 CN201220398723U CN202696655U CN 202696655 U CN202696655 U CN 202696655U CN 201220398723 CN201220398723 CN 201220398723 CN 201220398723 U CN201220398723 U CN 201220398723U CN 202696655 U CN202696655 U CN 202696655U
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Abstract
The utility model discloses a multi-interface to E1 protocol converter. The protocol converter comprises at least one serial port module, a keyboard module, a protocol conversion module, an E1 interface module and a microprocessor, wherein the serial port module and the keyboard module are connected to the protocol conversion module via a voltage conversion module, both the E1 interface module and the microprocessor are connected to the protocol conversion module, and the microprocessor is connected with a memory. The multi-interface to E1 protocol converter has the advantage that multiple interfaces can be simultaneously connected to a high-speed E1 line.
Description
Technical field
The utility model relates to a kind of protocol converter, particularly relates to a kind of many interfaces to the E1 protocol converter.
Background technology
Protocol converter is called for short association and turns, and also is interface convertor, and protocol converter is gateway namely, and it can make to be in adopts the main frame of different upper-layer protocols still to work in coordination on the communication network, finish various Distributed Application.Existing protocol converter all is single interface conversion generally, when running into a plurality of interface, needs to use a plurality of devices, and the cost that expends is excessive.
The utility model content
The purpose of this utility model namely is to overcome the deficiency of present technology, provides a kind of many interfaces to the E1 protocol converter, multiple interfaces can be accessed simultaneously on the E1 circuit at a high speed.
The utility model is achieved through the following technical solutions: comprise at least one serial port module, Keysheet module, protocol conversion module, E1 interface module and microprocessor, described serial port module and Keysheet module are connected on the protocol conversion module by a voltage transformation module, described E1 interface module and microprocessor all are connected on the protocol conversion module, are connected with memory on the microprocessor.
Also be connected with a monitoring module on the described protocol conversion module.
Described monitoring module comprises processing module, communication check module and alarm module, and described processing module is connected on the protocol conversion module, and communication check module and alarm module are connected on the processing module.
Described memory comprises data storage RAM and Large Volume Data buffer storage FLASH.
Described protocol conversion module also is connected with a time slot allocation indicating module by voltage transformation module.
The beneficial effects of the utility model are: multiple interfaces can be accessed simultaneously on the E1 circuit at a high speed.
Description of drawings
Fig. 1 is structural representation of the present utility model.
Embodiment
The utility model is described in further detail below in conjunction with embodiment, but structure of the present utility model is not limited only to following examples:
[embodiment]
As shown in Figure 1, many interfaces are to the E1 protocol converter, comprise at least one serial port module, Keysheet module, protocol conversion module, E1 interface module and microprocessor, described serial port module and Keysheet module are connected on the protocol conversion module by a voltage transformation module, described E1 interface module and microprocessor all are connected on the protocol conversion module, be connected with memory on the microprocessor, memory comprises data storage RAM and Large Volume Data buffer storage FLASH.
Serial port module of the present utility model adopts versatile interface chip LTC1546 and LTC1544, and the two combination consists of Full Featured multi-protocol interface interface, supports RS232, RS449, and EIA530, EIA-530-A, V.35, and V.36, agreement X.21; It is the FPGA of EP3C25F324C8 that protocol conversion module adopts model, and cost performance is high, aboundresources; Microprocessor adopts Freescale MPC875 embedded type CPU, and based on the POWERPC framework, dominant frequency is up to 133 MHz, 8 KB command caches, and 8 KB data cache, bus frequency reaches as high as 80 MHz; It is the CPLD of EPM7256 AETCl44-7 that voltage transformation module adopts model, supports the multiple interfaces level, because LTC1546, the LTC1544 interface level is 5 V, and FPGA does not support such interface voltage, uses CPLD to make interface circuit here.The E1 interface module adopts the E1 line interface chip XRT82D20 of RXAR company, supports single channel E1, has the functions such as HDB3 coding, clock recovery, circuit driving, 75 Ω or 120 Ω impedance matchings.
Microprocessor carries out model selection by voltage transformation module to serial port module.As V.35, RS 449 is the simultaneous equation interface, and common interfaces speed is N * 64 Kb/s (N=1～32).Clock, data-signal are the transmission of two line balances, and control signal is uneven transmission, when sending data, corresponding with it clock are exported in the lump; When receive data, use the interface clock sampled data.And RS 232 is uneven transmission, and frame format is fixed as: 1 start bit, 8 bit data positions, stop bits, stop bits has three kinds: 1,1.5,2.The start bit is fixed as " 0 ", position of rest is fixed as " 1 ", communicating pair must be appointed the parameter (transmission speed, frame format) of serial transmission before beginning to communicate by letter, at transmitting terminal, at first produce the serial baud rate that needs by frequency division, then send with the speed of appointing according to frame format; At receiving terminal, use 8 times of clocks to baud rate to carry out to the received signal over-sampling, if through being low level signal after the filtering, namely think the start bit, then according to the rate receiving data of appointing.
Protocol conversion module of the present utility model also is connected with a time slot allocation indicating module by voltage transformation module, the time slot allocation indicating module is LED light, totally 30, is used to refer to the operating position of 30 data time slots, when the LED lamp is lighted, represent that this time slot uses; The LED lamp does not work, and represents that this time slot is for idle.
Keysheet module of the present utility model is one 4 * 4 keyboard, is used for receiving slot to distribute input is set.Protocol conversion module under the management control of clock system, is finished the volume solution frame function of E1 just according to the distribution setting of time slot, and microprocessor then writes corresponding data according to the time slot allocation register that arranges in the protocol conversion module.
Also be connected with a monitoring module on the protocol conversion module of the present utility model.Monitoring module comprises processing module, communication check module and alarm module, and described processing module is connected on the protocol conversion module, and communication check module and alarm module are connected on the processing module.Processing module adopts the LPC2210 flush bonding processor, communication conditions between the main monitoring serial port module of communication check module, protocol conversion module, the E1 interface module three, when situation appearred in device, the communication check module transmitted a signal to processing module, processing module control alarm equipment alarm.
Claims (5)
1. many interfaces are to the E1 protocol converter, it is characterized in that: comprise at least one serial port module, Keysheet module, protocol conversion module, E1 interface module and microprocessor, described serial port module and Keysheet module are connected on the protocol conversion module by a voltage transformation module, described E1 interface module and microprocessor all are connected on the protocol conversion module, are connected with memory on the microprocessor.
2. many interfaces according to claim 1 is characterized in that to the E1 protocol converter: also be connected with a monitoring module on the described protocol conversion module.
3. many interfaces according to claim 2 are to the E1 protocol converter, it is characterized in that: described monitoring module comprises processing module, communication check module and alarm module, described processing module is connected on the protocol conversion module, and communication check module and alarm module are connected on the processing module.
4. arbitrary described many interfaces is characterized in that to the E1 protocol converter according to claim 1～3: described memory comprises data storage RAM and Large Volume Data buffer storage FLASH.
5. many interfaces according to claim 4 is characterized in that to the E1 protocol converter: described protocol conversion module also is connected with a time slot allocation indicating module by voltage transformation module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220398723 CN202696655U (en) | 2012-08-13 | 2012-08-13 | Multi-interface to E1 protocol converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220398723 CN202696655U (en) | 2012-08-13 | 2012-08-13 | Multi-interface to E1 protocol converter |
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| Publication Number | Publication Date |
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| CN202696655U true CN202696655U (en) | 2013-01-23 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 201220398723 Expired - Fee Related CN202696655U (en) | 2012-08-13 | 2012-08-13 | Multi-interface to E1 protocol converter |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103297335A (en) * | 2013-06-14 | 2013-09-11 | 成都思迈科技发展有限责任公司 | Improved structure of gateway of ethernet network |
| CN103312711A (en) * | 2013-06-14 | 2013-09-18 | 成都思迈科技发展有限责任公司 | Modified structure of E1 protocol converter |
| CN103312712A (en) * | 2013-06-14 | 2013-09-18 | 成都思迈科技发展有限责任公司 | E1 protocol converter provided with multiple interfaces |
| CN103595689A (en) * | 2012-08-13 | 2014-02-19 | 成都思迈科技发展有限责任公司 | Multi-interface to E1 protocol converter |
| CN104243297A (en) * | 2014-10-16 | 2014-12-24 | 成都思迈科技发展有限责任公司 | Multi-service ethernet gateway system |
-
2012
- 2012-08-13 CN CN 201220398723 patent/CN202696655U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103595689A (en) * | 2012-08-13 | 2014-02-19 | 成都思迈科技发展有限责任公司 | Multi-interface to E1 protocol converter |
| CN103297335A (en) * | 2013-06-14 | 2013-09-11 | 成都思迈科技发展有限责任公司 | Improved structure of gateway of ethernet network |
| CN103312711A (en) * | 2013-06-14 | 2013-09-18 | 成都思迈科技发展有限责任公司 | Modified structure of E1 protocol converter |
| CN103312712A (en) * | 2013-06-14 | 2013-09-18 | 成都思迈科技发展有限责任公司 | E1 protocol converter provided with multiple interfaces |
| CN104243297A (en) * | 2014-10-16 | 2014-12-24 | 成都思迈科技发展有限责任公司 | Multi-service ethernet gateway system |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130123 Termination date: 20130813 |