CN203242630U - Insulated gate bipolar transistor - Google Patents
Insulated gate bipolar transistor Download PDFInfo
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- CN203242630U CN203242630U CN 201320222463 CN201320222463U CN203242630U CN 203242630 U CN203242630 U CN 203242630U CN 201320222463 CN201320222463 CN 201320222463 CN 201320222463 U CN201320222463 U CN 201320222463U CN 203242630 U CN203242630 U CN 203242630U
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- 239000000758 substrate Substances 0.000 claims abstract description 63
- 238000009792 diffusion process Methods 0.000 claims abstract description 46
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 130
- 229920005591 polysilicon Polymers 0.000 claims description 102
- 239000012212 insulator Substances 0.000 claims description 54
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 38
- 229910052751 metal Inorganic materials 0.000 claims description 33
- 239000002184 metal Substances 0.000 claims description 33
- 230000004888 barrier function Effects 0.000 claims description 31
- 235000012239 silicon dioxide Nutrition 0.000 claims description 19
- 239000000377 silicon dioxide Substances 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- 230000003647 oxidation Effects 0.000 claims description 12
- 238000007254 oxidation reaction Methods 0.000 claims description 12
- 238000001259 photo etching Methods 0.000 abstract description 24
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 41
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 33
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 32
- 239000012535 impurity Substances 0.000 description 30
- 239000011521 glass Substances 0.000 description 17
- 238000000137 annealing Methods 0.000 description 16
- 238000004519 manufacturing process Methods 0.000 description 13
- 238000001312 dry etching Methods 0.000 description 12
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 description 12
- 238000002513 implantation Methods 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- 229910004205 SiNX Inorganic materials 0.000 description 8
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical group CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- 229910019213 POCl3 Inorganic materials 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 6
- 230000008020 evaporation Effects 0.000 description 6
- 238000001704 evaporation Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910052681 coesite Inorganic materials 0.000 description 5
- 229910052906 cristobalite Inorganic materials 0.000 description 5
- 229910052682 stishovite Inorganic materials 0.000 description 5
- 229910052905 tridymite Inorganic materials 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000005465 channeling Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
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Abstract
The utility model relates to a semiconductor device of the power electronic technology field, and especially relates to an insulated gate bipolar transistor. The insulated gate bipolar transistor comprises a first conductive type substrate, and a second conductive type base region is arranged in a first main surface of the first conductive type substrate; a second conductive type deep diffusion region is arranged in the second conductive type base region, and a first conductive type emitter region with a transverse electronic access unit is arranged in the second conductive type base region. Under the design of reducing a device window, and due to the accuracy reason of a photoetching machine when electrode holes are etched, sometimes electrodes can not be contacted with an emitter at one side, so that a half of devices are lose efficacy. While a transverse second unit emitter region of the utility model can realize the situation that the electrodes can be contacted with the emitters at the two sides on any condition, so that the reliability of the device is increased.
Description
Technical field
The semiconductor device that relates to electric and electronic technical field of the present utility model is specially a kind of insulated gate bipolar transistor.
Background technology
Existing insulated gate bipolar transistor IGBT mainly (comprises the SiO2 floor by N-drift region, P tagma, dark P+ district, N+ emitter region, P+ collector region, SiO2 grid oxide layer, polysilicon gate floor, SiO2 oxide layer, PSG phosphorosilicate glass layer, SiO2 layer) and front metal layer, metal layer on back form.The front metal layer contacts P tagma and N+ emitter region simultaneously, consists of the emitter of device.Back metal contacts P+ collector region, the collector electrode of formation device.Polysilicon gate consists of device grids together with the metal that connects.
As shown in Figure 2, can divide for by the PIN diode district (width is L) of polysilicon gate definition and the PNP bipolar transistor area under control (width is W) that is defined by the polysilicon gate interval at the IGBT device.When the device forward conduction, electronics from the N+ emitter through the Channeling implantation that forms under the polysilicon gate to the N-drift region.The hole is injected into the N-drift region from the P+ collector electrode simultaneously.For the PIN diode district, because the electron hole that stores is more, because the conductivity modulation effect of semiconductor excess carrier, so that this regional resistance is lower.For PNP bipolar transistor area under control, because the electron hole that stores is less, this regional resistance is higher on the contrary.Electric current flow through simultaneously PNP and these two zones of PIN form conduction voltage drop Vce(sat).The ratio W:L that reduces high resistant PNP zone and low-resistance PIN peak width can reduce the Vce(sat of device).
At present traditional IGBT manufacturing process is as follows:
(1) in a side of N-drift region by the mode of the thermal oxidation gate oxide of growing, and on gate oxide by the LPCVD deposit spathic silicon, and use POCl3 that polysilicon is mixed.
(2) by photoetching, dry etching, form the polysilicon gate that separates has not had polysilicon to cover between the grid window, B Implanted in window is annealed, is pushed away trap and processes, and forms the P tagma.
(3) form emitter pattern in the both sides of window region by photoetching, and in emitter pattern, inject phosphorus; Remove photoresist, in window, inject phosphorus; Anneal, push away trap and process, form N+ emitter region and dark P+ district.
(4) deposit SiO2, rear regrowth one deck PSG or BPSG at window region with above the polysilicon gate by LPCVD or PECVD; By photoetching, dry etching, form contact motor hole between the N+ district, middle part that window goes and in the middle part of the P+ district.
(5) B Implanted overleaf, annealing push away trap and process and form the P+ collector electrode; Make metal electrode at front and back by evaporation or sputter again and form the IGBT device.
We can see by top IGBT manufacturing process, repeatedly photoetching and etching processing have been adopted in technological process, because there is the problem of alignment precision in mask aligner itself, so that the width W of the Window layer between the polysilicon gate can only be limited within the width that the precision of mask aligner can reach, such as the width W of further reduction of device Window layer, will bring many hidden danger to device.Particularly in step (3) to the photoetching of N+ emitter region, the very possible appearance because cover causes that partially figure shifts deviation, do not have and Metal Contact such as the N+ emitter of a side in the window, cause half inefficacy of device active region.Simultaneously, in step (4) to the photoetching meeting of electrode hole because the short circuit between emitter and the grid occurs in cover partially, cause device all to lose efficacy.So, the IGBT device that utilizes existing technology to produce, ubiquity is because the restriction of mask aligner alignment precision causes device architecture to owe rationally affect running parameter and the reliability of device because a kind of new designs of needs reduce to produce in to the dependence of mask aligner equipment.
Be CN201110165393.8 such as the patent No., patent name is the patent of invention of " igbt and manufacture method ", its technical scheme is: a kind of igbt, comprise: collector region, formed by the P type layer that is formed at the silicon substrate bottom, draw collector electrode from the back side of described silicon substrate; The drift region is comprised of the N+ layer and the N-layer that are formed at successively on the described collector region, and the N-type impurity concentration of a described N+ layer is greater than the N-type impurity concentration of a described N-layer; The P trap is formed in the described N-layer; The emitter region is comprised of the 2nd N+ layer that is formed at described P trap top, and described P trap separates described emitter region and described drift region; Grid, the described P trap in cover part, the described P trap that is covered by described grid is channel region, described channel region connects described drift region and the described emitter region of described P trap both sides; It is characterized in that: be formed with groove or hole in described P trap, be formed with the P+ articulamentum in the described P trap of the bottom in described groove or hole, described P+ articulamentum is positioned at the bottom of described emitter region; Be formed with the emitter terminal hole at described groove or top, hole, the width in described emitter terminal hole is filled with metal and draws emitter in described groove or hole and described emitter terminal hole greater than the width in described groove or hole.
In structure aspects, the polysilicon window opening of the bipolar transistor that above-mentioned patent is described is larger, and the distance of electrode hole and polysilicon only has 1.5 ~ 3.5um, and the electrode hole width minimum that generally altogether added the polysilicon window more than 2um can only arrive 5 ~ 9um like this; Prior art has adopted repeatedly photoetching and etching processing aspect production technology, because there is the problem of alignment precision in mask aligner itself, so that the width W of the Window layer between the polysilicon gate can only be limited within the width that the precision of mask aligner can reach, width W such as further reduction of device Window layer, will bring many hidden danger to device, and cause device architecture to owe rationally to affect running parameter and the reliability of device.
The utility model content
The problems referred to above that exist in order to overcome existing insulated gate bipolar transistor, existing special a kind of insulated gate bipolar transistor that proposes.
Concrete scheme of the present utility model is as follows:
A kind of insulated gate bipolar transistor, comprise the first conductivity type substrate, be provided with the second conduction type base in the first interarea of the first conductivity type substrate, be provided with the dark diffusion region of the second conduction type in the second conduction type base, be provided with in the second conduction type base with the first conduction type emitter region, transverse electric sub-channel unit, described the first conduction type emitter region comprises two first modules and two second units, two first modules laterally link to each other with a second unit separately, and the second unit of two horizontally sets forms transverse electric sub-channel unit;
The first module of the first conduction type emitter region is separately positioned on the two ends of the dark diffusion region of the second conduction type, the first interarea of each the first conduction type emitter region is provided with gate insulator, gate insulator is provided with the polysilicon gate layer, the polysilicon gate layer is provided with the second insulating barrier, the inboard of two groups of polysilicon gate layers and the second insulating barrier is provided with insulative sidewall, the insulative sidewall lower end is arranged on the gate insulator, be provided with the second conduction type collector region in the second interarea of the first conductivity type substrate, the zone between the described two polysilicon gate layers is window region.
Further, also include front metal and back metal, front metal contacts the second conduction type base and the first conduction type emitter region simultaneously, consist of the emitter of device, back metal contacts the second conduction type collector region, consist of the collector electrode of device, the polysilicon gate layer consists of device grids together with the metal that connects it.
Further, described each first module links to each other with two second units, and each second unit links to each other with two first modules;
The same side of two first modules of described the first conduction type emitter region forms zone, two emitter regions, and the distance at edge is D1 between two first modules of same emitter region; Each zone, emitter region part is covered by gate insulator and described polysilicon gate layer;
Two second units of described the first conduction type emitter region form zone, two emitter regions, lay respectively at the both sides of window region, be horizontally installed between two first modules, the distance at edge is D2 between two emitter regions of described two second units, described each zone, emitter region part is covered by gate insulator and described polysilicon, another part zone is not covered by gate insulator and described polysilicon gate layer, and D2 is less than D1.
Further, described D2 is 0 o'clock, two second units 142 of described the first conduction type emitter region emitter region separately is communicated with, whole window region is run through in zone, described emitter region, both sides, zone, described emitter region are covered by gate insulator and described polysilicon, and zone line is not covered by gate insulator and described polysilicon;
Further, described the first conduction type is N-type, the second conduction type is the P type, described the first conductivity type substrate is silicon substrate, the first conductivity type substrate the first interarea is positive, the second interarea is the back side, and the diffusion depth of described the first conduction type emitter region is 0.2-0.5um, and each emitter region width is between the 0.4-1um.
Further, described gate insulator is the silicon dioxide layer that thermal oxidation technology forms, and the width of described insulative sidewall is less than the width of the first conduction type emitter region, and the width of described insulative sidewall is 0.1-1um, highly is between the 0.7-2um.
Further, the width of window region is between 2-20um between the described polysilicon gate layer, and more excellent condition is that the width of window region is between 3-5um between the polysilicon gate layer.
A kind of manufacture method of insulated gate bipolar transistor, concrete manufacturing process is:
A. on the first interarea of the first conductivity type substrate, with the method growth gate insulator of thermal oxidation, LPCVD or PECVD;
B. on gate insulator with the method for LPCVD or PECVD, the deposit spathic silicon grid layer;
C. use POCl3 that the polysilicon gate layer is mixed;
D. on the polysilicon gate layer, deposit the second insulating barrier by LPCVD or PECVD;
E. by photoetching, dry etching the second insulating barrier and polysilicon gate layer are carried out etching, form window region and polysilicon gate floor district;
F. in window region, inject the second conductive type impurity, anneal, push away trap and process, form the second conduction type base;
G. form emitter pattern in the both sides of window region by photoetching, and in emitter pattern, inject the first conductive type impurity; Remove photoresist, in window, inject the second conductive type impurity, do annealing, push away the trap processing, form with transverse electric sub-channel the first conduction type emitter region and the dark diffusion region of the second conduction type.
H. on window region and polysilicon gate polar region, deposit the 3rd insulating medium layer by LPCVD or PECVD, pass through dry etching, etch into the first conductivity type substrate surface, the 3rd insulating barrier forms insulative sidewall by polysilicon gate layer place in window region, the space that forms between the described insulative sidewall of self aligned electrode hole by sidewall is electrode hole;
I. inject overleaf the second conductive type impurity, annealing pushes away trap and processes formation the second conduction type collector region, makes metal electrode at front and back by evaporation or sputter again and forms resulting devices.
Further, described the second conduction type base doping concentration is higher than the doping content of the first conductivity type substrate, the dark diffusion region of described the second conduction type doping content is greater than the doping content of the second conduction type base, and less than the concentration of the first conduction type emitter region; The degree of depth of the dark diffusion region of described the second conduction type is greater than the first conduction type emitter region; And the zone that diffusion is diffused into less than the second conduction type base below the polysilicon gate, the doping content of described the second conduction type collector region is greater than the second conduction type base, and less than the first conduction type emitter region, the first conduction type emitter region concentration is higher than the second conduction type base, and diffusion depth is less than the second conduction type base.
Further, described the second insulating barrier is TEOS silicon dioxide, phosphorosilicate glass PSG, boron-phosphorosilicate glass BPSG or silicon nitride SiNx by LPCVD or PECVD deposit, and their combination in any; Described insulative sidewall is TEOS silicon dioxide, phosphorosilicate glass PSG, boron-phosphorosilicate glass BPSG or silicon nitride SiNx by LPCVD or PECVD deposit, and their combination in any.
The utility model has the advantage of:
1, under the design that reduces device window, during the electrode hole etching owing to the precision reason of mask aligner, sometimes electrode can not contact with one side of emitter, cause half inefficacy of device, the setting of the second unit emitter region that the utility model is horizontal can be implemented in then in any case that electrode can both contact with the both sides emitter, has increased like this device reliability.
2, to adopt insulative sidewall be the self aligned technology of a kind of electrode hole for bipolar transistor of the present utility model, do not need photoetching, therefore the width of the window of polysilicon can be reduced to 4um; So can realize the figure that more becomes more meticulous.
3, bipolar transistor of the present utility model has structurally increased insulative sidewall, electrode hole is aimed at fully, processing step can be reduced, because the existence of insulative sidewall, can reduce the width of window, dwindling another effect that the width of window brings is the ratio that has increased the area of polysilicon gate and polycrystalline window, and the effect of bringing like this is the conduction voltage drop Vce(sat of IGBT) can reduce.Because the reducing of window region, but the N+ emitter region needs photoetching to have deviation of the alignment, thus introduced a unit, N+ emitter region that goes across window, so that device is unlikely to have half inefficacy.
4, reduce the photoetching of electrode hole in operation, increased the deposition step of insulative sidewall, increased the step that insulative sidewall is dwindled in corrosion.Having reduced photo-mask process can make the width W of the Window layer between the polysilicon gate dwindle under the prerequisite that guarantees device reliability as far as possible.Because the existence of insulative sidewall, electrode hole do not need photoetching, so can save the step that the electrode hole photoetching needs.
5, the D step is used for isolating polysilicon gate and emitter electrode for to deposit the second insulating barrier by LPCVD or PECVD on the polysilicon gate layer.
6, the H step has formed insulative sidewall, forms the electrode hole self-registered technology by insulative sidewall.
7, in the I step because the self-aligned mask effect of insulative sidewall, the width of the dark diffusion region of the second conduction type has reduced cut-in voltage Vth less than the width of existing device.
Description of drawings
Fig. 1 is the three-dimension integrally design drawing of this patent device.
Fig. 2 is the two-dimensional cross sectional design drawing of existing technique.
Fig. 3 is sectional view of the present utility model.
Fig. 4 is two second units 142 of the utility model the first conduction type emitter region structural representations separately the time.
Structural representation when Fig. 5 is two second units, 142 cross connection of the utility model the first conduction type emitter region.
The manufacture craft of Fig. 6 ~ 16 respective devices:
Fig. 6 is silicon substrate.
The corresponding technique A of Fig. 7, B, C, D.
The corresponding technique E of Fig. 8.
The corresponding technique F of Fig. 9.
The device with the first emitter unit that the corresponding technique G of Figure 10 forms.
The device with the second emitter unit that Figure 11,12 corresponding technique G form.
The corresponding technique H of Figure 13.
The dark diffusion region that Figure 14,15 corresponding technique G form.
The corresponding technique I of Figure 16.
110: the first conductivity type substrate in the accompanying drawing; 120: the second conduction type bases; 130: the second dark diffusion regions of conduction type; 140: the first conduction type emitter regions; 141: first module; 142: second unit 142; 150: the second conduction type collector regions; 160: gate insulator; 170: polysilicon gate; 180: the second insulating barriers; 190: insulative sidewall.
The width of polysilicon gate is L, and the window region width between the polysilicon gate is W; Two emitter regions of the first conduction type emitter region first module be spaced apart D1; Spacing distance between two second units, 142 formed two emitter regions is D2.
Embodiment
Embodiment 1
As shown in Figure 1, a kind of insulated gate bipolar transistor, comprise the first conductivity type substrate 110, be provided with the second conduction type base 120 in the first interarea of the first conductivity type substrate 110, be provided with the dark diffusion region 130 of the second conduction type in the second conduction type base 120, be provided with in the second conduction type base 120 with the first conduction type emitter region 140, transverse electric sub-channel unit, described the first conduction type emitter region 140 comprises two first modules 141 and two second units 142, two first modules 141 vertically arrange side by side, two second units 142 laterally link to each other with a second unit 142 separately, and the second unit 142 of two horizontally sets forms transverse electric sub-channel unit;
The first module 141 of the first conduction type emitter region 140 is separately positioned on the two ends of the dark diffusion region 130 of the second conduction type, the first interarea of each the first conduction type emitter region 140 is provided with gate insulator 160, gate insulator 160 is provided with polysilicon gate layer 170, polysilicon gate layer 170 is provided with the second insulating barrier 180, the inboard of two groups of polysilicon gate layers 170 and the second insulating barrier 180 is provided with insulative sidewall 190, insulative sidewall 190 lower ends are arranged on the gate insulator 160, be provided with the second conduction type collector region 150 in the second interarea of the first conductivity type substrate 110, the zone between the described two polysilicon gate layers 170 is window region.
As shown in Figure 1, a kind of insulated gate bipolar transistor, comprise the first conductivity type substrate 110, be provided with the second conduction type base 120 in the first interarea of the first conductivity type substrate 110, be provided with the dark diffusion region 130 of the second conduction type in the second conduction type base 120, be provided with in the second conduction type base 120 with the first conduction type emitter region 140, transverse electric sub-channel unit, described the first conduction type emitter region 140 comprises two first modules 141 and two second units 142, two first modules 141 vertically arrange side by side, two second units 142 laterally link to each other with a second unit 142 separately, and the second unit 142 of two horizontally sets forms transverse electric sub-channel unit; Also include front metal and back metal, front metal contacts the second conduction type base 120 and the first conduction type emitter region 140 simultaneously, consist of the emitter of device, back metal contacts the second conduction type collector region 150, consist of the collector electrode of device, polysilicon gate layer 170 consists of device grids together with the metal that connects it.
The first module 141 of the first conduction type emitter region 140 is separately positioned on the two ends of the dark diffusion region 130 of the second conduction type, the first interarea of each the first conduction type emitter region 140 is provided with gate insulator 160, gate insulator 160 is provided with polysilicon gate layer 170, polysilicon gate layer 170 is provided with the second insulating barrier 180, the inboard of two groups of polysilicon gate layers 170 and the second insulating barrier 180 is provided with insulative sidewall 190, insulative sidewall 190 lower ends are arranged on the gate insulator 160, be provided with the second conduction type collector region 150 in the second interarea of the first conductivity type substrate 110, the zone between the described two polysilicon gate layers 170 is window region.
Described each first module 141 links to each other with two second units 142, and each second unit 142 links to each other with two first modules 141; The same side of two first modules 141 of described the first conduction type emitter region 140 forms zone, two emitter regions, and the distance at 141 edges of two first modules of same emitter region is D1; Each zone, emitter region part is covered by gate insulator 160 and described polysilicon gate layer 170.Two second units 142 of the first conduction type emitter region 140 form zone, two emitter regions, lay respectively at the both sides of window region, be horizontally installed between two first modules 141, the distance at edge is D2 between two emitter regions of described two second units 142, described each zone, emitter region part is covered by gate insulator and described polysilicon, another part zone is not covered by gate insulator 160 and described polysilicon gate layer 170, and D2 is less than D1.
If reduce window region, so when photoetching is carried out in the N+ emitter region might so that two emitter regions one of them can not cause device that half inefficacy is arranged with electrode contact, so the utility model is with the first conduction type emitter region 140 shown in Figure 1, the structure that is the part of black among Fig. 1 is improved, its shape approximation is the H type, lateral part in the middle of it is exactly our transverse electric sub-channel unit, and namely second unit 142.
The first conduction type is N-type, the second conduction type is the P type, described the first conductivity type substrate 110 is silicon substrate, the first conductivity type substrate 110 first interareas are positive, the second interarea is the back side, the diffusion depth of described the first conduction type emitter region 140 is 0.5um, and each emitter region width is between the 1um.The silicon dioxide layer that described gate insulator 160 forms for thermal oxidation technology, the width of described insulative sidewall 190 is less than the width of the first conduction type emitter region 140, and the width of described insulative sidewall 190 is 1um, highly is between the 2um.The width of window region is between 20um between the described polysilicon gate layer.The width of window region is between 5um between the polysilicon gate layer.
Embodiment 3
As shown in Figure 1, a kind of insulated gate bipolar transistor, comprise the first conductivity type substrate 110, be provided with the second conduction type base 120 in the first interarea of the first conductivity type substrate 110, be provided with the dark diffusion region 130 of the second conduction type in the second conduction type base 120, be provided with in the second conduction type base 120 with the first conduction type emitter region 140, transverse electric sub-channel unit, described the first conduction type emitter region 140 comprises two first modules 141 and two second units 142, two first modules 141 vertically arrange side by side, two second units 142 laterally link to each other with a second unit 142 separately, and the second unit 142 of two horizontally sets forms transverse electric sub-channel unit; Also include front metal and back metal, front metal contacts the second conduction type base 120 and the first conduction type emitter region 140 simultaneously, consist of the emitter of device, back metal contacts the second conduction type collector region 150, consist of the collector electrode of device, polysilicon gate layer 170 consists of device grids together with the metal that connects it.
The first module 141 of the first conduction type emitter region 140 is separately positioned on the two ends of the dark diffusion region 130 of the second conduction type, the first interarea of each the first conduction type emitter region 140 is provided with gate insulator 160, gate insulator 160 is provided with polysilicon gate layer 170, polysilicon gate layer 170 is provided with the second insulating barrier 180, the inboard of two groups of polysilicon gate layers 170 and the second insulating barrier 180 is provided with insulative sidewall 190, insulative sidewall 190 lower ends are arranged on the gate insulator 160, be provided with the second conduction type collector region 150 in the second interarea of the first conductivity type substrate 110, the zone between the described two polysilicon gate layers 170 is window region.
Described each first module 141 links to each other with two second units 142, and each second unit 142 links to each other with two first modules 141; The same side of two first modules 141 of described the first conduction type emitter region 140 forms zone, two emitter regions, and the distance at 141 edges of two first modules of same emitter region is D1; Each zone, emitter region part is covered by gate insulator 160 and described polysilicon gate layer 170.Two second units 142 of the first conduction type emitter region 140 form zone, two emitter regions, lay respectively at the both sides of window region, be horizontally installed between two first modules 141, the distance at edge is D2 between two emitter regions of described two second units 142, described each zone, emitter region part is covered by gate insulator and described polysilicon, another part zone is not covered by gate insulator 160 and described polysilicon gate layer 170, and D2 is less than D1.Described D2 is 0 o'clock, two second units 142 of described the first conduction type emitter region 140 emitter region separately is communicated with, whole window region is run through in zone, described emitter region, both sides, zone, described emitter region are covered by gate insulator and described polysilicon, and zone line is not covered by gate insulator and described polysilicon.
At first the first module 141 of emitter region can be identical with traditional devices for the utility model, the distance of supposing the unit of two emitter regions is D1, the distance B 2 of the unit, two emitter regions of second unit 142 is less than 141 two emitter regions of first module cell distance D1, when two emission zone distance D2 of second unit 142 little to 0 time, two emitter regions of second unit 142 just are linked to be an emitter region, run through whole window region.
The first conduction type is N-type, the second conduction type is the P type, described the first conductivity type substrate 110 is silicon substrate, the first conductivity type substrate 110 first interareas are positive, the second interarea is the back side, the diffusion depth of described the first conduction type emitter region 140 is 0.2um, and each emitter region width is between the 0.4um.The silicon dioxide layer that described gate insulator 160 forms for thermal oxidation technology, the width of described insulative sidewall 190 is less than the width of the first conduction type emitter region 140, and the width of described insulative sidewall 190 is 0.1um, highly is between the 0.7um.The width of window region is between 2um between the described polysilicon gate layer.The width of window region is between 3um between the polysilicon gate layer.
Embodiment 4
A kind of manufacture method of insulated gate bipolar transistor, concrete manufacturing process is:
A. on the first interarea of the first conductivity type substrate 110, with the method growth gate insulator 160 of thermal oxidation, LPCVD or PECVD;
B. on gate insulator 160 with the method for LPCVD or PECVD, deposit spathic silicon grid layer 170;
C. use POCl3 that polysilicon gate layer 170 is mixed;
D. on polysilicon gate layer 170, deposit the second insulating barrier 180 by LPCVD or PECVD;
E. by photoetching, dry etching the second insulating barrier 180 and polysilicon gate layer 170 are carried out etching, form window region and polysilicon gate floor 170 district;
F. in window region, inject the second conductive type impurity, anneal, push away trap and process, form the second conduction type base 120;
G. form emitter pattern in the both sides of window region by photoetching, and in emitter pattern, inject the first conductive type impurity; Remove photoresist, in window, inject the second conductive type impurity, do annealing, push away the trap processing, form with transverse electric sub-channel the first conduction type emitter region 140 and the dark diffusion region 130 of the second conduction type.
H. on window region and polysilicon gate polar region, deposit the 3rd insulating medium layer by LPCVD or PECVD, pass through dry etching, etch into the first conductivity type substrate 110 surfaces, the 3rd insulating barrier forms insulative sidewall 190 by polysilicon gate layer 170 place in window region, the space that forms between the described insulative sidewall of self aligned electrode hole by sidewall is electrode hole;
I. inject overleaf the second conductive type impurity, annealing pushes away trap and processes formation the second conduction type collector region 150, makes metal electrode at front and back by evaporation or sputter again and forms resulting devices.
Embodiment 5
A kind of manufacture method of insulated gate bipolar transistor, concrete manufacturing process is:
A. on the first interarea of the first conductivity type substrate 110, with the method growth gate insulator 160 of thermal oxidation, LPCVD or PECVD;
B. on gate insulator 160 with the method for LPCVD or PECVD, deposit spathic silicon grid layer 170;
C. use POCl3 that polysilicon gate layer 170 is mixed;
D. on polysilicon gate layer 170, deposit the second insulating barrier 180 by LPCVD or PECVD;
E. by photoetching, dry etching the second insulating barrier 180 and polysilicon gate layer 170 are carried out etching, form window region and polysilicon gate floor 170 district;
F. in window region, inject the second conductive type impurity, anneal, push away trap and process, form the second conduction type base 120;
G. form emitter pattern in the both sides of window region by photoetching, and in emitter pattern, inject the first conductive type impurity; Remove photoresist, in window, inject the second conductive type impurity, do annealing, push away the trap processing, form with transverse electric sub-channel the first conduction type emitter region 140 and the dark diffusion region 130 of the second conduction type.
H. on window region and polysilicon gate polar region, deposit the 3rd insulating medium layer by LPCVD or PECVD, pass through dry etching, etch into the first conductivity type substrate 110 surfaces, the 3rd insulating barrier forms insulative sidewall 190 by polysilicon gate layer 170 place in window region, the space that forms between the described insulative sidewall of self aligned electrode hole by sidewall is electrode hole;
I. inject overleaf the second conductive type impurity, annealing pushes away trap and processes formation the second conduction type collector region 150, makes metal electrode at front and back by evaporation or sputter again and forms resulting devices.
Described the second conduction type base 120 doping contents are higher than the doping content of the first conductivity type substrate 110, the dark diffusion region of described the second conduction type 130 doping contents are greater than the doping content of the second conduction type base 120, and less than the concentration of the first conduction type emitter region 140; The degree of depth of the dark diffusion region 130 of described the second conduction type is greater than the first conduction type emitter region 140; And the zone that diffusion is diffused into less than the second conduction type base 120 below the polysilicon gate, the doping content of described the second conduction type collector region 150 is greater than the second conduction type base 120, and less than the first conduction type emitter region 140, the first conduction type emitter region 140 concentration are higher than the second conduction type base 120, and diffusion depth is less than the second conduction type base 120.
Described the second insulating barrier 180 is TEOS silicon dioxide, phosphorosilicate glass PSG, boron-phosphorosilicate glass BPSG or silicon nitride SiNx by LPCVD or PECVD deposit, and their combination in any; Described insulative sidewall 190 is TEOS silicon dioxide, phosphorosilicate glass PSG, boron-phosphorosilicate glass BPSG or silicon nitride SiNx by LPCVD or PECVD deposit, and their combination in any.
Embodiment 6
As shown in Figure 1, it is a kind of igbt device with the lateral-emitter unit, comprise the first conductivity type substrate 110, be provided with the second conduction type base 120 in the first interarea of the first conductivity type substrate 110, be provided with the dark diffusion region 130 of the second conduction type in the second conduction type base 120, the first conduction type emitter region 140, be arranged in the dark diffusion region 130 of the second conduction type, the first interarea of the first conductivity type substrate 110 is provided with gate insulator 160, gate insulator 160 is provided with polycrystalline silicon grid layer 170, polycrystalline silicon grid layer 170 is provided with the second insulating barrier 180, and polycrystalline silicon grid layer 170 both sides are provided with insulative sidewall 190, be provided with the second conduction type collector region 150 in the second interarea of the first conductivity type substrate.
Zone between the described polysilicon is window region.
Described the first conduction type emitter region first module 141 comprises two discrete emitter regions, and its doping content is higher than the second conduction type base 120; The part of each emitter region is covered by polycrystalline silicon grid layer 170, and another part is positioned at window region, and distance is D1 between two emitter regions.
Described the first conduction type emitter region second unit 142 comprises a continuous emitter region, and its doping content is higher than the second conduction type base 120; The part of each emitter region is covered by polycrystalline silicon grid layer 170, and another part is positioned at window region.
Described the first conduction type emitter region second unit 142,142 comprises two discrete emitter regions, and its doping content is higher than the second conduction type base 120; The part of each emitter region is covered by polycrystalline silicon grid layer 170, and another part is positioned at window region, and distance is D2 between two emitter regions, D2＜D1.
The first conduction type is N-type, and the second conduction type is the P type.The first conductivity type substrate is that silicon substrate 110, the first conductivity type substrate the first interarea is positive, and the second interarea is the back side.
The second conduction type base 120 doping contents are higher than the doping content of the first conductivity type substrate 110;
The dark diffusion region of the second conduction type 130 doping contents are greater than the doping content of the second conduction type base 110, and less than the concentration of the first conduction type emitter region 140; The degree of depth of the dark diffusion region 130 of the second conduction type is greater than the first conduction type emitter region 140; And the zone that diffusion is diffused into less than polysilicon gate 160 the second following conduction type bases 120;
The diffusion depth of the first conduction type emitter region 140 is 0.2 ~ 0.5um; Each emitter region width is between 0.2 ~ 1um, and left and right each one all is the same width.
The doping content of the second conduction type collector region 150 is greater than the second conduction type base 110.
Concrete, the first conductivity type substrate 110 doping contents are that 2e13 ~ 2e14 ㎝-3, the second conduction type base 120 doping contents 1e17 ~ dark diffusion region of 5e17 ㎝-3, the second conduction type 130 doping contents are 1e19 ~ 3e19 ㎝-3; The first conduction type emitter region 140 doping contents are 1.5e20 ~ 2.5e20 ㎝-3; The second conduction type collector electrode 150 doping contents are 1e17 ~ 1e19 ㎝-3.
The silicon dioxide layer that described gate insulator 160 forms for thermal oxidation technology, its thickness is 0.03 ~ 0.2um.
Described polycrystalline silicon grid layer 170 is the polysilicon layer of LPCVD or PECVD deposition, and the width of polysilicon layer is at 8 ~ 20um, and thickness is at 0.4 ~ 1um; Part between the polycrystalline silicon grid layer forms window region, and the width of window region is at 2 ~ 8um;
Described the second insulating barrier 180 is the TEOS silicon dioxide by LPCVD or PECVD deposit, phosphorosilicate glass (PSG), and boron-phosphorosilicate glass (BPSG) or silicon nitride (SiNx), and their combination in any, its thickness are 0.5 ~ 2um;
Described insulative sidewall 190 is the TEOS silicon dioxide by LPCVD or PECVD deposit, phosphorosilicate glass PSG, boron-phosphorosilicate glass BPSG, silicon nitride SiNx, the width of insulative sidewall 190 is less than the width of the first conduction type emitter region 140, the width of described insulative sidewall is between 0.1-1um, and height is between 0.7-2um.Insulative sidewall be shaped as shape among Fig. 1, also can be other shapes such as triangle.
A kind of manufacturing process of igbt device of fully self aligned is shown in Fig. 6-16:
A. on the first interarea of the first conductivity type substrate, with the method growth gate insulator of thermal oxidation, LPCVD or PECVD;
B. on gate insulator with the method for LPCVD or PECVD, deposit spathic silicon grid layer.
C. use POCl3 that polycrystalline silicon grid layer is mixed, perhaps when step B, just polysilicon is mixed.
D. on polycrystalline silicon grid layer, deposit the second insulating barrier by LPCVD or PECVD.
E. by photoetching, dry etching the second insulating barrier and polycrystalline silicon grid layer are carried out etching, form window region (width is W) and polycrystalline silicon grid layer district (width is L).
F. in window, inject the second conductive type impurity, anneal, push away trap and process the second conduction type base.The impurity that injects in the step F is boron, injects metering 1e13 ~ 2e14 cm-2, and ideal selection is 6e13 ~ 1.5e14cm-2, and Implantation Energy is 10 ~ 200KeV, and annealing temperature is 900 ℃ ~ 1300 ℃, and the time is 10 ~ 200min.
G. form emitter pattern in the both sides of window region by photoetching, and at emitter pattern, middle injection the first conductive type impurity; Remove photoresist, anneal, push away trap and process, form with transverse electric sub-channel the first conduction type emitter region (140) and the dark diffusion region of the second conduction type (130).The impurity that injects among the step G is phosphorus or arsenic, injects metering 2e15 ~ 2e16 cm-2, and ideal selection is 1e16 ~ 2e16cm-2, and Implantation Energy is 10 ~ 200KeV, and annealing temperature is 900 ℃ ~ 1100 ℃, and the time is 5 ~ 200min.
H. in window region and polycrystalline silicon grid layer district, deposit the 3rd insulating medium layer by LPCVD or PECVD, by dry etching, etch into the first conductivity type substrate surface, in window region, form insulative sidewall by the polycrystalline silicon grid layer place.
I. take insulative sidewall as mask, inject the second conductive type impurity, anneal, push away trap and form the dark diffusion region of the second conduction type.The impurity that injects among the step I is boron, injects metering 1e15 ~ 2e15 cm-2, and ideal selection is 3e15 ~ 1e16cm-2, and Implantation Energy is 10 ~ 200KeV, and annealing temperature is 900 ℃ ~ 1000 ℃, and the time is 10 ~ 200min.Form the structure of Figure 12 .1.
J. inject overleaf the second conductive type impurity, annealing pushes away trap and processes the formation collector electrode; Make metal electrode at front and back by evaporation or sputter again and form the IGBT device.The impurity that injects among the step L is boron, injects metering 1e13 ~ 1e16 cm-2, and ideal selection is 1e13 ~ 1e15cm-2, and Implantation Energy is 10 ~ 200KeV, and annealing temperature is 300 ℃ ~ 900 ℃, and the time is 100 ~ 1000min.
This patent only relates to the positive technique of igbt, for different back side technology: a cut-off type igbt, contrary type igbt and other back side technology led, same applicable.
Embodiment 7
As shown in Figure 1, it is a kind of igbt device with the lateral-emitter unit, comprise the first conductivity type substrate 110, be provided with the second conduction type base 120 in the first interarea of the first conductivity type substrate 110, be provided with the dark diffusion region 130 of the second conduction type in the second conduction type base 120, the first conduction type emitter region 140, be arranged in the dark diffusion region 130 of the second conduction type, the first interarea of the first conductivity type substrate 110 is provided with gate insulator 160, gate insulator 160 is provided with polycrystalline silicon grid layer 170, polycrystalline silicon grid layer 170 is provided with the second insulating barrier 180, and polycrystalline silicon grid layer 170 both sides are provided with insulative sidewall 190, be provided with the second conduction type collector region 150 in the second interarea of the first conductivity type substrate.
Zone between the described polysilicon is window region.
Described the first conduction type emitter region first module 141 comprises two discrete emitter regions, and its doping content is higher than the second conduction type base 120; The part of each emitter region is covered by polycrystalline silicon grid layer 170, and another part is positioned at window region, and distance is D1 between two emitter regions.
Described the first conduction type emitter region second unit 142142 comprises a continuous emitter region, and its doping content is higher than the second conduction type base 120; The part of each emitter region is covered by polycrystalline silicon grid layer 170, and another part is positioned at window region.
Described the first conduction type emitter region second unit 142142 comprises two discrete emitter regions, and its doping content is higher than the second conduction type base 120; The part of each emitter region is covered by polycrystalline silicon grid layer 170, and another part is positioned at window region, and distance is D2 between two emitter regions, D2＜D1.
The first conduction type is N-type, and the second conduction type is the P type.The first conductivity type substrate is that silicon substrate 110, the first conductivity type substrate the first interarea is positive, and the second interarea is the back side.
The second conduction type base 120 doping contents are higher than the doping content of the first conductivity type substrate 110;
The dark diffusion region of the second conduction type 130 doping contents are greater than the doping content of the second conduction type base 110, and less than the concentration of the first conduction type emitter region 140; The degree of depth of the dark diffusion region 130 of the second conduction type is greater than the first conduction type emitter region 140; And the zone that diffusion is diffused into less than polysilicon gate 160 the second following conduction type bases 120;
The diffusion depth of the first conduction type emitter region 140 is 0.2 ~ 0.5um; Each emitter region width is between 0.2 ~ 1um, and left and right each one all is the same width.
The doping content of the second conduction type collector region 150 is greater than the second conduction type base 110.
Concrete, the first conductivity type substrate 110 doping contents are that 2e13 ~ 2e14 ㎝-3, the second conduction type base 120 doping contents 1e17 ~ dark diffusion region of 5e17 ㎝-3, the second conduction type 130 doping contents are 1e19-3e19 ㎝-3; The first conduction type emitter region 140 doping contents are 1.5e20 ~ 2.5e20 ㎝-3; The second conduction type collector electrode 150 doping contents are 1e17 ~ 1e19 ㎝-3.
The silicon dioxide layer that described gate insulator 160 forms for thermal oxidation technology, its thickness is 0.03 ~ 0.2um.
Described polycrystalline silicon grid layer 170 is the polysilicon layer of LPCVD or PECVD deposition, and the width of polysilicon layer is at 8 ~ 20um, and thickness is at 0.4 ~ 1um; Part between the polycrystalline silicon grid layer forms window region, and the width of window region is at 2 ~ 8um;
Described the second insulating barrier 180 is the TEOS silicon dioxide by LPCVD or PECVD deposit, phosphorosilicate glass (PSG), and boron-phosphorosilicate glass (BPSG) or silicon nitride (SiNx), and their combination in any, its thickness are 0.5 ~ 2um;
Described insulative sidewall 190 is the TEOS silicon dioxide by LPCVD or PECVD deposit, phosphorosilicate glass PSG, boron-phosphorosilicate glass BPSG, silicon nitride SiNx, the width of insulative sidewall 190 is less than the width of the first conduction type emitter region 140, the width of described insulative sidewall is between 0.1-1um, and height is between 0.7-2um.Insulative sidewall be shaped as shape among Fig. 1, also can be other shapes such as triangle.
A kind of manufacturing process of igbt device of fully self aligned is shown in Fig. 6-16:
A. on the first interarea of the first conductivity type substrate, with the method growth gate insulator of thermal oxidation, LPCVD or PECVD;
B. on gate insulator with the method for LPCVD or PECVD, deposit spathic silicon grid layer.
C. use POCl3 that polycrystalline silicon grid layer is mixed, perhaps when step B, just polysilicon is mixed.
D. on polycrystalline silicon grid layer, deposit the second insulating barrier by LPCVD or PECVD.
E. by photoetching, dry etching the second insulating barrier and polycrystalline silicon grid layer are carried out etching, form window region (width is W) and polycrystalline silicon grid layer district (width is L).
F. in window, inject the second conductive type impurity, anneal, push away trap and process the second conduction type base.The impurity that injects in the step F is boron, injects metering 1e13 ~ 2e14 cm-2, and ideal selection is 6e13 ~ 1.5e14cm-2, and Implantation Energy is 10 ~ 200KeV, and annealing temperature is 900 ℃ ~ 1300 ℃, and the time is 10 ~ 200min.
G. form emitter pattern in the both sides of window region by photoetching, and at emitter pattern, middle injection the first conductive type impurity, the impurity that injects is phosphorus or arsenic, injects metering 2e15 ~ 2e16 cm-2, and ideal selection is 1e16 ~ 2e16cm-2, Implantation Energy is 10 ~ 200KeV; Remove photoresist, inject the second conductive type impurity, the impurity of injection is boron, injects metering 1e15 ~ 2e15 cm-2, and ideal selection is 3e15 ~ 1e16cm-2, and Implantation Energy is 10 ~ 200KeV.Formation is with transverse electric sub-channel the first conduction type emitter region (140,141,142) and the dark diffusion region of the second conduction type (130).Annealing temperature is 900 ℃ ~ 1100 ℃, and the time is 5 ~ 200min.
H. in window region and polycrystalline silicon grid layer district, deposit the 3rd insulating medium layer by LPCVD or PECVD, by dry etching, etch into the first conductivity type substrate surface, in window region, form insulative sidewall by the polycrystalline silicon grid layer place.Form the device architecture of Figure 12 .2.
I. inject overleaf the second conductive type impurity, annealing pushes away trap and processes the formation collector electrode; Make metal electrode at front and back by evaporation or sputter again and form the IGBT device.The impurity that injects among the step L is boron, injects metering 1e13 ~ 1e16 cm-2, and ideal selection is 1e13 ~ 1e15cm-2, and Implantation Energy is 10 ~ 200KeV, and annealing temperature is 300 ℃ ~ 900 ℃, and the time is 100 ~ 1000min.
This patent only relates to the positive technique of igbt, for different back side technology: a cut-off type igbt, contrary type igbt and other back side technology led, same applicable.
Claims (7)
1. insulated gate bipolar transistor, it is characterized in that: comprise the first conductivity type substrate (110), be provided with the second conduction type base (120) in the first interarea of the first conductivity type substrate (110), be provided with the dark diffusion region of the second conduction type (130) in the second conduction type base (120), be provided with in the second conduction type base (120) with the first conduction type emitter region (140), transverse electric sub-channel unit, described the first conduction type emitter region (140) comprises two first modules (141) and two second units (142), two first modules (141) laterally link to each other with a second unit (142) separately, and the second unit of two horizontally sets (142) forms transverse electric sub-channel unit;
The first module (141) of the first conduction type emitter region (140) is separately positioned on the two ends of the dark diffusion region of the second conduction type (130), the first interarea of each the first conduction type emitter region (140) is provided with gate insulator (160), gate insulator (160) is provided with polysilicon gate layer (170), polysilicon gate layer (170) is provided with the second insulating barrier (180), the inboard of two groups of polysilicon gate layers (170) and the second insulating barrier (180) is provided with insulative sidewall (190), insulative sidewall (190) lower end is arranged on the gate insulator (160), be provided with the second conduction type collector region (150) in the second interarea of the first conductivity type substrate (110), the zone between the described two polysilicon gate layers (170) is window region.
2. a kind of insulated gate bipolar transistor according to claim 1, it is characterized in that: also include front metal and back metal, front metal contacts the second conduction type base (120) and the first conduction type emitter region (140) simultaneously, consist of the emitter of device, back metal contacts the second conduction type collector region (150), consist of the collector electrode of device, polysilicon gate layer (170) consists of device grids together with the metal that connects it.
3. a kind of insulated gate bipolar transistor according to claim 1, it is characterized in that: described each first module (141) links to each other with two second units (142), and each second unit (142) links to each other with two first modules (141);
The same side of two first modules (141) of described the first conduction type emitter region (140) forms zone, two emitter regions, and the distance at edge is D1 between two first modules (141) of same emitter region; Each zone, emitter region part is covered by gate insulator (160) and described polysilicon gate layer (170);
Two second units (142) of described the first conduction type emitter region (140) form zone, two emitter regions, lay respectively at the both sides of window region, be horizontally installed between two first modules (141), the distance at edge is D2 between two emitter regions of described two second units (142), described each zone, emitter region part is covered by gate insulator and described polysilicon, another part zone is not covered by gate insulator (160) and described polysilicon gate layer (170), and D2 is less than D1.
4. a kind of insulated gate bipolar transistor according to claim 3, it is characterized in that: described D2 is 0 o'clock, two second unit 142(142 of described the first conduction type emitter region (140)) separately emitter region is communicated with, whole window region is run through in zone, described emitter region, both sides, zone, described emitter region are covered by gate insulator and described polysilicon, and zone line is not covered by gate insulator and described polysilicon.
5. according to claim 3 or 4 described a kind of insulated gate bipolar transistors, it is characterized in that: described the first conduction type is N-type, the second conduction type is the P type, described the first conductivity type substrate (110) is silicon substrate, the first conductivity type substrate (110) first interareas are positive, the second interarea is the back side, and the diffusion depth of described the first conduction type emitter region (140) is 0.2-0.5um, and each emitter region width is between the 0.4-1um.
6. a kind of insulated gate bipolar transistor according to claim 5, it is characterized in that: the silicon dioxide layer that described gate insulator (160) forms for thermal oxidation technology, the width of described insulative sidewall (190) is less than the width of the first conduction type emitter region (140), the width of described insulative sidewall (190) is 0.1-1um, highly is between the 0.7-2um.
7. a kind of insulated gate bipolar transistor according to claim 6, it is characterized in that: the width of window region is between 2-20um between the described polysilicon gate layer, and more excellent condition is that the width of window region is between 3-5um between the polysilicon gate layer.
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| CN103367413B (en) * | 2013-04-27 | 2015-09-16 | 中国东方电气集团有限公司 | A kind of insulated gate bipolar transistor and manufacture method thereof |
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