CN203481237U - Fully self-aligned insulated gate bipolar transistor device provided with field stop layer - Google Patents
Fully self-aligned insulated gate bipolar transistor device provided with field stop layer Download PDFInfo
- Publication number
- CN203481237U CN203481237U CN201320577696.5U CN201320577696U CN203481237U CN 203481237 U CN203481237 U CN 203481237U CN 201320577696 U CN201320577696 U CN 201320577696U CN 203481237 U CN203481237 U CN 203481237U
- Authority
- CN
- China
- Prior art keywords
- conduction type
- region
- width
- fully self
- conductive type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Abstract
The utility model relates to a semiconductor device of the power electronic technology field, in particular to a fully self-aligned insulated gate bipolar transistor device provided with a field stop layer. The fully self-aligned insulated gate bipolar transistor device comprises a first conductive type substrate, wherein a second conductive type base region is formed in a first primary plane of the first conductive type substrate, a second conductive type deep diffusion region is formed in the second conductive type base region and is in the shape of a Chinese character 'ao' meaning concave, and a first conductive type emitting region is arranged in the second conductive type base region. The bipolar transistor device adopts insulated side walls and a technology of full self alignment, the photolithography is not needed, the width of a polycrystalline silicon window can be reduced to 4 microns and even 2 microns, and thus more refined patterns can be achieved; the field stop layer is introduced, so that the thickness of the first conductive type substrate is reduced, and the conduction voltage drop Vce(sat) can be reduced therewith; and the introduction of the field stop layer can further reduce the energy loss of switching off the device.
Description
Technical field
The semiconductor device that relates to electric and electronic technical field of the present utility model, is specially a kind of igbt device of the fully self aligned with field cutoff layer.
Background technology
Existing insulated gate bipolar transistor IGBT mainly (comprises SiO2 floor by N-drift region, ,Shen P+ district, P tagma, N+ emitter region, P+ collector region, SiO2 grid oxide layer, polycrystalline silicon grid layer, SiO2 oxide layer, PSG phosphorosilicate glass layer, SiO2 layer) and front metal layer, metal layer on back form.Front metal layer contacts P tagma and N+ emitter region simultaneously, forms the emitter of device.Back metal contacts P+ collector region, the collector electrode of formation device.Polysilicon gate forms device grids together with the metal connecting.
As shown in Figure 2, at IGBT device, can divide for the PIN diode district (width is L) being defined by polysilicon gate and the PNP bipolar transistor area under control (width is W) being defined by polysilicon gate interval.When device forward conduction, the Channeling implantation that electronics forms from N+ emitter process polysilicon gate is to N-drift region.Hole is injected into N-drift region from P+ collector electrode simultaneously.For PIN diode district, because the electron hole storing is more, due to the conductivity modulation effect of semiconductor excess carrier, make the resistance in this region lower.For PNP bipolar transistor area under control, because the electron hole storing is less, the resistance in this region is higher on the contrary.Electric current flow through PNP and these two regions of PIN form conduction voltage drop Vce(sat simultaneously).The ratio W:L that reduces high resistant PNP region and low-resistance PIN peak width can reduce the Vce(sat of device).
In addition, decline Vce(sat) can also realize by reducing the thickness of silicon chip.Common way is between P+ collector region and N-drift region, to insert one deck N+ resilient coating, and reduces the thickness of N-drift region simultaneously.N+ resilient coating is wherein commonly called a cutoff layer, and its introducing can reduce the Vce(sat of device when break-over of device), when device turn-offs, reduce the turn-off power loss of device, thereby reduce the power consumption of device, increase the stability of device.
At present traditional IGBT manufacturing process is as follows:
(1) in a side of N-drift region by the mode of the thermal oxidation gate oxide of growing, and on gate oxide by LPCVD deposit spathic silicon, and polysilicon is adulterated.
(2) by photoetching, dry etching, the window that has formed separated polycrystalline silicon grid layer and do not had polysilicon to cover between grid, B Implanted in window, anneals, pushes away trap and process, and forms P tagma.
(3) in the both sides of window region, by photoetching, form emitter pattern, and inject phosphorus in emitter pattern; Remove photoresist, in window, inject phosphorus; Anneal, push away trap and process, form He Shen P+ district, N+ emitter region.
(4) in window region with above polycrystalline silicon grid layer, by LPCVD or PECVD, deposit SiO2, rear regrowth one deck PSG or BPSG; Between the N+ district, middle part going at window, middle part, HeP+ district, by photoetching, dry etching, forms contact motor hole.
(5) B Implanted overleaf, annealing pushes away trap and processes and form P+ collector electrode; At front and back, by evaporation or sputter, make metal electrode again and form IGBT device.
We can see IGBT manufacturing process by above, technological process has adopted repeatedly photoetching and etching processing, because mask aligner itself exists the problem of alignment precision, within the width that the precision that makes the width W of the Window layer between polysilicon gate can only be limited to mask aligner can reach, as the width W of further reduction of device Window layer, will bring much hidden danger to device.The particularly photoetching to N+ emitter region in step (3), very possible appearance, because cover causes that figure shifts deviation partially, as the N+ emitter of a side in window does not have and Metal Contact, causes half inefficacy of device active region.Meanwhile, the photoetching meeting of electrode hole be there is the short circuit between emitter and grid in step (4) because cover is inclined to one side, cause device all to lose efficacy.So, the IGBT device that utilizes existing technology to produce, ubiquity is because the restriction of mask aligner alignment precision causes device architecture to owe rationally to affect running parameter and the reliability of device, because need a kind of new device design to reduce the dependence to mask aligner equipment in production.In addition, in the step of traditional handicraft (3), N+ emitter is to form by photoetching and injection, and its width is larger, causes device that latch-up easily occurs.
If the patent No. is CN201110165393.8, patent name is the patent of invention of " igbt and manufacture method ", its technical scheme is: a kind of igbt, comprise: collector region, by the P type layer that is formed at silicon substrate bottom, formed, from the back side of described silicon substrate, draw collector electrode; Drift region, is comprised of the N+ layer and the N-layer that are formed at successively on described collector region, and the N-type impurity concentration of a described N+ layer is greater than the N-type impurity concentration of a described N-layer; P trap, is formed in a described N-layer; Emitter region, is comprised of the 2nd N+ layer that is formed at described P trap top, and described P trap separates described emitter region and described drift region; Grid, P trap described in cover part, the described P trap being covered by described grid is channel region, described channel region connects described drift region and the described emitter region of described P trap both sides; It is characterized in that: in described P trap, be formed with groove or hole, in the described P trap of the bottom in described groove or hole, be formed with P+ articulamentum, described P+ articulamentum is positioned at the bottom of described emitter region; At described groove or top, hole, be formed with emitter terminal hole, the width in described emitter terminal hole is greater than the width in described groove or hole, in described groove or hole and described emitter terminal hole, is filled with metal and draws emitter.
In structure aspects, the polysilicon window opening of the bipolar transistor that above-mentioned patent is described is larger, and the distance of electrode hole and polysilicon only has 1.5 ~ 3.5um, and the width minimum that electrode hole has generally altogether added polysilicon window more than 2um like this can only arrive 5 ~ 9um; Above-mentioned bipolar transistor structure is left-right asymmetry, has so just reduced the ability of the anti-breech lock of device.
Aspect production technology, prior art has adopted repeatedly photoetching and etching processing, because mask aligner itself exists the problem of alignment precision, within the width that the precision that makes the width W of the Window layer between polysilicon gate can only be limited to mask aligner can reach, as the width W of further reduction of device Window layer, will bring much hidden danger to device, and cause device architecture to owe rationally to affect running parameter and the reliability of device.
Utility model content
The problems referred to above that exist in order to overcome existing insulated gate bipolar transistor, the existing special igbt device that proposes a kind of fully self aligned with field cutoff layer.
Concrete scheme of the present utility model is as follows:
A kind of igbt device of the fully self aligned with field cutoff layer, it is characterized in that: comprise the first conductivity type substrate, in the first interarea of the first conductivity type substrate, be provided with the second conduction type base, in the second conduction type base, be provided with the second dark diffusion region of conduction type, described the second dark diffusion region of conduction type is " recessed " shape, in the second conduction type base, be provided with the first conduction type emitter region, the first conduction type emitter region is separately positioned on two bossings of the second dark diffusion region of conduction type " recessed " type, the first interarea of each the first conduction type emitter region is provided with gate insulator, gate insulator is provided with polycrystalline silicon grid layer, polycrystalline silicon grid layer is provided with the second insulating barrier, polycrystalline silicon grid layer both sides are provided with insulative sidewall, in the second interarea of the first conductivity type substrate, be provided with the first conduction type field cutoff layer, the first conduction type field cutoff layer is provided with the second conduction type collector region, the diffusion depth of the first described cut-off region, conduction type field is 3 ~ 25um, width is the width of whole the first conductivity type substrate, its concentration is higher than the concentration of the first conductivity type substrate and lower than the concentration of the second conduction type emitter region.
Region between described polysilicon is window region, and the central authorities of window region form groove by etch polysilicon.
Described the first conduction type emitter region comprises two discrete emitter regions, and its doping content is higher than the second conduction type base; A part for each emitter region is covered by polycrystalline silicon grid layer, and another part is positioned at window region, and the groove that two discrete emitter regions are positioned in the middle part of window region separates.
Described the first conductivity type substrate is silicon substrate, and first conductivity type substrate the first interarea is positive, and the second interarea is the back side.
The diffusion depth of described the first conduction type emitter region is 0.2-0.5um, and each emitter region width is between 0.4-1um.
The gash depth at described the first middle part, conductivity type substrate window region is greater than the diffusion depth of the first conduction type emitter region, is less than the diffusion depth of the second dark diffusion region of conduction type, and its width is less than or equal to the width between insulative sidewall.
Described gate insulator is the silicon dioxide layer that thermal oxidation technology forms.
The width of described insulative sidewall is less than the width of the first conduction type emitter region, and the width of described insulative sidewall is 0.1-1um, is highly between 0.7-2um.
Between described polysilicon, the width of window region is between 2-20um.
Between polysilicon, the width of window region is between 3-5um.
The utility model has the advantage of:
1, bipolar transistor employing insulative sidewall of the present utility model is a kind of technology of fully self aligned, does not need photoetching, therefore the width of the window of polysilicon can be reduced to 4um, even can arrive 2um; So just can realize the figure more becoming more meticulous.Introduce a cutoff layer, the thickness of the first conductivity type substrate reduced, conduction voltage drop Vce(sat) reduce thereupon; The energy loss when introducing of a cutoff layer simultaneously can further reduce device shutoff.
2, the deviation that there is no lithography alignment due to the technology of this patent, is self aligned technology, so the device architecture in patent is left and right full symmetric, first due to device, there is no the deviation of lithography alignment, and two N+ emitter width are the same; Secondly the area that reduces to reduce N+ emitter region of window width, also improves significantly to the latch-up of device like this.
3, bipolar transistor of the present utility model has structurally increased insulative sidewall, device architecture is aimed at completely, processing step can be reduced, because the existence of insulative sidewall, N+ emitter region and electrode hole do not need photoetching, so can save the step that electrode hole and the photoetching of N+ emitter region need, can reduce the width of window, dwindling another effect that the width of window brings is the ratio that has increased the area of polysilicon gate and polycrystalline window, and the effect of bringing is like this conduction voltage drop Vce(sat of IGBT) can reduce.
Accompanying drawing explanation
Fig. 1 is device whole structure figure.
Fig. 2 is the whole structure figure of traditional devices.
Fig. 3 is a cutoff layer dopant profile.
Fig. 4 is a cutoff layer dopant profile.
110: the first conductivity type substrate in accompanying drawing; 120: the second conduction type bases; 130: the second dark diffusion regions of conduction type; 140: the first conduction type emitter regions; 150: the second conduction type collector regions; 160: gate insulator; 170: polycrystalline silicon grid layer; 180: the second insulating barriers; 190: insulative sidewall; 200: a cutoff layer.
Embodiment
Embodiment 1
As shown in Figure 1, it is a kind of igbt device of the fully self aligned with field cutoff layer, comprise the first conductivity type substrate 110, in the first interarea of the first conductivity type substrate 110, be provided with the second conduction type base 120, in the second conduction type base 120, be provided with the second dark diffusion region 130 of conduction type, described the second dark diffusion region 130 of conduction type is " recessed " shape, in the second conduction type base 120, be provided with the first conduction type emitter region 140, the first conduction type emitter region 140 is separately positioned on two bossings of the second dark diffusion region 130 of conduction type " recessed " type, the first interarea of each the first conduction type emitter region 140 is provided with gate insulator 160, gate insulator 160 is provided with polycrystalline silicon grid layer 170, polycrystalline silicon grid layer 170 is provided with the second insulating barrier 180, polycrystalline silicon grid layer 170 both sides are provided with insulative sidewall 190, in the second interarea of the first conductivity type substrate 110, be provided with the first conduction type field cutoff layer 200, the first conduction type field cutoff layer 200 is provided with the second conduction type collector region 150.
Region between described polysilicon is window region, and the central authorities of window region form groove by etch polysilicon.
Described the first conduction type emitter region 140 comprises two discrete emitter regions, and its doping content is higher than the second conduction type base 120; A part for each emitter region is covered by polycrystalline silicon grid layer 170, and another part is positioned at window region, and the groove that two discrete emitter regions are positioned in the middle part of window region separates.
The first conduction type is N-type, and the second conduction type is P type.The first conductivity type substrate is that silicon substrate 110, the first conductivity type substrate the first interareas are positive, and the second interarea is the back side.
The second conduction type base 120 doping contents are higher than the doping content of the first conductivity type substrate 110;
The the second dark diffusion region of conduction type 130 doping contents are greater than the doping content of the second conduction type base 110, and are less than the concentration of the first conduction type emitter region 140; The degree of depth of the second dark diffusion region 130 of conduction type is greater than the first conduction type emitter region 140; And the region that diffusion is diffused into less than polysilicon gate 160 the second conduction type base 120 below;
The diffusion depth of the first conduction type emitter region 140 is 0.2 ~ 0.5um; Each emitter region width is between 0.2 ~ 1um, and left and right each is all the same width.
The diffusion depth of the first cut-off region, conduction type field 200 is 3 ~ 25um, and width is the width of whole the first conductivity type substrate 110, and its concentration is higher than the concentration of the first conductivity type substrate 110 and lower than the concentration of the second conduction type emitter region 150.
The doping content of the second conduction type collector region 150 is greater than the second cut-off region, conduction type field 200.
Concrete, the first conductivity type substrate 110 doping contents are 2e13 ~ 2e14 ㎝-3,120 doping content 1e17 ~ 5e17 ㎝-3, the second conduction type base, and the second dark diffusion region of conduction type 130 doping contents are 1e19-3e19 ㎝-3; The first conduction type emitter region 140 doping contents are 1.5e20 ~ 2.5e20 ㎝-3; The second conduction type collector electrode 150 doping contents are 1e17 ~ 1e19 ㎝-3; Cut-off region, field 200 doping contents are 5e14 ~ 1e17 ㎝-3, its doping content can be for being the initial gaussian shaped profile of peak value from the first conductivity type substrate 110 second interareas, also can, for the inner a certain degree of depth of the first conductivity type substrate is the initial gaussian shaped profile of peak value or non-gaussian shaped profile, can also be the stack of one deck or the above-mentioned Impurity Distribution of multilayer.
The silicon dioxide layer that described gate insulator 160 forms for thermal oxidation technology, its thickness is 0.03 ~ 0.2um.
Described polycrystalline silicon grid layer 170 is the polysilicon layer of LPCVD or PECVD deposition, and the width of polysilicon layer is at 8 ~ 20um, and thickness is at 0.4 ~ 1um; Part between polycrystalline silicon grid layer forms window region, and the width of window region is at 2 ~ 8um;
Described the second insulating barrier 180 is by the TEOS silicon dioxide of LPCVD or PECVD deposit, phosphorosilicate glass (PSG), and boron-phosphorosilicate glass (BPSG) or silicon nitride (SiNx), and their combination in any, its thickness is 0.5 ~ 2um;
Described insulative sidewall 190 is for passing through the TEOS silicon dioxide of LPCVD or PECVD deposit, phosphorosilicate glass PSG, boron-phosphorosilicate glass BPSG, silicon nitride SiNx, the width of insulative sidewall 190 is less than the width of the first conduction type emitter region 140, the width of described insulative sidewall is between 0.1-1um, and height is between 0.7-2um.Insulative sidewall be shaped as the shape in Fig. 1, can be also other shapes such as triangle.
The gash depth of the first middle part, conductivity type substrate window region is greater than the diffusion depth of the first conduction type emitter region 140, is less than the diffusion depth of the second dark diffusion region 130 of conduction type, is generally 0.2 ~ 0.6um; Its width is less than or equal to the width between insulative sidewall 190, is generally 1 ~ 7um.
A kind of manufacturing process of igbt device of the fully self aligned with field cutoff layer is as follows:
A. on the first interarea of the first conductivity type substrate, with the method growth gate insulator of thermal oxidation, LPCVD or PECVD;
B. on gate insulator by the method for LPCVD or PECVD, deposit spathic silicon grid layer.
C. use POCl3 to adulterate to polycrystalline silicon grid layer, or just polysilicon is adulterated when step B.
D. on polycrystalline silicon grid layer, by LPCVD or PECVD, deposit the second insulating barrier.
E. by photoetching, dry etching, the second insulating barrier and polycrystalline silicon grid layer are carried out to etching, form window region (width is W) and polycrystalline silicon grid layer district (width is L).
F. in window, inject the second conductive type impurity, anneal, push away trap and process, the second conduction type base.The impurity injecting in step F is boron, injects metering 1e13 ~ 2e14 cm
-2, the desirable 6e13 ~ 1.5e14cm that is chosen as
-2, Implantation Energy is 10 ~ 200KeV, and annealing temperature is 900 ℃ ~ 1300 ℃, and the time is 10 ~ 200min.
G. in window region, inject the first conductive type impurity, anneal, push away trap and process, form the emitter region of the first conduction type being connected.The impurity injecting in step G is phosphorus or arsenic, injects metering 2e15 ~ 2e16 cm
-2, the desirable 1e16 ~ 2e16cm that is chosen as
-2, Implantation Energy is 10 ~ 200KeV, and annealing temperature is 900 ℃ ~ 1100 ℃, and the time is 5 ~ 200min.
H. in window region and polycrystalline silicon grid layer district, by LPCVD or PECVD, deposit the 3rd insulating medium layer, by dry etching, etch into the first conductivity type substrate surface, in window region, by polycrystalline silicon grid layer place, form insulative sidewall.
I. take insulative sidewall as mask, inject the second conductive type impurity, anneal, push away trap and form the second dark diffusion region of conduction type.The impurity injecting in step I is boron, injects metering 1e15 ~ 2e15 cm
-2, the desirable 3e15 ~ 1e16cm that is chosen as
-2, Implantation Energy is 10 ~ 200KeV, and annealing temperature is 900 ℃ ~ 1000 ℃, and the time is 10 ~ 200min.
J. take insulative sidewall as mask, silicon substrate is carried out to etching, etching depth is greater than the degree of depth of the first conduction type emitter region, forms two separated emitter regions.In step J, the degree of depth of etching is 0.1 ~ 1um;
K. wet etching insulative sidewall, comes out emitter region part on the first interarea of the first conductivity type substrate.The degree of depth of corroding in step K is 0 ~ 0.3um.
L. inject overleaf the first conductive type impurity, annealing pushes away trap and processes a formation cutoff layer; The impurity injecting in step L can be phosphorus, arsenic, and sulphur, selenium, tellurium, hydrogen ions etc., inject metering for 1e13 ~ 1e15 cm
-2, desirable 2e13 ~ 5e14 cm that is chosen as
-2, Implantation Energy is 10KeV ~ 2MeV, and annealing temperature is 300 ℃ ~ 1200 ℃, and the time is 5min ~ 48hours.
M. inject overleaf the second conductive type impurity, annealing pushes away trap and processes formation collector electrode; At front and back, by evaporation or sputter, make metal electrode again and form IGBT device.The impurity injecting in step M is boron, injects metering 1e13 ~ 1e16 cm
-2, the desirable 1e13 ~ 1e15cm that is chosen as
-2, Implantation Energy is 10 ~ 200KeV, and annealing temperature is 300 ℃ ~ 900 ℃, and the time is 100 ~ 1000min.
Claims (7)
1. the igbt device with the fully self aligned of field cutoff layer, it is characterized in that: comprise the first conductivity type substrate (110), in the first interarea of the first conductivity type substrate (110), be provided with the second conduction type base (120), in the second conduction type base (120), be provided with the second dark diffusion region of conduction type (130), described the second dark diffusion region of conduction type (130) is " recessed " shape, in the second conduction type base (120), be provided with the first conduction type emitter region (140), the first conduction type emitter region (140) is separately positioned on two bossings of the second dark diffusion region of conduction type (130) " recessed " type, the first interarea of each the first conduction type emitter region (140) is provided with gate insulator (160), gate insulator (160) is provided with polycrystalline silicon grid layer (170), polycrystalline silicon grid layer (170) is provided with the second insulating barrier (180), polycrystalline silicon grid layer (170) both sides are provided with insulative sidewall (190), in the second interarea of the first conductivity type substrate (110), be provided with the first conduction type field cutoff layer (200), the first conduction type field cutoff layer (200) is provided with the second conduction type collector region (150), the diffusion depth of the first cut-off region, conduction type field (200) is 3 ~ 25um, width is the width of whole the first conductivity type substrate (110), its concentration is higher than the concentration of the first conductivity type substrate (110) and lower than the concentration of the second conduction type emitter region (150).
2. the igbt device of a kind of fully self aligned with field cutoff layer according to claim 1, is characterized in that: the region between described polysilicon is window region, and the central authorities of window region form groove by etch polysilicon.
3. the igbt device of a kind of fully self aligned with field cutoff layer according to claim 2, it is characterized in that: described the first conduction type emitter region (140) comprises two discrete emitter regions, and its doping content is higher than the second conduction type base (120); A part for each emitter region is covered by polycrystalline silicon grid layer (170), and another part is positioned at window region, and the groove that two discrete emitter regions are positioned in the middle part of window region separates.
4. the igbt device of a kind of fully self aligned with field cutoff layer according to claim 3, it is characterized in that: described the first conduction type is N-type, the second conduction type is P type, described the first conductivity type substrate (110) is silicon substrate, the first conductivity type substrate (110) first interareas are positive, the second interarea is the back side, the diffusion depth of described the first conduction type emitter region (140) is 0.2-0.5um, each emitter region width is between 0.4-1um, the igbt device of a kind of fully self aligned with field cutoff layer according to claim 1, it is characterized in that: the gash depth at middle part, described the first conductivity type substrate (110) window region is greater than the diffusion depth of the first conduction type emitter region (140), be less than the diffusion depth of the second dark diffusion region of conduction type (130), its width is less than or equal to the width between insulative sidewall (190).
5. the igbt device of a kind of fully self aligned with field cutoff layer according to claim 4, it is characterized in that: the silicon dioxide layer that described gate insulator (160) forms for thermal oxidation technology, the width of described insulative sidewall (190) is less than the width of the first conduction type emitter region (140), the width of described insulative sidewall (190) is 0.1-1um, is highly between 0.7-2um.
6. the igbt device of a kind of fully self aligned with field cutoff layer according to claim 5, is characterized in that: between described polysilicon, the width of window region is between 2-20um.
7. the igbt device of a kind of fully self aligned with field cutoff layer according to claim 5, is characterized in that: between polysilicon, the width of window region is between 3-5um.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320577696.5U CN203481237U (en) | 2013-09-18 | 2013-09-18 | Fully self-aligned insulated gate bipolar transistor device provided with field stop layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320577696.5U CN203481237U (en) | 2013-09-18 | 2013-09-18 | Fully self-aligned insulated gate bipolar transistor device provided with field stop layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203481237U true CN203481237U (en) | 2014-03-12 |
Family
ID=50229512
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320577696.5U Expired - Lifetime CN203481237U (en) | 2013-09-18 | 2013-09-18 | Fully self-aligned insulated gate bipolar transistor device provided with field stop layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203481237U (en) |
-
2013
- 2013-09-18 CN CN201320577696.5U patent/CN203481237U/en not_active Expired - Lifetime
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103219237B (en) | A kind of manufacture method of autoregistration insulated gate bipolar transistor | |
| CN100590850C (en) | Method for fabricating full-self-aligned stripe shaped grating power perpendicular double diffusion field effect transistor | |
| CN102034707B (en) | Method for manufacturing IGBT | |
| CN103035521B (en) | Realize the process of few groove-shaped IGBT of sub-accumulation layer | |
| CN105679667A (en) | Manufacturing method for terminal structure of trench IGBT device | |
| CN103050541A (en) | Radio frequency LDMOS (laterally diffused metal oxide semiconductor) device and manufacture method thereof | |
| CN101304006A (en) | Semiconductor component and method of manufacture | |
| CN103219238B (en) | The igbt device of a kind of fully self aligned and manufacture method thereof | |
| CN104716177A (en) | Radio frequency LOMOS device for overcoming electricity leakage and manufacturing method of radio frequency LOMOS device for overcoming electricity leakage | |
| CN103035730A (en) | Radio frequency laterally diffused metal oxide semiconductor (LDMOS) device and manufacturing method thereof | |
| CN102723353B (en) | High voltage power LDMOS device and manufacture method thereof | |
| CN103367413B (en) | A kind of insulated gate bipolar transistor and manufacture method thereof | |
| CN108336152A (en) | Groove-shaped silicon carbide SBD device with floating junction and its manufacturing method | |
| US4757027A (en) | Method for fabricating improved oxide defined transistors | |
| CA1290079C (en) | Vertical bipolar transistor | |
| CN203242631U (en) | Full-self-alignment insulated gate bipolar transistor (IGBT) device | |
| CN203481237U (en) | Fully self-aligned insulated gate bipolar transistor device provided with field stop layer | |
| CN108133892B (en) | Method for manufacturing bipolar transistor | |
| CN103165443B (en) | A kind of gated transistor device and method of manufacturing technology thereof | |
| CN203242630U (en) | Insulated gate bipolar transistor | |
| CN103390641B (en) | A kind of insulated gate bipolar transistor and autoregistration manufacture method thereof | |
| US4982257A (en) | Vertical bipolar transistor with collector and base extensions | |
| CN102881595B (en) | A kind of manufacture method of super-junction high-voltage power device | |
| JP2515055B2 (en) | Semiconductor device | |
| US9240457B2 (en) | IGBT transistor with protection against parasitic component activation and manufacturing process thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140312 |