CN103390641B - A kind of insulated gate bipolar transistor and autoregistration manufacture method thereof - Google Patents
A kind of insulated gate bipolar transistor and autoregistration manufacture method thereof Download PDFInfo
- Publication number
- CN103390641B CN103390641B CN201310151900.1A CN201310151900A CN103390641B CN 103390641 B CN103390641 B CN 103390641B CN 201310151900 A CN201310151900 A CN 201310151900A CN 103390641 B CN103390641 B CN 103390641B
- Authority
- CN
- China
- Prior art keywords
- diffusion region
- insulating barrier
- region
- bipolar transistor
- conducting layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 238000009792 diffusion process Methods 0.000 claims abstract description 96
- 238000005530 etching Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 230000004888 barrier function Effects 0.000 claims description 65
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 54
- 229920005591 polysilicon Polymers 0.000 claims description 40
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 38
- 229910052710 silicon Inorganic materials 0.000 claims description 38
- 239000010703 silicon Substances 0.000 claims description 38
- 239000013078 crystal Substances 0.000 claims description 31
- 238000005468 ion implantation Methods 0.000 claims description 22
- 239000002245 particle Substances 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 17
- 238000002513 implantation Methods 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 10
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 238000009828 non-uniform distribution Methods 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 230000003247 decreasing effect Effects 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000009826 distribution Methods 0.000 claims description 3
- 239000000796 flavoring agent Substances 0.000 claims description 3
- 235000019634 flavors Nutrition 0.000 claims description 3
- 208000037170 Delayed Emergence from Anesthesia Diseases 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 39
- 239000000377 silicon dioxide Substances 0.000 description 19
- 238000010586 diagram Methods 0.000 description 11
- 238000002347 injection Methods 0.000 description 9
- 239000007924 injection Substances 0.000 description 9
- 230000001413 cellular effect Effects 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 241000828883 Alope Species 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
The semiconductor device relating to electric and electronic technical field of the present invention, be specially a kind of insulated gate bipolar transistor and manufacture method thereof, comprise the first conductivity type substrate, the second conduction type base region is provided with in first interarea of the first conductivity type substrate, the second conductive-type moldeed depth diffusion region is provided with in second conduction type base region, be provided with transverse electric path unit first conduction type emitter region in second conduction type base region, under the design reducing device window, due to the precision reason of mask aligner during electrode hole etching, sometimes electrode can not with emitter while contact, device half is caused to lose efficacy, the setting of the second unit emitter region of transverse direction of the present invention then can realize under any circumstance electrode and can contact with both sides emitter, which increase the reliability of device.
Description
Technical field
The invention belongs to field of semiconductor devices, be specifically related to a kind of insulated gate bipolar transistor and autoregistration manufacture method thereof, more specifically relate to one and there is low JFET(JunctionField-EffectTransistor) the plane insulated gate bipolar transistor of resistance and autoregistration manufacture method thereof.
Background technology
IGBT(InsulatedGateBipolarTransistor, insulated gate bipolar transistor) since the eighties in 20th century comes out, developed into the 6th generation technique at present, Related product is widely used in the fields such as inverter, electric automobile, railway, household electrical appliances.For plane IGBT(as shown in Figure 1), for promoting its performance and the market competitiveness, must play on its advantage basis that preparation is relatively simple, advantage of lower cost is honest and clean, realizing the target of high withstand voltage, big current and low-power consumption.
The withstand voltage of IGBT depends on doping content, drift region thickness and carrier lifetime; Saturation current density is mainly limited to MOS saturation current, bipolar transistor gain and device primitive unit cell density etc.; Power consumption is then mainly limited to conducting resistance, switching time and operating frequency etc.Therefore, on the basis that withstand voltage degree and current density are protected, reduce conducting resistance by the adjustment of structural parameters and seem particularly important.
IGBT conducting resistance is primarily of the part composition such as emitter contact resistance, channel resistance, surface accumulation resistance, JFET resistance, tagma drift resistance, substrate contact resistance, wherein JFET resistance proportion is usually more than 50%, and the JFET resistance therefore how effectively reducing plane IGBT is one of key of manufacturing and designing of IGBT.
The MOS base of conventional I GBT adopts the mode of uniform ion injection, pushing away both sides, MOS base after trap through high temperature is column type PN junction, and the existence of this cylinder knot not only can increase electric current convergence effect, causes JFET resistance to increase, increase conduction voltage drop, the power consumption of device self is increased; Puncture voltage also can be caused to decline simultaneously.
Summary of the invention
Goal of the invention: for above-mentioned prior art Problems existing and deficiency, the object of this invention is to provide a kind of insulated gate bipolar transistor and autoregistration manufacture method thereof, the PN junction that both sides, this device MOS base and drift region are formed has the feature more level and smooth than traditional devices, be conducive to reducing JFET resistance, thus reduce device power consumption.
Technical scheme: for achieving the above object, the first technical scheme that the present invention adopts is a kind of insulated gate bipolar transistor, comprising: the crystal silicon base of the first conduction type; Described crystal silicon base is provided with the first insulating barrier; Described first insulating barrier is provided with polysilicon gate conducting layer, injects heavy particle in described polysilicon gate conducting layer; Described polysilicon gate conducting layer is provided with the second insulating barrier; At least etch polysilicon grid conducting layer and the second insulating barrier, forms the window with the first sloped sidewall 2011 and the second sloped sidewall 2012; Described crystal silicon base is at least provided with second diffusion region contrary with described crystal silicon base conduction type, three diffusion region identical with described crystal silicon base conduction type, four diffusion region contrary with described crystal silicon base conduction type and five diffusion region contrary with described crystal silicon base conduction type, described 5th diffusion region formed on described crystal silicon base lower surface and described 5th diffusion region as collector area, the lower surface of described 5th diffusion region is provided with collector electrode; At least on described first sloped sidewall 2011 and the second sloped sidewall 2012, form the 3rd insulating barrier; Described second diffusion region and described 3rd diffusion region, described 4th diffusion region have contact with each other, and wherein the 3rd diffusion region is as emitter region, and the 4th diffusion region is as source region; On described second insulating barrier, be respectively equipped with the first opening and the second opening in described window both sides, expose polysilicon gate conducting layer; Also comprise at least with the metal level of described polysilicon gate conducting layer, the 3rd diffusion region and the 4th diffusion region contacts, described metal level makes the 3rd diffusion region and the 4th diffusion region short circuit, forms emitter; Described polysilicon gate conducting layer and the metal level contacted with it form grid.
Preferably, described second diffusion region is positioned at the below of described crystal silicon base upper surface, described 3rd diffusion region is positioned at described second diffusion region, described 4th diffusion region is positioned at the below of the 3rd diffusion region, be provided with a groove at the middle part of described 3rd diffusion region, described metal level is by this groove and described 4th diffusion region contacts.
Preferably, described second diffusion region pushes away trap by a non-equilibrium diffusion source to obtain.Preferred, the CONCENTRATION DISTRIBUTION in described non-equilibrium diffusion source is: the even concentration in described window, and the concentration outside described window is successively decreased from the near to the remote according to the distance to window.
Preferably, six diffusion region identical with described crystal silicon base conduction type is also provided with between described 5th diffusion region and crystal silicon base.
Preferably, the thickness of described first insulating barrier is 500A-1500A; The thickness of described polysilicon gate conducting layer is 2000A-8000A; The thickness of described second insulating barrier and the 3rd insulating barrier is 2000A-20000A.
The second technical scheme that the present invention adopts is the manufacture method that a kind of autoregistration makes insulated gate bipolar transistor described above, comprises the steps:
(1) provide the crystalline silicon substrate of the first conduction type, described crystalline silicon substrate is as base;
(2) the first insulating barrier is made in the front of described crystalline silicon substrate;
(3) deposit spathic silicon grid conducting layer on described first insulating barrier, and heavy particle is injected in described polysilicon gate conducting layer;
(4) on described polysilicon gate conducting layer, the second insulating barrier is deposited;
(5) etching window figure: adopt photoresist mask at least to etch the second insulating barrier and polysilicon gate conducting layer, etch the second insulating barrier, polysilicon gate conducting layer and the first insulating barrier at the most, form the graph window with the first sloped sidewall 2011 and the second sloped sidewall 2012;
(6) with described graph window for mask carries out ion implantation, form the first doped region 1071 of non-uniform Distribution, described ionic conduction type is contrary with the first conduction type;
(7) high temperature pushes away trap, forms the second diffusion region;
(8) carry out ion implantation with described graph window for mask, form the second doped region 1091;
(9) upper surface deposition the 3rd insulating barrier of the device formed in described step (8);
(10) carry out first time bevel etched to described 3rd insulating barrier, the direction of described etching is consistent with the first sloped sidewall;
(11) carry out second time bevel etched to described 3rd insulating barrier, the direction of described etching is consistent with the second sloped sidewall, and the sidewall of described graph window forms side wall;
(12) with described graph window and side wall for mask carries out ion implantation, high temperature forms the 3rd diffusion region and the 4th diffusion region after pushing away trap, described 3rd diffusion region is identical with described crystal silicon base conduction type, and described 4th diffusion region is contrary with described crystal silicon base conduction type;
(13) with described graph window and side wall for mask, the device that described step (12) is formed is etched, the degree of depth of described etching is not less than the thickness of described 3rd diffusion region, and the degree of depth of described etching is not more than the thickness sum of described 3rd diffusion region and the 4th diffusion region;
(14) side wall described in erodable section, exposes part the 3rd diffusion region under described side wall;
(15) the second insulating barrier on described window both sides respectively polysilicon gate conducting layer described in etched portions, polysilicon gate conducting layer described in expose portion;
(16) the upper surface deposits conductive material of the device formed in described step (15), makes described 3rd diffusion region and the 4th diffusion region short circuit, forms emitter, and described polysilicon gate conducting layer and the electric conducting material contacted with it form grid;
(17) etch described electric conducting material, be separated described grid and described emitter;
(18) lower surface of the device formed in described step (17) carries out ion implantation, forms five diffusion region contrary with described crystal silicon base conduction type;
(19) in the lower surface deposits conductive material of described 5th diffusion region, collector electrode is formed.
Preferably, described graph window comprises open region and residual district, described open region and residual district mutually isolated; Described open region retains the first insulating barrier, residual block reservation first insulating barrier, polysilicon gate conducting layer and the second insulating barrier.Preferred, described graph window comprises surface, open region and the region between residual district sidewall and the second surface of insulating layer place plane, and the width of described graph window increases from the first insulating barrier place plane gradually to the second insulating barrier place plane.
Preferably, the thickness that etches of bevel etched is roughly the half of described 3rd thickness of insulating layer described first time.
Preferably, the 3rd insulating barrier not on described sidewall etches away by described second time bevel etched completely.
Preferably, in described step (18), before described 5th diffusion region of formation, the lower surface of the device formed in described step (17) carries out ion implantation, forms six diffusion region identical with described crystal silicon base conduction type.
Preferably, in described polysilicon gate conducting layer, carry out original flavor doping, diffusing, doping or ion implantation doping, make conduction sheet resistance be 1-50 Ω/.
Preferably, in described step (3), inject As ion in described polysilicon gate conducting layer, Implantation Energy is 80kev-200kev, and implantation dosage is 1e13/cm
3-2e14cm
3.
Preferably, described electric conducting material is conducting metal.Preferred, the thickness of described conducting metal is 500nm-5 μm.
Beneficial effect: the feature of New insulated grid bipolar transistor of the present invention is: (1) level and smooth MOS base, reduces electric field convergence effect, improve puncture voltage; (2) reduce junction field (JFET) resistance, thus reduce device power consumption.Present invention also offers a kind of Fully self-aligned process making this device.The feature of described technique is: (1) two step bevel etched makes window jamb; (2) grooving realizes emitter-self-alignment contact.Described technique can realize: (1) improves the ratio between grid width and window width, alleviates JFET resistance further; (2) reduce strict step of aiming at, thus reduce technology difficulty and production cost.
Accompanying drawing explanation
Fig. 1 is the schematic cross-section of conventional I GBT cellular;
Fig. 2 is the cross section signal schematic diagram of IGBT cellular of the present invention;
Fig. 3 is that alope sidewall prepares schematic diagram, and Fig. 4 is the window sidewall that tilts for mask carries out ion implantation schematic diagram;
Fig. 5 pushes away trap and N+ ion implantation schematic diagram for carrying out high temperature, and the region that in figure, dotted line frame surrounds is MOS base, and Fig. 6 is the MOS base region structure schematic diagram of conventional I GBT cellular;
Fig. 7 is first time bevel etched schematic diagram;
Fig. 8 is second time bevel etched schematic diagram;
Fig. 9 is P type source region ion implantation schematic diagram;
Figure 10 is vertical etch emitter region schematic diagram;
Figure 11 is wet etching window jamb schematic diagram;
Figure 12 is the complete structure schematic diagram of IGBT cellular of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, illustrate the present invention further, these embodiments should be understood only be not used in for illustration of the present invention and limit the scope of the invention, after having read the present invention, the amendment of those skilled in the art to the various equivalent form of value of the present invention has all fallen within the application's claims limited range.
As shown in Figure 1, conventional I GBT cellular comprises: collector area, the carrier drift district be located thereon, and is arranged in the MOS base of described drift region, is arranged in source region and the emitter region of MOS base, source region and emitter region short circuit; Be positioned at the grid oxic horizon on drift region; Be positioned at the polysilicon conducting layers on grid oxic horizon.
Grid is connected with polysilicon conducting layers; Emitter is connected with emitter region with source region; Collector electrode is connected with collector area.
Drift region, emitter region are the first conduction type, and collector area, source region, MOS base are the second conduction type; Conduction type has two kinds, and one is P type, and one is N-type.
As shown in Figure 2, IGBT cellular of the present invention comprises: collector area 102, the carrier drift district 103 be located thereon, and is arranged in the MOS base 107 of described drift region, be arranged in P+ source region 108 and the N+ emitter region 109 of MOS base, source region and emitter region are by metal electrode 110 shorted contacts; Be positioned at the grid oxic horizon 104 on drift region 103; Be positioned at the conductive polycrystalline silicon 105 on grid oxic horizon 104;
Conductive polycrystalline silicon 105 has the sidewall 201 of inclination; MOS base has level and smooth PN junction 202;
Metal electrode 106 and conductive polycrystalline silicon 105 are connected to form grid; Metal electrode 110, by emitter and source short, forms emitter; Metal electrode 101 and collector area 102 are connected to form collector electrode.
The autoregistration manufacture method of insulated gate bipolar transistor of the present invention is illustrated below in conjunction with Fig. 3 to Figure 12:
For N-type silicon chip substrate.As shown in Figure 3, on silicon chip, the method for thermal oxidation is first adopted to make the first insulating barrier silica 1041.Oxidation environment can be: dry oxygen or wet oxygen, and silicon oxide thickness is: 500A-1500A, and oxidizing temperature is: 800 DEG C-1000 DEG C.
Depositing electrically conductive polysilicon 105(and the polysilicon gate conducting layer described in claim on described silica 1041), method can adopt chemical vapour deposition (CVD) or sputtering, and thickness can adopt 2000A-8000A; For making it have good conductivity, can carry out original flavor doping, diffusing, doping or ion implantation doping, conduction sheet resistance is 1-50 Ω/.
In described conductive polycrystalline silicon, carry out heavy particle injection, described heavy particle can select As particle, Ar particle or other heavy particles, and form heavy particle injection region 401, Implantation Energy can select 80kev-200kev, and implantation dosage can select 1e13/cm
3-2e14cm
3.
On described conductive polycrystalline silicon 105, deposit the second insulating barrier silica 1042, can adopt the mode of chemical vapour deposition (CVD) or sputtering, thickness adopts 2000A-20000A.
In described silica 1042, carry out heavy particle injection, described heavy particle can select As particle, Ar particle or other heavy particles, and form heavy particle injection region 402, Implantation Energy can select 80kev-200kev, and implantation dosage can select 1e13/cm
3-2e14cm
3.It should be noted that, in described silica 1042, also can not carry out heavy particle injection, in etching so below, described silica 1042 also keeps rectangle, and the length in its cross section is identical with the upper base of described conductive polycrystalline silicon 105.
Photoresist mask 403 is adopted to etch, because heavy particle bombardment effect can change the Selection radio of horizontal direction and vertical direction, increase lateral etching speed, thus produce the window (or claiming " graph window ") with sloped sidewall 2011 and 2012 as shown in Figure 4.Etching depth is not less than the second insulating barrier silica 1042, conductive polycrystalline silicon 105 thickness sum, but is not more than the first insulating barrier silica 1041, conductive polycrystalline silicon 105, second insulating barrier silica 1042 thickness sum.
With described window for mask carries out P type ion implantation, form the first doped region described in non-uniform Distribution P type doped region 1071(and claim).Implantation Energy can select 60kev-100kev, and implantation dosage can select 1e13/cm
3-1e14/cm
3.
Shown in Fig. 3, device comprises: N-type drift region 1031; The the first insulating barrier silica 1041 be located thereon; Be positioned at the conductive polycrystalline silicon 105 on 1041 and As injection region 401; Be positioned at the second insulating barrier silica 1042 on conductive polycrystalline silicon 105 and As injection region 402; Be positioned at the photoresist mask 403 on As injection region 402.
Shown in Fig. 4, device comprises: N-type drift region 1031; The the first insulating barrier silica 1041 be located thereon; Be positioned at the conductive polycrystalline silicon 105 on the first insulating barrier silica 1041; Be positioned at the second insulating barrier silica 1042 on conductive polycrystalline silicon 105;
Window comprises base 203, sloped sidewall 2011 and 2012;
Under window, non-uniform Distribution P type doped region 1071 is formed after P type ion implantation;
The region be positioned under window base 203 is Uniform Doped, and the region be positioned under window sloped sidewall 2011 and 2012 is non-uniform doping, forms doping border 2021 and 2022.
As shown in Figure 5, first carry out high temperature P trap to advance, advance temperature can select 1000 DEG C-1200 DEG C, the propelling time can select 1hour-3hour, formation has level and smooth PN junction 2023 and 2024(is a PN junction, two labels represent the sidewall that this PN junction two is level and smooth respectively) P type MOS base (being the second diffusion region described in claim), compare with the PN junction shape 2025 and 2026 of traditional P type MOS base as shown in Figure 6, there is more level and smooth feature.
Then carry out N+ ion implantation, form the second doped region described in N+ doped region 1091(and claim).Implantation Energy can select 35kev-80kev; Implantation dosage can select 1e15/cm
3-1e17/cm
3.
As shown in Figure 7, deposition the 3rd insulating barrier silica 111, depositional mode can adopt chemical vapour deposition (CVD) or sputtering, and thickness can select 2000A-20000A.Carry out first time to tilt dry etching, etching direction and the first sloped sidewall described in window sloped sidewall 2011(and claim) consistent, etching depth is the half of the 3rd insulating barrier silica 111 thickness Hs.
As shown in Figure 8, carry out second time to tilt dry etching, etching direction and the second sloped sidewall described in window sloped sidewall 2012(and claim) consistent, etching depth is the half of the 3rd insulating barrier silica 111 thickness Hs, exposes N+ emitter region in the future (being N+ doped region 1091 now).
As shown in Figure 9, the thickness of the 3rd residual insulating barrier silica 1111 and 1112 is about Hs/2, and it is as the side wall of window.With side wall 1111 and 1112 for mask carries out P+ ion implantation.High temperature forms the 4th diffusion region described in P+ source region 108(and claim after pushing away trap) and N+ emitter region 109(and the 3rd diffusion region described in claim).Pushing away trap temperature is 900 DEG C-110 DEG C, and pushing away the trap time is 30mins-13mins.
As shown in Figure 10, with window and side wall for mask, carry out dry etching to silicon substrate, etching depth is not less than the thickness of N+ emitter region 109 but is not more than the thickness in P+ source region 108, forms groove 301 at the middle part of P+ source region 108 and N+ emitter region 109.
As shown in figure 11, carry out wet etching to window jamb, corrosion depth d is less than Hs/2, and after corrosion, N+ emitter region exposes local 2031,2032; The residual thickness of window jamb 1111 and 1112 is about Hs/2-d.
As shown in figure 12, in the second insulating barrier silica 1042 upper shed 3021 and 3022, expose conductive polycrystalline silicon 105; Front conductive metal deposition makes N+ emitter 109 and P+ source region 108 short circuit, forms emitter 110; Carve hole 3031 and 3032, to be separated conductive polycrystalline silicon and emitter region, form grid 1061,1062, emitter 110.The thickness of conducting metal can select 500nm-3um.
Carry out P+ ion implantation 1031 times in N-type drift region, formation P+ collector area 102(is the 5th diffusion region described in claim), Implantation Energy is 60kev-200kev, injects metering for 2e13/cm
3-2e16/cm
3; In P+ collector area, 102 times conductive metal deposition form collector electrode 101.
So far, whole device autoregistration completes.
It is to be noted, this embodiment designs for the NPT-IGBT (Non-PunchthroughIGBT) of N-type silicon substrate (N-shaped raceway groove), it is equally applicable to PT-IGBT (Punchthrough-IGBT): before described 5th diffusion region of formation, carry out N+ ion implantation 1031 times in N-type drift region, form six diffusion region (not shown) identical with described crystal silicon base conduction type.Be applicable to the IGBT of P-type silicon substrate (p-type raceway groove) simultaneously.
Claims (18)
1. an insulated gate bipolar transistor, comprising: the crystal silicon base of the first conduction type; Described crystal silicon base is provided with the first insulating barrier; Described first insulating barrier is provided with polysilicon gate conducting layer, injects heavy particle in described polysilicon gate conducting layer; Described polysilicon gate conducting layer is provided with the second insulating barrier; At least etch polysilicon grid conducting layer and the second insulating barrier, forms the window with the first sloped sidewall and the second sloped sidewall; Described crystal silicon base is at least provided with second diffusion region contrary with described crystal silicon base conduction type, three diffusion region identical with described crystal silicon base conduction type, four diffusion region contrary with described crystal silicon base conduction type and five diffusion region contrary with described crystal silicon base conduction type, described 5th diffusion region formed on described crystal silicon base lower surface and described 5th diffusion region as collector area, the lower surface of described 5th diffusion region is provided with collector electrode; At least on described first sloped sidewall and the second sloped sidewall, form the 3rd insulating barrier; Described second diffusion region and described 3rd diffusion region, described 4th diffusion region have contact with each other, and wherein the 3rd diffusion region is as emitter region, and the 4th diffusion region is as source region; On described second insulating barrier, be respectively equipped with the first opening and the second opening in described window both sides, expose polysilicon gate conducting layer; Also comprise at least with the metal level of described polysilicon gate conducting layer, the 3rd diffusion region and the 4th diffusion region contacts, described metal level makes the 3rd diffusion region and the 4th diffusion region short circuit, forms emitter; Described polysilicon gate conducting layer and the metal level contacted with it form grid;
Described second diffusion region pushes away trap by a non-equilibrium diffusion source to obtain; The CONCENTRATION DISTRIBUTION in described non-equilibrium diffusion source is: the even concentration in window, and the concentration outside described window is successively decreased from the near to the remote according to the distance to window.
2. a kind of insulated gate bipolar transistor according to claim 1, it is characterized in that: described second diffusion region is positioned at the below of described crystal silicon base upper surface, described 3rd diffusion region is positioned at described second diffusion region, described 4th diffusion region is positioned at the below of the 3rd diffusion region, be provided with a groove at the middle part of described 3rd diffusion region, described metal level is by this groove and described 4th diffusion region contacts.
3. a kind of insulated gate bipolar transistor according to claim 1, is characterized in that: described second diffusion region pushes away trap by a non-equilibrium diffusion source to obtain.
4. a kind of insulated gate bipolar transistor according to claim 3, is characterized in that: the CONCENTRATION DISTRIBUTION in described non-equilibrium diffusion source is: the even concentration in described window, and the concentration outside described window is successively decreased from the near to the remote according to the distance to window.
5. a kind of insulated gate bipolar transistor according to claim 1, is characterized in that: be also provided with six diffusion region identical with described crystal silicon base conduction type between described 5th diffusion region and crystal silicon base.
6. a kind of insulated gate bipolar transistor according to claim 1, is characterized in that: the thickness of described first insulating barrier is 500A-1500A.
7. a kind of insulated gate bipolar transistor according to claim 1, is characterized in that: the thickness of described polysilicon gate conducting layer is 2000A-8000A.
8. insulated gate bipolar transistor according to claim 1, is characterized in that: the thickness of described second insulating barrier and the 3rd insulating barrier is 2000A-20000A.
9. autoregistration makes a manufacture method for insulated gate bipolar transistor as claimed in claim 1, comprises the steps:
(1) provide the crystalline silicon substrate of the first conduction type, described crystalline silicon substrate is as base;
(2) the first insulating barrier is made in the front of described crystalline silicon substrate;
(3) deposit spathic silicon grid conducting layer on described first insulating barrier, and heavy particle is injected in described polysilicon gate conducting layer;
(4) on described polysilicon gate conducting layer, the second insulating barrier is deposited;
(5) etching window figure: adopt photoresist mask at least to etch the second insulating barrier and polysilicon gate conducting layer, etch the second insulating barrier, polysilicon gate conducting layer and the first insulating barrier at the most, form the graph window with the first sloped sidewall and the second sloped sidewall;
(6) with described graph window for mask carries out ion implantation, form first doped region (1071) of non-uniform Distribution, described ionic conduction type is contrary with the first conduction type;
(7) high temperature pushes away trap, forms the second diffusion region;
(8) carry out ion implantation with described graph window for mask, form the second doped region;
(9) upper surface deposition the 3rd insulating barrier of the device formed in described step (8);
(10) carry out first time bevel etched to described 3rd insulating barrier, the direction of described etching is consistent with the first sloped sidewall;
(11) carry out second time bevel etched to described 3rd insulating barrier, the direction of described etching is consistent with the second sloped sidewall, and the sidewall of described graph window forms side wall;
(12) with described graph window and side wall for mask carries out ion implantation, high temperature forms the 3rd diffusion region and the 4th diffusion region after pushing away trap, described 3rd diffusion region is identical with described crystal silicon base conduction type, and described 4th diffusion region is contrary with described crystal silicon base conduction type;
(13) with described graph window and side wall for mask, the device that described step (12) is formed is etched, the degree of depth of described etching is not less than the thickness of described 3rd diffusion region, and the degree of depth of described etching is not more than the thickness sum of described 3rd diffusion region and the 4th diffusion region;
(14) side wall described in erodable section, exposes part the 3rd diffusion region under described side wall;
(15) the second insulating barrier on described window both sides respectively polysilicon gate conducting layer described in etched portions, polysilicon gate conducting layer described in expose portion;
(16) the upper surface deposits conductive material of the device formed in described step (15), makes described 3rd diffusion region and the 4th diffusion region short circuit, forms emitter, and described polysilicon gate conducting layer and the electric conducting material contacted with it form grid;
(17) etch described electric conducting material, be separated described grid and described emitter;
(18) lower surface of the device formed in described step (17) carries out ion implantation, forms five diffusion region contrary with described crystal silicon base conduction type;
(19) in the lower surface deposits conductive material of described 5th diffusion region, collector electrode is formed.
10. a kind of autoregistration makes the manufacture method of insulated gate bipolar transistor as claimed in claim 1 according to claim 9, it is characterized in that: described graph window comprises open region and residual district, described open region and residual district mutually isolated; Described open region retains the first insulating barrier, residual block reservation first insulating barrier, polysilicon gate conducting layer and the second insulating barrier.
11. according to claim 10 a kind of autoregistration make the manufacture method of insulated gate bipolar transistor as claimed in claim 1, it is characterized in that: described graph window comprises surface, open region and the region between residual district sidewall and the second surface of insulating layer place plane, and the width of described graph window increases from the first insulating barrier place plane gradually to the second insulating barrier place plane.
12. according to claim 9 a kind of autoregistration make the manufacture method of insulated gate bipolar transistor as claimed in claim 1, it is characterized in that: described first time the thickness that etches of bevel etched be roughly the half of described 3rd thickness of insulating layer.
13. according to claim 9 a kind of autoregistration make the manufacture method of insulated gate bipolar transistor as claimed in claim 1, it is characterized in that: the 3rd insulating barrier not on described sidewall etches away by described second time bevel etched completely.
14. according to claim 9 a kind of autoregistration make the manufacture method of insulated gate bipolar transistor as claimed in claim 1, it is characterized in that: in described step (18), before described 5th diffusion region of formation, the lower surface of the device formed in described step (17) carries out ion implantation, forms six diffusion region identical with described crystal silicon base conduction type.
15. according to claim 9 a kind of autoregistration make the manufacture method of insulated gate bipolar transistor as claimed in claim 1, it is characterized in that: in described polysilicon gate conducting layer, carry out original flavor doping, diffusing, doping or ion implantation doping, make conduction sheet resistance be 1-50 Ω/.
16. according to claim 9 a kind of autoregistration make the manufacture method of insulated gate bipolar transistor as claimed in claim 1, it is characterized in that: in described step (3), heavy particle is injected in described polysilicon gate conducting layer, Implantation Energy is 80kev-200kev, and implantation dosage is 1e13/cm
3-2e14cm
3.
17. according to claim 9 a kind of autoregistration make the manufacture method of insulated gate bipolar transistor as claimed in claim 1, it is characterized in that: described electric conducting material is conducting metal.
18. make the manufacture method of insulated gate bipolar transistor as claimed in claim 1 according to autoregistration a kind of described in claim 17, it is characterized in that: the thickness of described conducting metal is 500nm-5um.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310151900.1A CN103390641B (en) | 2013-04-27 | 2013-04-27 | A kind of insulated gate bipolar transistor and autoregistration manufacture method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310151900.1A CN103390641B (en) | 2013-04-27 | 2013-04-27 | A kind of insulated gate bipolar transistor and autoregistration manufacture method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103390641A CN103390641A (en) | 2013-11-13 |
| CN103390641B true CN103390641B (en) | 2016-02-03 |
Family
ID=49534861
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310151900.1A Active CN103390641B (en) | 2013-04-27 | 2013-04-27 | A kind of insulated gate bipolar transistor and autoregistration manufacture method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103390641B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106784222A (en) * | 2017-01-05 | 2017-05-31 | 宗仁科技(平潭)有限公司 | A kind of modified power semiconductor devices and preparation method thereof |
| CN111370477B (en) * | 2018-12-25 | 2022-05-17 | 上海睿驱微电子科技有限公司 | Insulated gate bipolar transistor with overcurrent limiting function and construction method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5665988A (en) * | 1995-02-09 | 1997-09-09 | Fuji Electric Co., Ltd. | Conductivity-modulation semiconductor |
| CN1198003A (en) * | 1997-03-11 | 1998-11-04 | 哈里公司 | MOS-gated semiconductor devices |
| CN203521423U (en) * | 2013-04-27 | 2014-04-02 | 中国东方电气集团有限公司 | Insulated gate bipolar transistor |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8354733B2 (en) * | 2011-03-04 | 2013-01-15 | International Rectifier Corporation | IGBT power semiconductor package having a conductive clip |
-
2013
- 2013-04-27 CN CN201310151900.1A patent/CN103390641B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5665988A (en) * | 1995-02-09 | 1997-09-09 | Fuji Electric Co., Ltd. | Conductivity-modulation semiconductor |
| CN1198003A (en) * | 1997-03-11 | 1998-11-04 | 哈里公司 | MOS-gated semiconductor devices |
| CN203521423U (en) * | 2013-04-27 | 2014-04-02 | 中国东方电气集团有限公司 | Insulated gate bipolar transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103390641A (en) | 2013-11-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103219237B (en) | A kind of manufacture method of autoregistration insulated gate bipolar transistor | |
| CN103035521B (en) | Realize the process of few groove-shaped IGBT of sub-accumulation layer | |
| CN102569373B (en) | Insulated gate bipolar transistor (IGBT) with low-conductivity saturation voltage drop and manufacturing method for IGBT | |
| CN103094324B (en) | Trench-type insulated gate bipolar transistor and preparation method thereof | |
| CN103985746A (en) | Groove type IGBT (Insulated Gate Bipolar Transistor) device and manufacturing method thereof | |
| CN206976354U (en) | Suitable for the power semiconductor device structure of deep trench | |
| CN102842502B (en) | Insulated gate bipolar transistor and manufacturing method thereof | |
| CN103762230A (en) | N-channel injection efficiency reinforced insulated gate bipolar transistor | |
| CN103219238B (en) | The igbt device of a kind of fully self aligned and manufacture method thereof | |
| CN103390641B (en) | A kind of insulated gate bipolar transistor and autoregistration manufacture method thereof | |
| CN103681817A (en) | IGBT (insulated gate bipolar translator) device and manufacturing method thereof | |
| CN103855206A (en) | Insulated gate bipolar transistor and manufacturing method thereof | |
| CN103730506A (en) | Low-grid charge power device and manufacturing method thereof | |
| CN103367413B (en) | A kind of insulated gate bipolar transistor and manufacture method thereof | |
| CN203312299U (en) | Super barrier rectifying device | |
| CN203871337U (en) | Groove type IGBT device | |
| CN203521423U (en) | Insulated gate bipolar transistor | |
| CN102544083B (en) | MOS (metal oxide semiconductor) power device and manufacturing method thereof | |
| CN203013733U (en) | Igbt | |
| CN103779404B (en) | P Channeling implantation enhanced efficiency insulated gate bipolar transistor | |
| CN203242631U (en) | Full-self-alignment insulated gate bipolar transistor (IGBT) device | |
| CN104916686A (en) | VDMOS device and manufacturing method thereof | |
| CN203242630U (en) | Insulated gate bipolar transistor | |
| CN105336774A (en) | Vertical double-diffusion field effect transistor and manufacturing method thereof | |
| CN205621739U (en) | IGBT device with high locking -resisting ability |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |