CN102842608B - Insulated gate bipolar transistor and manufacturing method thereof - Google Patents
Insulated gate bipolar transistor and manufacturing method thereof Download PDFInfo
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- CN102842608B CN102842608B CN201110165393.8A CN201110165393A CN102842608B CN 102842608 B CN102842608 B CN 102842608B CN 201110165393 A CN201110165393 A CN 201110165393A CN 102842608 B CN102842608 B CN 102842608B
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Abstract
The invention discloses an insulated gate bipolar transistor, wherein a trench or a hole is formed in a P-well; a P+ connecting layer is formed at the bottom of the trench or the hole and is arranged at the bottom of an emitter region; an emitter lead hole is formed at the upper part of the trench or the hole; the width of the emitter lead hole is larger than the width of the trench or the hole; metal is filled into the trench or the hole and the emitter lead hole and the emitter is led out. The invention also discloses a manufacturing method of the insulated gate bipolar transistor. The manufacturing method comprises the following steps: after forming the gate and the P-well, carrying out photoetching and silicon etching on the P-well so as to form the trench or the hole; carrying out boron ion injection at the trench or the bottom of the hole so as to form an emitter region; and filling the metal into the trench or the hole so as to form a metal electrode. With the adoption of the insulated gate bipolar transistor, a parasitic resistance between the emitter and the P-well is reduced, and the self-locking effect is suppressed.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to a kind of igbt, the invention still further relates to a kind of manufacture method of igbt.
Background technology
Igbt (Insulated Gate Bipolar Transistor, IGBT) be the bipolar compound device of a kind of voltage-controlled MOS/, this device has the major advantage of dipole power transistor and power MOSFET simultaneously: input impedance is high, input queued switches power is little, conducting resistance is little, current capacity is large, switching speed is fast.IGBT structure and VDMOS structure closely similar, as shown in Figure 2, be the structural representation of the first IGBT existing, comprise: collector region, be made up of the P-type layer 13 be formed at bottom silicon substrate, draw collector electrode from the back side of described silicon substrate; Drift region, is made up of the N+ layer 12 be formed at successively on described collector region and a N-layer 11, and the N-type impurity concentration of a described N+ layer 12 is greater than the N-type impurity concentration of a described N-layer 11; P trap 16, is formed in a described N-layer 11; Emitter region, be made up of the 2nd N+ layer 14 being formed at described P trap 16 top, described emitter region and described drift region separate by described P trap 16; Grid 21, P trap 16 described in cover part, the described P trap 16 covered by described grid 21 is channel region, and described channel region connects the described drift region of described P trap 16 both sides and described emitter region; P+ articulamentum 15a, is formed through described 2nd N+ layer 14 and with described P trap 16 and contacts; Emitter 24a, is formed with described 2nd N+ layer 14 and contacts and draw described P trap 16 by described P+ articulamentum 15a; Its midfield oxygen 22 is for the isolation between device, and dielectric layer 23 is for the isolation between metal level and device.It is the N+ substrate of existing VDMOS has been changed into N-substrate and a described N-layer 11 that above-mentioned the first IGBT existing and the structure of existing VDMOS do not exist together, and increases one deck P layer and described P-type layer 13.But the character that this architecture advances is IGBT there occurs the change of essence compared to VDMOS, define a kind of bipolar transistor structure controlled with mos gate.When break-over of device, injecting a large amount of minority carriers due to described P-type layer 13 to a described N-layer 11 makes a described N-layer 11 produce strong conductivity modulation effect, thus its resistivity reduces greatly, thus the conducting resistance of device is diminished by the described resistivity of a N-layer 11 and the restriction of thickness.By suitably choosing resistivity and the thickness of a described N-layer 11, the withstand voltage of device can be made to be improved, obviously can not increase conducting resistance simultaneously.Therefore, IGBT overcome VDMOS inherently and also be the contradiction between conducting resistance and puncture voltage that cannot overcome.But, IGBT is while overcoming VDMOS shortcoming, bring again self intrinsic fault of construction, that is exactly that the PNPN structure of IGBT under certain operating conditions breech lock occurs, IGBT is caused to lose grid-control ability, device cannot turn off voluntarily, and the big current even formed due to positive feedback makes that IGBT is permanent to be burnt, and this phenomenon is called as the latching effect of IGBT.
IGBT latching effect is device layout, need strictly to avoid in manufacture and application process, and the resistance reduced between emitter 24a and P trap 16 can suppress IGBT latching effect.Be illustrated in figure 4 the equivalent circuit diagram of the first IGBT existing, a PNP pipe is defined and a NPN manages by PNPN structure structure, wherein said PNP pipe is made up of described P-type layer 13, a described N+ layer 12, a described N-layer 11 and described P trap 16, and described P-type layer 13 draws collector electrode; Described NPN pipe is phost line, and be made up of a described N+ layer 12, a described N-layer 11, described P trap 16 and described 2nd N+ layer 14, described 2nd N+ layer 14 draws emitter; Contact resistance between described P trap 16 and described emitter is Rs; The source region of NMOS tube is a described N+ layer 12 and a described N-layer 11, the drain region of NMOS is described 2nd N+ layer 14, and grid 21 controls the formation of the raceway groove of NMOS tube.There is breech lock in the PNPN structure of IGBT, cause IGBT to lose grid-control ability, device cannot turn off voluntarily under certain operating conditions, and the big current even formed due to positive feedback makes that IGBT is permanent to be burnt, and this phenomenon is called as the latching effect of IGBT.IGBT latching effect is device layout, need strictly to avoid in manufacture and application process, the dead resistance Rs reduced between described emitter 21a and described P trap 16 can reduce voltage drop on the base stage of described NPN and emitter, be reduced by the electronics that NPN is injected into N-region and a described N+ layer 12 and described N-layer 11 region, be conducive to described PNP pipe to turn off when NMOS turns off, be conducive to suppressing IGBT latching effect.
The first IGBT existing as shown in Figure 2 realizes described emitter 24a by described P+ articulamentum 15a to contact with described P trap 16 formation, and the dead resistance Rs of the formation of this structure is general larger.
The structural representation of existing the second IGBT as shown in Figure 3, existing the second IGBT is formed at the fairlead of emitter 24b and increases silicon etching process simultaneously, inject bottom described fairlead and form P+ articulamentum 15b, generally can bottom described fairlead the P+ articulamentum 15b of Formation Depth about 1 μm.Existing the second IGBT is owing to being subject to the restriction of the width of described fairlead, and the described P+ articulamentum 15b degree of depth finally formed can not be very dark, makes dead resistance Rs still larger.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of igbt, can reduce the dead resistance between emitter and P trap, suppress to hold up post effect; For this reason, the present invention also provides a kind of manufacture method of igbt.
For solving the problems of the technologies described above, igbt provided by the invention comprises: collector region, is made up of the P-type layer be formed at bottom silicon substrate, draws collector electrode from the back side of described silicon substrate.Drift region, is made up of the N+ layer be formed at successively on described collector region and a N-layer, and the N-type impurity concentration of a described N+ layer is greater than the N-type impurity concentration of a described N-layer.P trap, is formed in a described N-layer.Emitter region, be made up of the 2nd N+ layer being formed at described P trap top, described emitter region and described drift region separate by described P trap.Grid, P trap described in cover part, the described P trap covered by described grid is channel region, and described channel region connects the described drift region of described P trap both sides and described emitter region.In described P trap, be formed with groove or hole, in the described P trap of the bottom in described groove or hole, be formed with P+ articulamentum, described P+ articulamentum is positioned at the bottom of described emitter region; Be formed with emitter terminal hole at described groove or top, hole, the width in described emitter terminal hole is greater than the width in described groove or hole, is filled with metal and draws emitter in described groove or hole and described emitter terminal hole.
Further improvement is, the position in described groove or hole is positioned at described P well area central authorities, and grid described in the Edge Distance in described groove or hole is 1.5 μm ~ 3.5 μm, and the degree of depth in described groove or hole is 1 μm ~ 4 μm.
For solving the problems of the technologies described above, the manufacture method of igbt provided by the invention, comprises the steps:
Step one, bottom silicon substrate, form a P-type layer, described P-type layer composition collector region.
Step 2, in described P-type layer formed a N+ layer and a N-layer composition, the N-type impurity concentration of a described N+ layer is greater than the N-type impurity concentration of a described N-layer, a described N+ layer and described one N-layer composition drift region.
Step 3, in a described N-layer, form P trap.
Step 4, formation grid, P trap described in described grid cover part, the described P trap covered by described grid is channel region, and described channel region connects described drift region and the follow-up emitter region that will be formed.
Step 5, employing photoetching and etching technics carry out silicon etching and form groove or hole in described P trap.
Step 6, in the described P trap of the bottom in described groove or hole, carry out boron ion implantation and anneal, forming P+ articulamentum.
Step 7, form the 2nd N+ layer on described P trap top, form emitter region by described 2nd N+ layer, described P+ articulamentum is positioned at the bottom of described emitter region, and described emitter region and described drift region separate by described P trap.
Step 8, on described 2nd N+ layer, form a dielectric layer, and etch described dielectric layer and form emitter terminal hole, described emitter terminal hole is positioned at described groove or top, hole, and the width in described emitter terminal hole is greater than the width in described groove or hole; In described groove or hole and described emitter terminal hole, fill metal and draw emitter.
Further improvement is, the position in groove described in step 5 or hole is positioned at described P well area central authorities, and grid described in the Edge Distance in described groove or hole is 1.5 μm ~ 3.5 μm, and the degree of depth in described groove or hole is 1 μm ~ 4 μm.
Further improvement is, the ion implantation of boron described in step 6 can adopt different-energy, dosage repeatedly injects, and the angle of described boron ion implantation is 0 degree or 7 degree, implantation dosage is 1E14cm
-2~ 2E16cm
-2, Implantation Energy is 10kev ~ 200kev.Optimal selection is, the implantation dosage of described boron ion implantation is 1E15cm
-2~ 1E16cm
-2.
Further improvement is, the temperature of annealing described in step 6 is 900 DEG C ~ 1100 DEG C, the time is 10 points ~ 200 points.
Groove or hole that the present invention is less than the fairlead of emitter by forming a width in the P trap bottom the fairlead of emitter, and P+ articulamentum is formed bottom groove or hole.The present invention is relative to the first IGBT existing, and emitter directly can be deep into the inside of P trap thus directly draw P trap by metal, thus can reduce dead resistance between emitter and P trap, suppresses to hold up post effect.The present invention is relative to existing the second IGBT, width due to groove or hole and the degree of depth in groove or hole less than the silicon etching of the P trap of existing the second IGBT and all large than the corresponding size of the silicon etching of the P trap of existing the second IGBT from gate distance, thus the P+ articulamentum degree of depth of the present invention can be enable to be strengthened, thus dead resistance between emitter and P trap can be reduced too, suppress to hold up post effect.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the structural representation of the embodiment of the present invention one IGBT;
Fig. 2 is the structural representation of the first IGBT existing;
Fig. 3 is the structural representation of existing the second IGBT;
Fig. 4 is the equivalent circuit diagram of the first IGBT existing;
Fig. 5-Fig. 8 is the structural representation in each step of the manufacture method of the embodiment of the present invention one IGBT;
Fig. 9 is the structural representation of the embodiment of the present invention two IGBT.
Embodiment
As shown in Figure 1, be the schematic diagram of the embodiment of the present invention one igbt, the embodiment of the present invention one igbt comprises: collector region, is made up of the P-type layer 13 be formed at bottom silicon substrate, draws collector electrode from the back side of described silicon substrate.Drift region, is made up of the N+ layer 12 be formed at successively on described collector region and a N-layer 11, and the N-type impurity concentration of a described N+ layer 12 is greater than the N-type impurity concentration of a described N-layer 11.P trap 16, is formed in a described N-layer 11.Emitter region, be made up of the 2nd N+ layer 14 being formed at described P trap 16 top, described emitter region and described drift region separate by described P trap 16.Grid 21, for a kind of grid of longitudinal plough groove type, the channel shaped of described grid 21 is formed in a described N-layer 11, P trap 16 described in described grid 21 cover part, the described P trap 16 covered by described grid 21 is channel region, and described channel region connects the described drift region of described P trap 16 both sides and described emitter region.In described P trap 16, be formed with groove or hole, in the described P trap 16 of the bottom in described groove or hole, be formed with P+ articulamentum 15, described P+ articulamentum 15 is positioned at the bottom of described emitter region.Be formed with emitter terminal hole at described groove or top, hole, the width in described emitter terminal hole is greater than the width in described groove or hole, is filled with metal and draws emitter 24 in described groove or hole and described emitter terminal hole.Its midfield oxygen 22 is for the isolation between device, and dielectric layer 23 is for the isolation between metal level and device.Wherein, the position in described groove or hole is positioned at described P trap 16 region central authorities, and grid 21 described in the Edge Distance in described groove or hole is 1.5 μm ~ 3.5 μm, and the degree of depth in described groove or hole is 1 μm ~ 4 μm.
As shown in Figure 9, for the schematic diagram of the embodiment of the present invention two igbt, the grid 21a be distinguished as wherein of the embodiment of the present invention two igbt and the embodiment of the present invention two igbt is a kind of horizontal planarized structure, and the surface that described grid 21a is formed at described P trap 16 forms the channel region of a transverse direction from P trap 16 described in the surface coverage of described P trap 16.
As shown in Fig. 5 ~ Fig. 8, be the structural representation in each step of the manufacture method of the embodiment of the present invention one igbt, the manufacture method of the embodiment of the present invention one igbt comprises the steps:
Step one, as shown in Figure 5, form a P-type layer 13 bottom silicon substrate, described P-type layer 13 forms collector region.
Step 2, as shown in Figure 5, in described P-type layer 13, formation the one N+ layer 12 and a N-layer 11 form, the N-type impurity concentration of a described N+ layer 12 is greater than the N-type impurity concentration of a described N-layer 11, and a described N+ layer 12 and a described N-layer 11 form drift region.
Step 3, as shown in Figure 5, in a described N-layer 11, form P trap 16.
Step 4, as shown in Figure 5, forms grid 21, P trap 16 described in described grid 21 cover part, and the described P trap 16 covered by described grid 21 is channel region, and described channel region connects described drift region and the follow-up emitter region that will be formed.
Step 5, as shown in Figure 6, adopts photoetching and etching technics in described P trap 16, carry out silicon etching and forms groove or hole.The position in described groove or hole is defined by photoresist 26, and be positioned at described P trap 16 region central authorities, grid 21 described in the Edge Distance in described groove or hole is 1.5 μm ~ 3.5 μm, and the degree of depth in described groove or hole is 1 μm ~ 4 μm.
Step 6, as shown in Figure 7, carries out boron ion implantation and anneals, forming P+ articulamentum 15 in the described P trap 16 of the bottom in described groove or hole.Described boron ion implantation can adopt different-energy, dosage repeatedly injects, and the angle of described boron ion implantation is 0 degree or 7 degree, implantation dosage is 1E14cm
-2~ 2E16cm
-2, Implantation Energy is 10kev ~ 200kev.Optimal selection is, the implantation dosage of described boron ion implantation is 1E15cm
-2~ 1E16cm
-2.The temperature of described annealing is 900 DEG C ~ 1100 DEG C, the time is 10 points ~ 200 points.
Step 7, as shown in Figure 8, form the 2nd N+ layer 14 on described P trap 16 top, form emitter region by described 2nd N+ layer 14, described P+ articulamentum 15 is positioned at the bottom of described emitter region, and described emitter region and described drift region separate by described P trap 16.
Step 8, as shown in Figure 1, described 2nd N+ layer 14 forms a dielectric layer 23, and etch described dielectric layer 23 and form emitter terminal hole, described emitter terminal hole is positioned at described groove or top, hole, and the width in described emitter terminal hole is greater than the width in described groove or hole; In described groove or hole and described emitter terminal hole, fill metal and draw emitter 24.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (5)
1. a manufacture method for igbt, is characterized in that, comprises the steps:
Step one, bottom silicon substrate, form a P-type layer, described P-type layer composition collector region;
Step 2, in described P-type layer formed a N+ layer and a N-layer composition, the N-type impurity concentration of a described N+ layer is greater than the N-type impurity concentration of a described N-layer, a described N+ layer and described one N-layer composition drift region;
Step 3, in a described N-layer, form P trap;
Step 4, formation grid, P trap described in described grid cover part, the described P trap covered by described grid is channel region, and described channel region connects described drift region and the follow-up emitter region that will be formed;
Step 5, employing photoetching and etching technics carry out silicon etching and form groove or hole in described P trap;
Step 6, in the described P trap of the bottom in described groove or hole, carry out boron ion implantation and anneal, forming P+ articulamentum;
Step 7, form the 2nd N+ layer on described P trap top, form emitter region by described 2nd N+ layer, described P+ articulamentum is positioned at the bottom of described emitter region, and described emitter region and described drift region separate by described P trap;
Step 8, on described 2nd N+ layer, form a dielectric layer, and etch described dielectric layer and form emitter terminal hole, described emitter terminal hole is positioned at described groove or top, hole, and the width in described emitter terminal hole is greater than the width in described groove or hole; In described groove or hole and described emitter terminal hole, fill metal and draw emitter.
2. the manufacture method of igbt as claimed in claim 1, it is characterized in that: the position in groove described in step 5 or hole is positioned at described P well area central authorities, grid described in the Edge Distance in described groove or hole is 1.5 μm ~ 3.5 μm, and the degree of depth in described groove or hole is 1 μm ~ 4 μm.
3. the manufacture method of igbt as claimed in claim 1, it is characterized in that: the ion implantation of boron described in step 6 can adopt different-energy, dosage repeatedly injects, the angle of described boron ion implantation is 0 degree or 7 degree, implantation dosage is 1E14cm
-2~ 2E16cm
-2, Implantation Energy is 10kev ~ 200kev.
4. the manufacture method of igbt as claimed in claim 3, is characterized in that: the implantation dosage of described boron ion implantation is 1E15cm
-2~ 1E16cm
-2.
5. the manufacture method of igbt as claimed in claim 1, is characterized in that: the temperature of annealing described in step 6 is 900 DEG C ~ 1100 DEG C, the time is 10 points ~ 200 points.
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| CN201110165393.8A CN102842608B (en) | 2011-06-20 | 2011-06-20 | Insulated gate bipolar transistor and manufacturing method thereof |
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| CN102842608B true CN102842608B (en) | 2015-04-08 |
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| CN109427881A (en) * | 2017-08-23 | 2019-03-05 | 深圳尚阳通科技有限公司 | Trench gate mosfet and manufacturing method with shield grid |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0726602A2 (en) * | 1995-02-09 | 1996-08-14 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device |
| CN1525575A (en) * | 2003-02-26 | 2004-09-01 | �����Զ�����ʽ���� | High withstand voltage field effect type semiconductor device |
| CN101393857A (en) * | 2008-08-08 | 2009-03-25 | 成都方舟微电子有限公司 | Method for implementing well division construction in super-high density slot type power device design |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3971327B2 (en) * | 2003-03-11 | 2007-09-05 | 株式会社東芝 | Insulated gate semiconductor device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0726602A2 (en) * | 1995-02-09 | 1996-08-14 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device |
| CN1525575A (en) * | 2003-02-26 | 2004-09-01 | �����Զ�����ʽ���� | High withstand voltage field effect type semiconductor device |
| CN101393857A (en) * | 2008-08-08 | 2009-03-25 | 成都方舟微电子有限公司 | Method for implementing well division construction in super-high density slot type power device design |
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